SAME

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, perpendicular spin transfer torque memory (pSTTM) devices with a non- stoichiometric tantalum nitride bottom electrode and methods to form the same. BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovation in material technology to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with pSTTM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a pSTTM stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, improving magnetic properties of layers that result in higher performing pSTTM devices are some important areas of development. As such, improvements are still needed in the areas of pSTTM stack development that will contribute to improving magnetic properties. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a cross-sectional view of a perpendicular STTM (pSTTM) device, in accordance with an embodiment of the present disclosure.

Figure 2 illustrates a cross-sectional view of a perpendicular STTM (pSTTM) device disposed on a conductive interconnect, in accordance with an embodiment of the present disclosure.

Figures 3 A-3F illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM device, in accordance with an embodiment of the present disclosure.

Figure 3 A illustrates a cross-sectional view of the formation of a conductive interconnect, a seed layer on the conductive interconnect and a bottom electrode layer on the seed layer.

Figure 3B illustrates a cross-sectional view of the structure in Figure 3 A following the formation of barrier layer on the bottom electrode layer, in accordance with an embodiment of the present disclosure.

Figure 3C illustrates a cross-sectional view of the structure in Figure 3B following the formation of various layers to complete formation of a pSTTM material layer stack.

Figure 3D illustrates a cross-sectional view of the structure in Figure 3C following partial patterning of the pSTTM material layer stack.

Figure 3E illustrates a cross-sectional view of the structure in Figure 3D following the formation of a dielectric spacer layer on sidewalls of the partially patterned pSTTM material layer stack.

Figure 3F illustrates a cross-sectional view of the structure in Figure 3E following the formation of a dielectric spacer and following completion of patterning of the pSTTM material layer stack to form a pSTTM device.

Figure 4A illustrates a cross-sectional view of a synthetic antiferromagnetic structure including a trilayer, in accordance with an embodiment of the present disclosure.

Figure 4B illustrates a cross-sectional view of a synthetic antiferromagnetic structure including a repeated bilayer stack, in accordance with an embodiment of the present disclosure.

Figure 5A illustrates a cross-sectional view of the structure in Figure 3D following further patterning of the pSTTM material layer stack to form a pSTTM device. Figure 5B illustrates a cross-sectional view of the structure in Figure 5 A following the formation of a dielectric spacer on sidewalls of the patterned pSTTM material layer stack.

Figure 6 illustrates a cross-sectional view of a pSTTM device formed on a conductive interconnect coupled to a transistor, in accordance with an embodiment of the present disclosure.

Figure 7 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 8 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Perpendicular spin transfer torque memory (pSTTM) device with an enhanced bottom electrode and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

A pSTTM device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. The resistance state of a pSTTM device is defined by the relative orientation of magnetization between a free magnetic layer and a fixed magnetic layer that are separated by a tunnel barrier. When the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that are in the same direction the pSTTM device is said to be in a low resistance state. Conversely, when the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that are in opposite directions, the pSTTM device is said to be in a high resistance state. In an embodiment, resistance switching is brought about by passing a critical amount of spin polarized current through the pSTTM device so as to influence orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need power to retain relative orientation of magnetization, the resistance state of the pSTTM device is retained even when there is no power applied to the pSTTM device. For this reason, pSTTM belongs to a class of memory known as non-volatile memory.

Integrating a non-volatile memory device such as an STTM device onto an access transistor enables the formation of embedded memory for system on chip or for other

applications. However, approaches to integrate an STTM device onto an access transistor presents challenges that have become far more formidable with scaling. Examples of such challenges range from improving a pinned layer or a fixed magnetic layer characteristics without sacrificing thermal stability or increasing thickness of the free magnetic layer. As scaling continues, the need for smaller memory devices to fit into a scaled cell size has driven the industry in the direction of adopting a "perpendicular" STTM (pSTTM) device. The word "perpendicular" in pSTTM devices refers to fact that magnetic dipoles in the free and fixed magnets are directed perpendicular to a plane of a substrate above which the pSTTM device is formed. While pSTTM devices can be scaled to fabricate smaller devices, the thickness of the fixed magnetic layer and the free magnetic layers must also be scaled to maintain perpendicular magnetic anisotropy or perpendicular magnetism. In some instances, when the free and fixed magnetic layers have perpendicular magnetic anisotropy that is similar in magnitude, the fixed magnetic layers needs to pinned to a particular orientation for the pSTTM device to function. Insertion of a synthetic antiferromagnetic (SAF) structure below and magnetically coupled with the fixed layer helps to pin the fixed magnetic layer in a given magnetic direction. However, the antiferromagnetic coupling of the SAF structure depends on the crystal structure of the constituent materials. In an embodiment, an electrode layer upon which the SAF structure is formed (bottom electrode) can influence the crystalline texture, grain size, roughness, and other material properties relevant for optimal magnetic performance. In an embodiment, a bottom electrode which does not lattice match to a lowermost layer of a SAF structure, but includes a material that promotes a favorable texture for the formation of a SAF structure with strong perpendicular magnetic anisotropy is highly advantageous for pSTTM functionality.

In accordance with embodiments of the present disclosure, a material layer stack for a pSTTM device includes a bottom electrode that is a non-stoichiometric tantalum nitride layer that exhibits the characteristics required for forming a SAF structure with strong perpendicular magnetic anisotropy (PMA). While such a bottom electrode is in itself favorable for forming a SAF structure, non-stoichiometry favors the formation of a SAF layer with a higher degree of PMA. Additionally, varying the level of the nitrogen non-stoichiometry changes the texture of the bottom electrode which can in turn give rise to a greater degree of flexibility in the variety of layers utilized in the SAF structure. In an embodiment, there are manufacturing benefits for a using non-stoichiometric material. Improved PMA can enable stronger pinning fields for improved pSTTM device stability, i.e. reduced susceptibility to erroneous fluctuations in the magnetization of the fixed magnetic layer direction due to external magnetic fields. Large PMA in pinning layers in a pSTTM device enables use of a free magnetic layer that can withstand a sufficiently large external magnetic field without becoming demagnetized. In this context a sufficiently large external magnetic field is one that can exert a torque on the magnetization of a free layer that is significantly greater than the spin torque transfer effect brought about by passing current in a pSTTM device.

In an embodiment, the pSTTM device further includes a SAF structure disposed above the bottom electrode. Depending on the level of non-stoichiometry of the TaN bottom electrode layer, the SAF structure includes a trilayer stack with a non-magnetic layer disposed between two magnetic layers or a multilayer stack including bilayers having alternating layers of magnetic and non-magnetic materials. In an embodiment, the multilayer stack includes repeating layers of magnetic and non-magnetic materials. A fixed magnet is disposed above the SAF structure and lattice matched to a tunnel barrier disposed directly above. The tunnel barrier for optimization of tunnel magnetoresi stance ratio includes a material such as but not limited to MgO and AI2O3. A free magnet is disposed above the tunnel barrier. The free magnet includes a material that is similar to a material of the fixed magnet or include a material that is substantially different as long as the free magnet has perpendicular magnetic anisotropy (PMA). The free magnet should also be susceptible to change in direction of magnetization by an action of a torque imposed by a stream of spin polarized electrons. In an embodiment, a top electrode is disposed above the free magnet. In alternative embodiments, two or more layers of non- magnetic and magnetic materials may be disposed between the free magnet and the top electrode to enhance the perpendicularity of the free magnetic layer.

Figure 1 illustrates a cross-sectional illustration of a pSTTM device 100. pSTTM device 100 includes a bottom electrode 102 having a non-stoichiometric tantalum nitride layer, a synthetic antiferromagnetic (SAF) structure 104 is disposed on the bottom electrode 102, a non- magnetic spacer 105 is disposed on the SAF structure 104, a fixed magnet 106 is disposed on the non-magnetic spacer 105, a tunnel barrier 108 is disposed on the fixed magnet 106, a free magnet 110 is disposed on the tunnel barrier 108 and a top electrode 114 is disposed above the free magnet 110.

The bottom electrode 102 includes a material that promotes ferromagnetic coupling between the SAF structure 104 and the fixed magnet 106. In an embodiment, the bottom electrode 102 has a chemical composition Taioo-xN _x , where X and Y each represent an atomic percent. In an embodiment, X is greater than or equal to 10 and less than or equal to 50. In an embodiment, X is 10. In an embodiment, X is 50. In an embodiment, the bottom electrode 102 is a non-stoichiometric tantalum nitride layer that is amorphous in texture. In one specific embodiment, the bottom electrode 102 is a non-stoichiometric tantalum nitride layer that is polycrystalline in texture. In one embodiment, the bottom electrode 102 is a non-stoichiometric tantalum nitride layer, Taioo-xN _x , where X is between 40 and 50. In an embodiment, a non- stoichiometric tantalum nitride layer where X is between 40 and 50 has a face center cubic (FCC) (111) crystal orientation. In one embodiment, the bottom electrode 102 is a non- stoichiometric tantalum nitride layer, Taioo-xN _x , where X is between 11 and 30. In an

embodiment, a non-stoichiometric tantalum nitride layer, Taioo-xN _x , where X is between 11 and 30 has Alpha-Ta phase (110) crystal orientation. In an embodiment, the bottom electrode 102 has a thickness between 2nm-20nm.

The SAF structure 104 is disposed between the bottom electrode 102 and the fixed magnet 106 in order to pin a magnetization of the fixed magnet 106. In a perpendicular magnetic system, a SAF structure 104 helps to fix a magnetization of the fixed magnet 106 by

ferromagnetically coupling with the fixed magnet 106. In an embodiment, the SAF structure 104 includes a non-magnetic layer 104B between a first ferromagnetic layer 104 A and a second ferromagnetic layer 104C as depicted in the cross-sectional illustration of Figure 1. The first ferromagnetic layer 104 A and the second ferromagnetic layer 104C are anti -ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 104 A has a direction of magnetization 150 and the second ferromagnetic layer 104C has a direction of magnetization 152 (as indicated by arrows). When the direction of magnetization 150 in the first ferromagnetic layer 104A is opposite to the direction of magnetization 152 in the second ferromagnetic layer

104C as is depicted in the cross-sectional illustration of Figure 1, the first ferromagnetic layer

104 A and the second ferromagnetic layer 104C are anti-ferromagnetically coupled.

In an embodiment, the first ferromagnetic layer 104A includes a layer of a magnetic metal such as Co, Ni, Fe. In an embodiment, the first ferromagnetic layer 104 A includes an alloy such as CoFe, CoFeB or FeB. In an embodiment, the first ferromagnetic layer 104 A of the

SAF structure 104 is lattice matched to the bottom electrode 102 having a non-stoichiometric tantalum nitride layer. In an embodiment, the first ferromagnetic layer 104 A has a thickness between 0.5nm-1.2nm.

In an embodiment, the non-magnetic layer 104B includes a ruthenium or an iridium layer. In an embodiment, a ruthenium based non-magnetic layer 104B has a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnetic layer 104 A and the second ferromagnetic layer 104C is antiferromagnetic in nature.

In an embodiment, the second ferromagnetic layer 104C includes a layer of a magnetic metal such as Co, Ni, Fe. In an embodiment, the second ferromagnetic layer 104C includes an alloy such as CoFe, CoFeB or FeB. In an embodiment, the second ferromagnetic layer 104C has a thickness between 1.Onm-1.5nm.

In an alternative embodiment, the SAF structure 104 includes one or more bilayers of a magnetic material on a non-magnetic metal such as a bilayer of Co/Pd or a bilayer of Co/Pt (not shown). In an embodiment, total number of bilayers can range from 2-20.

In an embodiment, an ultra-thin non-magnetic spacer 105 is disposed on the SAF structure 104 as illustrated in Figure 1. In an embodiment, when the SAF structure 104 includes a second ferromagnetic layer 104C, a layer of non-magnetic spacer 105 enables anti- ferromagnetic coupling between the second ferromagnetic layer 104C and a fixed magnet 106 directly above. In an embodiment, the layer of non-magnetic spacer 105 may include metals such as Ru or Ir. In an embodiment, the thickness of the layer of non-magnetic spacer material is between 0.1nm-3.0nm.

Referring again to Figure 1, in an embodiment, the fixed magnet 106 includes cobalt, boron and iron. In an embodiment, the fixed magnet 106 of the pSTTM device 100 includes an alloy such as CoFe or CoFeB. In an embodiment, the fixed magnet 106 includes a layer of

Coioo-x-yFe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 106 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In other embodiments, fixed magnet 106 further includes magnetic alloys of Ni. In an embodiment the fixed magnet 106 has a thickness that is between 1.5nm-2.5nm. In an embodiment, the fixed magnet 106 having a thickness between 1.5nm and 2.5nm results in the fixed magnet 106 having a perpendicular magnetic anisotropy.

Referring again to Figure 1, in an embodiment, the tunnel barrier 108 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 108, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 108. Thus, the tunnel barrier 108 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 108 includes an oxide such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 108 is MgO and has a thickness between lnm to 2nm.

In an embodiment, the free magnet 110 includes cobalt, boron and iron. In an

embodiment, the free magnet 110 of the pSTTM device 100 includes an alloy such as CoFe or CoFeB. In an embodiment, the free magnet 110 includes a layer of Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnet 110 is FeB, where the concentration of boron is between

10-40 atomic percent of the total composition of the FeB alloy. In an embodiment the free magnet 110 has a thickness that is between lnm-2.5nm. In an embodiment, free magnet 110 having a thickness between l.Onm and 2.5nm results in the free magnet 110 having a

perpendicular magnetic anisotropy.

In an embodiment, the pSTTM device 100 further includes a top electrode 114 disposed above the free magnet 110 as illustrated in Figure 1. In an embodiment, the top electrode 114 includes a material such as Ta or TiN. In an embodiment, the top electrode 114 has a thickness between 30nm-70nm.

Figure 2 illustrates a cross-sectional view of a pSTTM device 200 disposed above a conductive interconnect 226, in accordance with an embodiment of the present disclosure. The pSTTM device 200 includes a seed layer 202, a bottom electrode 204 comprising a non- stoichiometric tantalum nitride layer, a barrier layer 206 above the bottom electrode 204, a perpendicular magnetic tunnel junction (pMTJ) 208 including a synthetic antiferromagnetic (SAF) structure 210 above the barrier layer 206, a non-magnetic spacer layer 212 above the SAF structure 210, a fixed magnet 214 above the non-magnetic spacer layer 212, a tunnel barrier 216 above the fixed magnet 214, a free magnet 218 above the tunnel barrier 216. The pSTTM device 200 further includes an oxide layer 220 above the free magnet 218, a magnetic follower layer 222 above the oxide layer 220 and a top electrode 224 above the magnetic follower layer 222.

In an embodiment, the seed layer 202 includes one or more layers of metals such as but not limited to ruthenium and tantalum. The seed layer 202 is disposed on a conductive interconnect 226 and on a portion of a dielectric layer 228 surrounding the conductive interconnect 226. In an embodiment, seed layer 202 has a thickness that is between 5nm-10nm.

The bottom electrode 204 includes a material that promotes ferromagnetic coupling between the SAF structure 210 and the fixed magnet 214. In an embodiment, the bottom electrode 204 has a chemical composition Taioo-xN _x , where X and Y each represent an atomic percent. In an embodiment, X is greater than or equal to 10 and less than or equal to 50. In an embodiment, X is 10. In an embodiment, X is 50. In an embodiment, the bottom electrode 204 is a non-stoichiometric tantalum nitride layer that is amorphous in texture. In one specific embodiment, the bottom electrode 204 is a non-stoichiometric tantalum nitride layer that is polycrystalline in texture. In one embodiment, the bottom electrode 204 is a non-stoichiometric tantalum nitride layer, Taioo-xN _x , where X is between 40 and 50. In an embodiment, a non- stoichiometric tantalum nitride layer where X is between 40 and 50 has a face center cubic (FCC) (111) crystal orientation. In one embodiment, the bottom electrode 204 is a non- stoichiometric tantalum nitride layer, Taioo-xN _x , where X is between 11 and 30. In an embodiment, a non-stoichiometric tantalum nitride layer, Taioo-xN _x , where X is between 11 and 30, has an Alpha-Ta (110) crystal orientation. In an embodiment, the bottom electrode 204 has a thickness between 2nm-20nm.

Referring again to Figure 2, the barrier layer 206 includes one or more layers of a metal selected from the group consisting of Ta, Ru and Pt. In an embodiment, the barrier layer 206 includes a lowermost layer of Ta, and an uppermost layer including ruthenium on the layer of tantalum. In an embodiment, the barrier layer 206 has a thickness between 2.0nm-3.0nm. In an embodiment, an uppermost surface of the barrier layer 206 has a surface roughness of 0.5nm or less.

In an embodiment, the SAF structure 210 is a SAF structure similar to or substantially similar to SAF structure 104.

In an embodiment, the non-magnetic spacer layer 212 is the same or substantially the same as the non-magnetic spacer 105. In an embodiment, the fixed magnet 214 is the same or substantially the same as the fixed magnet 106 and has a thickness between 1.5nm-2.5nm to maintain perpendicular anisotropy. In an embodiment, the tunnel barrier 216 is the same or substantially the same as the tunnel barrier 108 and includes a material such as MgO. The free magnet 218 is the same or substantially the same as the free magnet 110 and has a thickness between l .Onm and 2.5nm to maintain perpendicular anisotropy.

In an embodiment, the pSTTM device 200 further includes an oxide layer 220 disposed above the free magnet 218. In an embodiment, when a free magnet 218 includes iron, the oxide layer 220 provides a source of oxygen that enables oxygen-iron hybridization at an interface 230 located between an uppermost surface of the free magnet 218 and a lowermost surface of the oxide layer 220. Oxygen-iron hybridization at the interface 230 can enable a high interfacial perpendicular magnetic anisotropy in the free magnet 218. In an embodiment, the oxide layer

220 is MgO. In an embodiment, the oxide layer 220 has a thickness that is between 0.3nm-

0.7nm. In an embodiment, the oxide layer 220 has a thickness that is less than the thickness of the tunnel barrier 216. An oxide layer 220 having a thickness of less than 0.8nm is sufficiently thin to allow electron current to flow through the pSTTM device 200.

Referring again to Figure 2, the pSTTM device 200 further includes a follower magnetic layer 222 disposed above the oxide layer 220. In an embodiment, the follower magnetic layer 222 includes an alloy such as but not limited to CoFe or CoFeB. In an embodiment the follower magnetic layer 222 is CoFeB. In an embodiment, the follower magnetic layer 222 is

magnetically coupled to the free magnet 218 to form a coupled system of switching magnetic layers. In an embodiment, the follower magnetic layer 222 has a weaker perpendicular magnetic anisotropy than the perpendicular magnetic anisotropy of the free magnet 218. A follower magnetic layer 222 having a weaker perpendicular magnetic anisotropy undergoes current induced magnetization switching more easily than a free magnet 218 having a stronger perpendicular magnetic anisotropy. In an embodiment, the follower magnetic layer is magnetically dead.

In an embodiment, the follower magnetic layer 222 has a thin uppermost portion that can be non-magnetic. In such an embodiment, the follower magnetic layer 222 has a material composition and thickness sufficient for perpendicular magnetic anisotropy and to remain magnetically coupled to the free magnet 218. In an embodiment, the follower magnetic layer 222 has a thickness between 0.6nm-2.0nm. In an embodiment, a CoFeB follower magnetic layer

222 having a thickness of at least 0.6nm is sufficiently thick to possess perpendicular magnetic anisotropy.

Referring again to Figure 2, in an embodiment, the top electrode 224 is the same or substantially the same as the top electrode 114.

Referring again to Figure 2, the conductive interconnect structure 201 includes the conductive interconnect 226 disposed in a dielectric layer 228. Portions of the conductive interconnect 226 may be electrically coupled (not shown) with a drain contact disposed above a drain region of a transistor. The conductive interconnect 226 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the dielectric layer 228 includes a dielectric layer such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. As illustrated in Figure 2, the pSTTM device 200 has a width, WPSTTM, and the conductive interconnect 226 has a width Wei. In an embodiment, the pSTTM device 200 has a width, WPSTTM, that is less that the width Wei, of the conductive interconnect 226. In an embodiment, the pSTTM device 200 has a width, WPSTTM, that is greater that the width Wei, of the conductive interconnect 226. In another embodiment, the pSTTM device 200 has a width, WPSTTM, that is similar to the width Wei, of the conductive interconnect 226. In an embodiment, the substrate 250 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 250 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 250. Logic devices such as access transistors may be integrated with memory devices such as pSTTM device 200 to form embedded memory. Embedded memory including pSTTM devices and logic MOSFET transistors can be combined to form functional integrated circuit such as a system on chip. Figures 3 A-3F illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM device, in accordance with an embodiment of the present disclosure.

Figure 3A illustrates a conductive interconnect 302 surrounded by a dielectric layer 301 formed above a substrate 300, the formation of a seed layer 303 on the conductive interconnect 302, and the formation of a bottom electrode layer 305 on the seed layer 303. In an embodiment, the conductive interconnect 302 is formed in a dielectric layer 301 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 302 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the conductive interconnect 302 is fabricated using a subtractive etch process when materials other than copper are utilized. In an embodiment, the dielectric layer 301 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 301 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 302. In an embodiment, the dielectric layer 301 has a total thickness between 70nm-300nm. In an embodiment, conductive interconnect 302 is electrically connected to a circuit element such as a transistor (not shown).

In an embodiment, the seed layer 303 is blanket deposited onto an uppermost surface of the conductive interconnect 302 and onto an uppermost surface of the dielectric layer 301. In an embodiment, the seed layer 303 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, forming the seed layer 303 includes depositing one or more layers of metals such as but not limited to ruthenium and tantalum or an alloy such as TiN. In an embodiment, a thin layer of tantalum is deposited on a thin layer of ruthenium. In an embodiment, seed layer has a thickness that is between 5nm-10nm. In an embodiment the seed layer 303 is first blanket deposited and subsequently polished to achieve a surface roughness of lnm or less. In an embodiment, when a seed layer 303 is first blanket deposited and subsequently polished, the seed layer 303 is first deposited to a thickness between 20nm-50nm, and then polished to a thickness between lOnm- 40nm.

In an embodiment, the bottom electrode layer 305 is blanket deposited onto an uppermost surface of the seed layer 303. In an embodiment, the bottom electrode layer 305 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. The bottom electrode layer 305 includes a material that promotes ferromagnetic coupling between SAF structure and a fixed magnet to be subsequently deposited in a further operation. In an embodiment, the bottom electrode layer 305 is a non-stoichiometric tantalum nitride layer that is amorphous as deposited. In one specific embodiment, the bottom electrode layer 305 is a non-stoichiometric tantalum nitride layer that is polycrystalline as deposited. In an embodiment, the bottom electrode layer 305 has a chemical composition Tai- xNx, where X and Y each represent an atomic percent. In an embodiment, the deposition of the bottom electrode layer 305 is performed by sputtering tantalum onto the conductive interconnect and reacting the sputtered tantalum with a nitrogen gas (N ₂ ) to form a bottom electrode layer 305 having a chemical composition Tai- _X N _X . In an embodiment, the nitrogen gas is flowed at a constant rate, where the rate is adjusted to obtain a desired nitrogen stoichiometry in the Tai- _X N _X material. In an embodiment, X is greater than or equal to 10 and less than or equal to 50. In an embodiment, X is 10. In an embodiment, X is 50. When X is 50, the Tai _-X N _X bottom electrode layer 305 is amorphous in texture. In an embodiment, when X is between 40 and 50, the Tai _-X N _X bottom electrode layer 305 has a face center cubic (FCC) (111) TaN phase crystal structure. In an embodiment, when X is 5-10 the Tai _-x N _x bottom electrode layer 305 has an Alpha-Ta with (110) crystal orientation. In an embodiment, when X is 10-50 the Tai _-X N _X bottom electrode layer 305 is polycrystalline with TaN and Ta metal crystallites. In an embodiment, when X is 10-50 the Tai- _x N _x bottom electrode layer 305 is amorphous. In an embodiment, the bottom electrode layer 305 is deposited to a thickness between 2nm-20nm. In an embodiment the bottom electrode layer 305 is first blanket deposited on the seed layer 303 and subsequently polished to achieve a surface roughness of lnm or less. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process to form a topographically smooth uppermost surface having a surface roughness of less than lnm. A surface roughness of less than lnm is sufficient to enable a subsequent fixed magnetic layer and a tunnel barrier layer to be formed with well-ordered crystal planes. In an embodiment, the planarization process removes 5nm-10nm of bottom electrode material. In one such

embodiment, the as-deposited thickness of the bottom electrode layer 305 is between 7nm-30nm. In another embodiment, when a seed layer 303 is first blanket deposited and subsequently polished, the bottom electrode layer 305 is an ultra-thin layer of Tai- _X N _X . In an embodiment, an ultra-thin Tai- _x N _x has a thickness between lnm-5nm. In one embodiment, the ultra-thin layer of Tai- _X N _X does not significantly degrade the surface roughness relative to the polished seed layer 303.

In an embodiment, the substrate 300 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 300 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-V or a group III-N compound.

Figure 3B illustrates a cross-sectional view of the structure in Figure 3 A following the formation a barrier layer 307 and partial etch back of the barrier layer 307 in accordance with an embodiment of the present disclosure.

In an embodiment, the barrier layer 307 is deposited on the bottom electrode layer 305. In an embodiment, a barrier layer 307 is deposited on the bottom electrode layer 305 that has been planarized. In an embodiment, the barrier layer 307 is blanket deposited using a physical vapor deposition (PVD) process. In an embodiment, the barrier layer 307 includes one or more layers of metals selected from the group consisting of Ta, Ru and Pt. In an embodiment, the barrier layer 307 includes a lowermost layer of tantalum, and an uppermost layer including ruthenium on the layer of tantalum. In an embodiment, the barrier layer 307 has a thickness between 2.0nm-3.0nm. In an embodiment, the uppermost surface of the barrier layer 307 has a surface roughness of 0.5nm or less.

In an embodiment, prior to depositing a SAF structure, an etch back of the barrier layer 307 is performed. In an embodiment, the etched back portion 307A includes an Ar sputter clean.

In an embodiment, the Ar sputter clean removes 0.8nm-1.0nm of the as deposited barrier layer

307. In an embodiment, the Ar sputter clean is carried out in the same tool as where the SAF structure 309 is to be deposited, and no air break is performed after the sputter clean and prior too deposition of the SAF structure.

Figure 3C illustrates a cross-sectional view of the structure in Figure 3B following the formation of various layers of a material layer stack for a pSTTM device, in accordance with an embodiment of the present disclosure. In an embodiment, a SAF structure 309 is deposited on the partially etched back barrier layer 307. In an embodiment, forming the SAF structure 309 includes sequentially depositing individual layers of a trilayer stack. An exemplary embodiment of a trilayer stack is illustrated in Figure 4A. The trilayer stack includes a first ferromagnetic layer 341, a non-magnetic layer 342 deposited on the first ferromagnetic layer 341 and a second ferromagnetic layer 343 deposited on the non-magnetic layer 342. In an embodiment, the trilayer stack is deposited by a PVD process.

In an embodiment, the first ferromagnetic layer 341 includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe. In an embodiment, the first ferromagnetic layer 341 has a thickness between 0.5nm-1.2nm. In an embodiment, the second ferromagnetic layer 343 includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe. In an embodiment, the second ferromagnetic layer 342 has a thickness between 1.0nm-1.5nm. In an embodiment, the first ferromagnetic layer 341 has a thickness that is less than the thickness of the second ferromagnetic layer 342. In an embodiment, the non-magnetic layer 342 includes a ruthenium or an iridium layer.

In an embodiment, a ruthenium based non-magnetic layer 342 has a thickness between 4-9

Angstroms to ensure that the coupling between the first ferromagnetic layer 341 and the second ferromagnetic layer 343 is antiferromagnetic in nature.

In another embodiment, the SAF structure 309 includes a stack of bilayers 350 to increase the perpendicular anisotropy of the SAF structure 309. In an embodiment, each bilayer stack 350 includes a layer of a non-magnetic material 350A deposited on a layer of a magnetic material 350B. In an embodiment, each bilayer stack 350 is deposited by a PVD process. In an embodiment, the SAF structure 309 includes a stack of 4-10 bilayers. By forming a stack of bilayers the interfacial perpendicular anisotropy of the SAF structure 309 can be increased. In an embodiment, the layer of magnetic material 350B includes a Co and the layer of non-magnetic material 350A includes a Pt or Pd. In an embodiment, the bilayer 350 includes Co/Pd bilayer or a Co/Pt bilayer. In an embodiment, the magnetic material 350B has a thickness between 0.2nm- 0.6nm and the non-magnetic material 350A has a thickness between 0.15nm-0.35nm.

A non-magnetic spacer layer 311 is deposited on the SAF structure 309. In an embodiment, the non-magnetic spacer layer 311 is blanket deposited by a PVD process. In an embodiment, the non-magnetic spacer layer 311 has a thickness between 0.15nm-0.4nm. The non-magnetic spacer layer 311 enables antiferromagnetic coupling between the SAF structure 309 and a fixed magnetic layer to be formed above.

A fixed magnetic layer 313 is deposited on the non-magnetic spacer layer 311. In an embodiment, the fixed magnetic layer 313 is blanket deposited using a physical vapor deposition (PVD) process. In an embodiment, a fixed magnetic layer 313 deposited by a PVD process is amorphous in nature. In an embodiment, the fixed magnetic layer 313 includes an alloy such as but not limited to CoFe, CoFeB and FeB. In an embodiment, fixed magnetic layer 313 includes a Coi-x-yFe _x By, where X and Y each represent atomic percent. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the fixed magnetic layer 313 is blanket deposited to a thickness between lnm-2.5nm. The PVD deposition process ensures that the fixed magnetic layer 313 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate.

A tunnel barrier layer 315 is then blanket deposited on the fixed magnetic layer 313. In an embodiment, the tunnel barrier layer 315 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 315 is a layer of MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room

temperature. In an embodiment, reactive sputter process is carried out at elevated temperatures between 200-400C. In an embodiment, tunnel barrier layer 315 is a layer of MgO and is RF sputtered from a MgO target. In an embodiment, tunnel barrier layer 315 is a layer of MgO and is formed by a reactive oxidation of DC sputtered Mg films.

In an embodiment, the MgO is deposited to a thickness between 0.8nm to lnm. In an embodiment, the reactive sputter deposition process is carried out in a manner that yields a tunnel barrier layer 315 having a mostly crystalline structure. In another embodiment, the tunnel barrier layer 315 is not crystalline as deposited but becomes highly crystalline after an anneal process.

A free magnetic layer 317 is then deposited on the tunnel barrier 315. In an embodiment, the free magnetic layer 317 is blanket deposited using a PVD process. In an embodiment, the process is carried out at room temperature. In an embodiment, the free magnetic layer 317 includes an alloy such as but not limited to CoFe, CoFeB and FeB. In an embodiment, the free magnetic layer 317 is formed by a co-sputter depositing iron, boron and cobalt in a PVD chamber. In one embodiment, the free magnetic layer 317 includes a Coi-x-yFe _x By, where X and Y each represent atomic percent. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the free magnetic layer 317 is blanket deposited to a thickness between lnm- 2.5nm. The PVD deposition process ensures that the free magnetic layer 317 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate. The oxide layer 319 is formed on the uppermost surface of the free magnetic layer 317 to increase the interfacial perpendicular magnetic anisotropy of the pSTTM material layer stack 330. In an embodiment, the oxide layer 319 is deposited using a process that is substantially similar to the process of depositing the tunnel barrier layer 315. In an embodiment, the oxide deposition process includes depositing a layer of metal onto an uppermost surface of the free magnetic layer 317 and then oxidizing the layer of metal to form the oxide layer 319. In an embodiment, the oxidation process creates an oxide layer 319 that is not crystalline compared to a crystalline oxide layer 319 formed by a reactive co-sputter process. However, unlike the tunnel barrier layer 315, the oxide layer 319 does not act as a spin filter but acts rather as a conductive layer. In an embodiment, an oxide layer 319 formed by a metal deposition followed by an oxidation process is sufficiently conductive. In an embodiment, a metal such as magnesium is first sputter deposited onto the surface of the free magnetic layer 317. In an embodiment, the process includes a DC sputter deposition carried out at ambient temperatures of less than 300K. In an embodiment, the process includes a DC sputter deposition is carried out at temperatures between 200-400C. In an embodiment, an oxidation process is carried out to oxidize the as- sputtered magnesium metal. In an embodiment, the oxidation process includes subjecting the first metal to an 0 ₂ gas at a pressure between 3mtorr-750mtorr. In an embodiment, the oxide layer 319 is deposited to a thickness between 0.3nm-0.7nm.

In an embodiment, the follower magnetic layer 321 is blanket deposited on the uppermost surface of the oxide layer 319. In an embodiment, the follower magnetic layer 321 is the same or substantially the same as the free magnetic layer 317. In an embodiment, the deposition process includes a physical vapor deposition (PVD) process. The follower magnetic layer 321 is deposited with a material and having a thickness where the perpendicular magnetic anisotropy of the follower layer is not greater than perpendicular magnetic anisotropy of the free magnetic layer 317. In an embodiment, the free magnetic layer 317 has a thickness between 0.5nm-0.9nm.

In an embodiment, the top electrode layer 323 is blanket deposited on the surface of the follower magnetic layer 321. In an embodiment, the top electrode layer 323 includes a material suitable to provide a hardmask for etching the pSTTM material layer stack 330 to form a pSTTM device. In an embodiment, the top electrode layer 323 includes a material such as Ta. In an embodiment, the thickness of the top electrode layer 323 ranges from 30nm-70nm. The thickness is chosen to accommodate the various sizes of the pSTTM devices that will subsequently be fabricated as well as to provide etch resistivity during etching of the pSTTM material layer stack 330.

In an embodiment, after all the layers in the pSTTM material layer stack 330 are deposited, an anneal is performed under conditions well known in the art to promote solid phase epitaxy of the free magnetic layer 317 following a template of a crystalline layer of the tunnel barrier layer 315. A post-deposition anneal of the pSTTM material layer stack 330 is carried out in a furnace at a temperature between 300-500 degrees Celsius in a forming gas environment. In an embodiment, the anneal is performed immediately post deposition but before patterning of the pSTTM material layer stack 330 to enable a crystalline MgO-tunnel barrier layer 315 to be formed. The post-deposition anneal process also enables boron to diffuse away from an interface 325 between the tunnel barrier layer 315 and the free magnetic layer 317. The process of diffusing boron away from the interface enables lattice matching between the free magnetic layer 317 and the tunnel barrier layer 315.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 313 and the free magnetic layer 317. An applied magnetic field that is directed parallel to the vertical axis of the pSTTM material layer stack 330, during the annealing process, enables a perpendicular magnetic anisotropy to be set in the fixed magnetic layer 313 and in the free magnetic layer 317. The annealing process initially aligns the magnetization of the fixed magnetic layer 313 and the free magnetic layer 317 to be parallel to each other.

Figure 3D illustrates a cross-sectional view of the structure in Figure 3C following an etch process to form a patterned portion 332 of the pSTTM material layer stack 330. In an embodiment, a layer photoresist (not shown) is formed above the top electrode layer 323. In an embodiment, the photoresist is patterned using well known lithographic processes known in the art. The lithography process defines the shape and size of a pSTTM device and a location where the pSTTM device is to be formed with respect the conductive interconnect 302. In an embodiment, the top electrode layer 323 is first patterned by a plasma etch process to form a top electrode 324. In an embodiment, the top electrode 324 is utilized to act as a hardmask for patterning the remaining portion of the pSTTM material layer stack 330. In an embodiment, the etch is halted once an uppermost surface of the bottom electrode layer 305 is exposed.

In an embodiment, the plasma etch process forms a magnetic follower 322, an oxide layer

320, a free magnet 318, a tunnel barrier 316, a fixed magnet 314, patterned spacer layer 312, a synthetic antiferromagnet 310 and a patterned barrier layer 308. In an embodiment, the magnetic follower 322 is magnetic as deposited but magnetically dead at the end of the patterning process. In an embodiment, almost 30-50% of the as deposited top electrode layer 323 may be consumed during the complete etch process. In an embodiment, the plasma etch patterns a portion of the pSTTM material layer stack 330 with a tapered profile (indicated by dashed lines 360). While a highly energetic plasma etch can produce a vertical profile of a portion of the pSTTM material layer stack 330, a tapered profile results when non-volatile etch residue is deposited onto the sidewalls of a patterned pSTTM material layer stack 330. In an embodiment, the non-volatile etch residue extending from the fixed magnet 314 to the free magnet 318 may be conductive and can lead to electrical shorting between the fixed magnet 314 and the free magnet 318. In an embodiment, a second clean-up etch process is carried out to remove the etch residue from sidewalls of the tunnel barrier 316 to electrically isolate the free magnet 318 from the fixed magnet 314.

In an embodiment, the plasma etch process also etches the bottom electrode layer 305

(not shown) and the plasma etch is halted once an uppermost surface of the seed layer 303 is exposed.

Figure 3E illustrates a cross-sectional view of the structure in Figure 3D following the formation of a dielectric spacer layer 325 around the patterned portion 332 of the pSTTM material layer stack 330, and on an uppermost surface of the bottom electrode layer 305. In an embodiment, a dielectric spacer layer 325 is blanket deposited immediately following the plasma etch process utilized to partially pattern the pSTTM material layer stack 330. In an embodiment, the dielectric spacer layer 325 is deposited immediately following the plasma etch process but without breaking vacuum to prevent unwanted oxidation of the magnetic layers.

In an embodiment, the dielectric spacer layer 325 includes a material such as silicon nitride, silicon dioxide or carbon doped silicon nitride. In an embodiment, the dielectric spacer layer 325 is chosen to exclude an oxygen containing material to prevent oxidation of magnetic layers after the clean-up etch process. In an embodiment, the dielectric spacer layer 325 is deposited at a process temperature of less than 300 degrees Celsius. In an embodiment, the dielectric spacer layer 325 is deposited to a thickness between 10nm-20nm.

In an embodiment, when the plasma etch process also etches the bottom electrode layer

305 (as described in connection with Figure 3D), a dielectric spacer layer 325 is also deposited on sidewalls of an etched bottom electrode (not shown).

Figure 3F illustrates a cross-sectional view of the structure in Figure 3E following the formation of a dielectric spacer 326 and following the patterning of the bottom electrode layer 305 and patterning of the seed layer 303 to form a pSTTM device 370. In an embodiment, the dielectric spacer layer 325 is etched by a plasma etch process to form a dielectric spacer 326 on sidewalls of the patterned portion 332 of the pSTTM material layer stack 330. After forming the dielectric spacer 326, in an embodiment, a different plasma etch process is utilized to etch the bottom electrode layer 305 and seed layer 303 to form bottom electrode 306 and patterned seed layer 304. In an embodiment, a protrusion 327 is formed on the bottom electrode layer 305 due to masking by the dielectric spacer 326. In an embodiment, sidewalls of the bottom electrode 306 have a vertical profile. In other embodiments the sidewalls are tapered. The process of patterning the bottom electrode layer 305 by using the dielectric spacer 326 results in a bottom electrode 326 having a width that is greater than a width of the patterned portion 332 of the pSTTM material layer stack 330.

In an embodiment, a second anneal process can be performed after formation of the pSTTM device 370. In an embodiment, the second anneal process is carried out at a process temperature of at least 300 degrees Celsius but less than 400 degrees Celsius. In an embodiment, the post process anneal can help to recrystallize sidewalls of the tunnel barrier 316 that may have become potentially damaged during the etching process utilized to form the pSTTM device 370.

Figure 5 A illustrates a cross-sectional view of the structure in Figure 3D following the patterning of the bottom electrode layer 305 and the seed layer 303 prior to forming a dielectric spacer layer to form a pSTTM device 580. In an embodiment, the plasma etch described in association with Figure 3D is continued further to form a bottom electrode 506 and a patterned seed layer 504. In one such embodiment, the bottom electrode 506 does not have a protrusion. In one such embodiment, the bottom electrode 506 does not have a protrusion although the entire patterned pSTTM material layer stack 330 can have a tapered profile. In one embodiment, the bottom electrode 506 does not have a protrusion and all the layers in the pSTTM material layer stack 330 have an approximately similar width.

Figure 5B illustrates a cross-sectional view of the structure in Figure 5 A following the formation of a dielectric spacer 526 on sidewalls of the pSTTM device 580. In an embodiment, a dielectric spacer layer is deposited on the structure of Figure 5 A and subsequently plasma etched to form a dielectric spacer layer. In an embodiment, dielectric spacer layer includes a material that is the same or substantially the same as the dielectric spacer layer 325.

Figure 6 illustrates a pSTTM device 370, formed on a conductive interconnect 602. In an embodiment, the pSTTM device 370 includes the patterned barrier layer 308, the bottom electrode 310 including a non-stoichiometrically nitrogen doped TaN layer, patterned spacer layer 312, the fixed magnet 314, the tunnel barrier 316 such as an MgO, the free magnet 318, the oxide layer 320, the magnetic follower 322 and top electrode 324. In an embodiment, the conductive interconnect 602 is disposed on a contact structure 604 above a drain region 606 of an access transistor 608 disposed above a substrate 610. In an embodiment, a portion of the conductive interconnect 602 is disposed on a first dielectric layer 603. A second dielectric layer 607 laterally surrounds conductive interconnect 602. In an embodiment, a pSTTM device 370 is disposed on a conductive interconnect 602 as is illustrated in Figure 6. In an embodiment, the pSTTM device 370 is surrounded by a dielectric spacer 326. In an embodiment, the pSTTM device 370 has a width that is greater than a width of the conductive interconnect 602. In one such embodiment, a portion of the seed layer 304 of pSTTM device 370 is also disposed on a second dielectric layer 607. In an embodiment, the pSTTM device 370 has a width smaller than the width of the conductive interconnect 602. In an embodiment, the pSTTM device 370 has a width equal to the width of the conductive interconnect 602.

In an embodiment, the conductive interconnect 602 is the same or substantially the same as conductive interconnect 302.

In an embodiment, the underlying substrate 610 represents a surface used to manufacture integrated circuits. Suitable substrate 610 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 610 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 608 associated with substrate 610 are metal- oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 610. In various implementations of the invention, the access transistor 608 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. In an embodiment, the access transistor 608 of substrate 610 includes a gate stack formed of at least two layers, a gate dielectric layer 614 and a gate electrode layer 612. The gate dielectric layer 614 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 614 to improve its quality when a high-k material is used.

The gate electrode layer 612 of the access transistor 608 of substrate 610 is formed on the gate dielectric layer 614 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 612 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 612 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an MOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 612 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U- shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 612 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U- shaped layers.

In some implementations of the invention, a pair of sidewall spacers 616 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 616 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 618 and drain region 606 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 618 and drain region 606 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 618 and drain region 606. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 618 and drain region 606. In some implementations, the source region 618 and drain region 606 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 618 and drain region 606 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 618 and drain region 606.

In an embodiment, a gate contact 620 and a source contact 622 are formed in a third dielectric layer 624, in the second dielectric layer 607 and in the first dielectric layer 603, above the gate electrode layer 612 and source region 618, respectively. In an embodiment, an MTJ contact 626 is disposed on the pSTTM device 370.

Figure 7 illustrates a computing device 700 in accordance with one embodiment of the invention. The computing device 700 houses a motherboard 702. The motherboard 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the motherboard 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the motherboard 702. In further implementations, the communication chip 706 is part of the processsor 704.

Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.17 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more memory devices, such as a pSTTM device 370, built with a pSTTM material layer stack 330 in accordance with

embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes pSTTM devices integrated with access transistors, built in accordance with embodiments of the present invention.

In an embodiment, the pSTTM devices includes a pSTTM device 370.

In further implementations, another component housed within the computing device 700 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data such as for e.g. in automobile applications.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of a pSTTM material layer stack 330. Such pSTTM material layer stack 330 may be used in an embedded non-volatile memory application.

Figure 8 illustrates an integrated circuit (IC) structure 800 that includes one or more embodiments of the invention. The integrated circuit (IC) structure 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an integrated circuit (IC) structure 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the integrated circuit (IC) structure 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the integrated circuit (IC) structure 800. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 800.

The integrated circuit (IC) structure 800 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 810. The integrated circuit (IC) structure 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, pSTTM devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 800. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 800.

Thus, embodiments of the present disclosure include perpendicular STTM (pSTTM) devices with an enhanced bottom electrode and methods to form same.

Example 1 : A memory device includes, a bottom electrode comprising a non- stoichiometric tantalum nitride layer, a synthetic antiferromagnetic layer above the bottom electrode, a fixed magnet above the synthetic antiferromagnetic layer, a tunnel barrier above the fixed magnet, a free magnet above the tunnel barrier, and a top electrode.

Example 2: The memory device of example 1, wherein the bottom electrode has a chemical composition Tai- _X N _X , where X and Y each represent an atomic percent, and further where X is greater than 10 and less than 90.

Example 3 : The memory device of example 1 or 2, wherein the non-stoichiometric tantalum nitride layer is amorphous.

Example 4: The memory device of example 1 or 2, wherein the non-stoichiometric tantalum nitride layer is polycrystalline.

Example 5: The memory device of example 1, 2 or 4, wherein the non-stoichiometric tantalum nitride layer has a FCC (111) crystal orientation.

Example 6: The memory device of example 1, wherein the synthetic antiferromagnetic layer is lattice matched to the non-stoichiometric tantalum nitride layer.

Example 7: The memory device of example 1 or 2, wherein the bottom electrode has a thickness between 2nm-20nm.

Example 8: The memory device of example 1 or 6, wherein the synthetic

antiferromagnetic layer includes a non-magnetic layer between a first ferromagnetic layer and a second ferromagnetic layer, further wherein the first ferromagnetic layer is anti- ferromagnetically coupled to the second ferromagnetic layer.

Example 9: A memory device includes a conductive interconnect, a seed layer disposed above the conductive interconnect, a bottom electrode including a nitrogen doped tantalum layer disposed on the conductive interconnect and a buffer layer diposed above the non-stoichiometric bottom electrode. The memory device further includes perpendicular magnetic tunnel junction (pMTJ) including a synthetic antiferromagnetic layer disposed above the buffer layer, a fixed magnet disposed above the buffer layer, a tunnel barrier disposed above the fixed magnet, a free magnet disposed above the tunnel barrier, an oxide layer disposed above the free magnet, and a top electrode disposed above the oxide cap. Example 10: The memory device of example 9, wherein the bottom electrode has a chemical composition Taioo-xN _x , where X and Y each represent an atomic percent, and further where X is greater than 10 and less than 50.

Example 11 : The memory device of example 9 or 10, wherein the non-stoichiometric tantalum nitride layer is amorphous

Example 12: The memory device of example 9, wherein the non-stoichiometric tantalum nitride layer is polycrystalline.

Example 13 : The memory device of example 9 or 12, wherein the non-stoichiometric tantalum nitride layer has a FCC (111) crystal orientation.

Example 14: The memory device of example 9 or 10, wherein the bottom electrode has a thickness between lnm to 50nm.

Example 15: The memory device of example 9, wherein the buffer layer includes a first layer and a second layer, wherein the first layer include a metal are selected from the group consisting of Ta, Ru and Pt, and the second layer includes a metal selected from the group consisting of Ta, Ru and Pt, and further wherein the metal of the first layer is different from the metal of the second layer.

Example 16: The memory device of example 9 or 15, wherein the buffer layer is lattice matched to the non-stoichiometric tantalum nitride layer.

Example 17: The memory device of example 9, 15 or 16, wherein the buffer layer has a thickness between lnm to 5nm.

Example 18: The memory device of example 9, wherein the synthetic antiferromagnet includes a non-magnetic layer disposed between a first ferromagnetic layer and a second ferromagnetic layer, further wherein the first ferromagnetic layer is anti-ferromagnetically coupled to the second ferromagnetic layer.

Example 19: A method of fabricating a memory device includes forming a bottom electrode layer above a conductive interconnect structure. The method further includes forming a buffer layer on the bottom electrode layer. The method further includes performing a partial etch back of the buffer layer prior to forming a material layer stack for a memory device. The method further includes forming the material layer stack for a memory device on the partially etched buffer layer, the forming including, forming a synthetic antiferromagnetic layer on the buffer layer. The method further includes forming a fixed magnetic layer above the synthetic antiferromagnetic layer, forming a tunnel barrier layer on the fixed magnetic layer, forming a free magnetic layer on the tunnel barrier layer and forming a top electrode layer above the oxide layer. The method further includes forming a mask above the top electrode layer, and etching the material layer stack to form a patterned material layer stack having sidewalls.

Example 20: The method of example 19, wherein the deposition of the bottom electrode layer is performed by sputtering tantalum onto the conductive interconnect and reacting the sputtered tantalum with nitrogen gas (N ₂ ) to form a bottom electrode layer having a chemical composition Taioo-xN _x , where X and Y each represent an atomic percent, and further where X is greater than 10 and less than 50.

Example 21 : The method of example 20, wherein the nitrogen gas is flowed at a constant rate.

Example 22: The method of example 19 or 20, wherein the process of forming the bottom electrode layer includes depositing the bottom electrode and then planarizing the bottom electrode layer.

Example 23 : The method of example 19 further includes etching the buffer layer to form a patterned buffer layer and stopping the etch on the bottom electrode layer. The method further includes forming a dielectric spacer layer laterally adjacent to the sidewalls of the patterned material layer stack and laterally adjacent to the patterned buffer layer. The method further includes etching the dielectric spacer layer to expose the bottom electrode layer. The method further includes etching the bottom electrode layer to form a non-stoichiometric bottom electrode, and etching the seed layer to form a patterned seed layer. Example 24: The method of example 19 further includes etching the bottom electrode layer to form a non-stoichiometric bottom electrode and etching the seed layer to form a patterned seed layer. . The method further includes forming a dielectric spacer layer laterally adjacent to the sidewalls of the patterned material layer stack, laterally adjacent to the buffer layer, laterally adjacent to the bottom electrode and laterally adjacent to the patterned seed layer. The method further includes and etching the dielectric spacer to expose the conductive interconnect structure.