Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and low damping and methods to form the same.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with pSTTM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a pSTTM stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, increasing thermal stability and reducing magnetic damping of pSTTM devices are some important areas of development. As such, improvements are still needed in the areas of pSTTM stack development that will contribute to improving stability and reducing magnetic damping.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a cross-sectional view of a magnet, in an accordance with an embodiment of the present disclosure.

Figure 2A illustrates a cross-sectional view of a perpendicular STTM (pSTTM) device, in an accordance with an embodiment of the present disclosure.

Figure 2B illustrates a cross-sectional view depicting the direction of magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present disclosure.

Figure 2C illustrates a cross-sectional view depicting the direction of magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present disclosure.

Figures 2D illustrates a cross-sectional view of individual layers of a synthetic antiferromagnetic structure, in accordance with an embodiment of the present disclosure. Figure 3A illustrates a cross-sectional view of a pSTTM device, in an accordance with an embodiment of the present disclosure.

Figure 3B illustrates a cross-sectional view of a pSTTM device, where a follower magnetic layer includes a magnetic alloy, in an accordance with an embodiment of the present disclosure.

Figures 4 A illustrate a cross-sectional view of a pSTTM device, where an additional magnetic layer is inserted into the storage layer to improve stability.

Figures 4B illustrate a cross-sectional view of a pSTTM device, where an additional magnetic layer is inserted above the fixed layer.

Figures 4C illustrate a cross-sectional view of a pSTTM device, where an additional magnetic layer is inserted into the storage layer and a second additional magnetic layer is added above the fixed layer, in accordance with an embodiment of the present disclosure.

Figure 5 A-5E illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM material layer stack.

Figure 5A illustrates a cross-sectional view of the formation of a conductive interconnect and a bottom electrode layer on the conductive interconnect.

Figure 5B illustrates a cross-sectional view of the structure in Figure 5 A following the formation of various layers in a material layer stack for a pSTTM device on the conductive interconnect.

Figure 5C illustrates a cross-sectional view of the structure in Figure 5B following the formation of various layers to complete the formation of a pSTTM material layer stack.

Figure 5D illustrates a cross-sectional view of the structure in Figure 5C following patterning of the pSTTM material layer stack to form a pSTTM device.

Figure 5E illustrates a cross-sectional view of the structure in Figure 5D following the formation of a dielectric spacer on sidewalls of the pSTTM device.

Figure 6 illustrates a plot of stability versus thickness of the storage layer for a variety of storage layers in pSTTM devices, in accordance with embodiments of the present disclosure.

Figure 7 illustrates a plot of damping versus thickness of the storage layer for a variety of storage layers in pSTTM devices, in accordance with embodiments of the present disclosure.

Figure 8 illustrates a cross-sectional view of a pSTTM device formed on a conductive interconnect coupled to a transistor.

Figure 9 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 10 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure. DESCRIPTION OF THE EMBODIMENTS

Perpendicular-spin transfer torque memory (pSTTM) devices with enhanced stability and low damping and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

A pSTTM device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. The resistance state of a pSTTM device is defined by the relative orientation of magnetization between a free magnetic layer and a fixed magnetic layer that are separated by a tunnel barrier. When the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that are in the same direction the pSTTM device is said to be in a low resistance state. Conversely, when the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that in opposite directions, the pSTTM device is said to be in a high resistance state. In an embodiment, resistance switching is brought about by passing a critical amount of spin polarized current through the pSTTM device so as to influence orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need power to retain relative orientation of magnetization, the resistance state of the pSTTM device is retained even when there is no power applied to the pSTTM device. For this reason, pSTTM belongs to a class of memory known as non-volatile memory. Integrating a non-volatile memory device such as an STTM device onto an access transistor enables the formation of embedded memory for system on chip applications.

However, approaches to integrate an STTM device onto an access transistor presents challenges that have become far more formidable with scaling. Examples of such challenges range from improving stability against perturbing forces and reducing damping forces in STTM devices. As scaling continues, the need for smaller memory devices to fit into a scaled cell size has driven the industry in the direction of "perpendicular" STTM or pSTTM. The word "perpendicular" in pSTTM devices refers to fact that magnetic dipoles in the free and fixed magnets are directed perpendicular to a plane of a substrate above which the pSTTM device is formed. Fortunately, while pSTTM devices have higher stability for small memory device sizes, maintaining stability along with reducing damping continues to be a challenge. Stability of a pSTTM device refers to the ease with which the pSTTM device can be perturbed from a high or low resistance state. Alternatively, the stability of pSTTM device is a measure of the memory retention of the device. A greater stability represents better memory retention. Stability of a pSTTM free layer is given by equation (1), provided below.

Stability = Area * K _eff * t _mag = Area * [/¾ - ((N _z - N _x )M^t _mag °/ ₂ )]

Equation (1)

The parameter K _e jf refers to the effective magnetic anisotropy of the free magnetic layer (for example in a perpendicular direction), the t _mag terms refers to the thickness of the free magnetic layer, the parameter, K, refers to the interfacial magnetic anisotropy of the free magnetic layer, N _z is a term that denotes demagnetization in a direction that is parallel to an axis of the pSTTM device, N _x is a term that denotes demagnetization in a direction that is orthogonal to the axis of the pSTTM device, M _s is the saturation magnetization of the magnetic free layer, and μ ₀ is the magnetic permeability of free space. The demagnetization, also known as a stray field, is the magnetic field (H-field) generated by the magnetization in a magnet. Saturation magnetization is a state of magnetization in a magnet where an increase in an applied external magnetic field H cannot increase the magnetization of the magnet any further. A reduction in the saturation magnetization, M _s , of the magnetic free layer can increase the stability of the free magnetic layer. As can be appreciated from equation (1), reducing the value oiM _s reduces the negative term that is subtracted from K thus increasing K _e /f and as a result increasing the stability. Hence, a material with lower M _s is desirable for increasing stability if K, and (N _z -N _x ) terms are unchanged.

However, while reducing M _s is advantageous to improve stability, a simultaneous reduction in magnetic damping can help to render a pSTTM device that can also switch with a lower switching current. Damping relates to a magnetic friction experienced by the magnetic dipoles in a magnet as they switch direction. However, for free magnetic layers consisting of alloys two or more elements of Co, Fe and B, increase in thickness of the free magnetic layer also leads to an increase in magnetic damping. Thus, an alloy that can exhibit low damping and higher stability is advantageous for scaled STTM devices such as pSTTM devices.

In accordance with embodiments of the present disclosure, a material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier such as but not limited to MgO disposed above the fixed magnetic layer. A free magnetic layer is disposed on the tunnel barrier where the free magnetic layer includes an alloy, such as FeB, mixed with a nonmagnetic element such as Mo, for instance a layer of (ΡεγΒιοο-γ)ιοο-χΜο _χ . Inclusion of less than 10% of a nonmagnetic element, such as Mo, in a (ΤεγΒιοο-γ)ιοο-χΜο _χ free magnetic layer can noticeably reduce the saturation magnetization, M _s , of the (ΤεγΒιοο-γ)ιοο-χΜο _χ free magnetic layer. The nonmagnetic element incorporated into the free magnet can be a metal or a non-metal. The free magnetic layer including a nonmagnetic element can have a thickness that is greater than a conventional free magnetic layer such as a free magnetic layer including an alloy of two or more elements from the group consisting of Co, Fe and B. Increasing material thickness can be advantageous for perpendicular magnetic systems because perpendicular magnets tend to be thin, and are often limited to a small range for e.g 1.0nm-2.5nm or 1.5nm-3nm depending on the application, and demand greater process uniformity during the deposition process.

While adding a non-magnetic element to the free magnetic layer can reduce M _s , however, another property of the pSTTM device, the tunneling magnetoresi stance ratio (TMR) can be lowered in some instances. The TMR is a parameter that is related to the numerical difference between values of electrical resistance measured when a pSTTM device is in a high resistance state and when a pSTTM device is in a low resistance state. In an embodiment, a thin magnetic layer including an alloy such as CoFeB, or FeB or a magnetic material like iron can be inserted between a free magnetic layer having a nonmagnetic element and the tunnel barrier to help improve TMR. The inserted thin magnetic layer and the free magnetic layer having a

nonmagnetic element act as a coupled free magnetic structure. In one such embodiment, the inserted thin magnetic layer is sufficiently thick to help increase TMR of the pSTTM device, but is appreciably thin so to not raise the saturation magnetization, M _s , of the coupled free magnetic structure.

Figure 1 illustrates a cross-sectional illustration of a magnet 100 having a composition that is capable of lowering saturation magnetization and reducing magnetic damping in accordance with an embodiment of the present disclosure. In an embodiment, the magnet includes an alloy consisting of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo. In one embodiment, the magnet 100 includes an alloy with a chemical composition of (ΡεγΒιοο-γ)ιοο-χΕχ, where X and Y each represent an atomic percent and E represents a single element. In one exemplary embodiment, the magnet 100 includes an alloy of iron and boron, with a small amount of molybdenum having a chemical composition of (ΡεγΒιοο-γ)ιοο-χΜο _χ , where X and Y each represent an atomic percent. In an embodiment, X is less than 10 and Y is greater than or equal to 80. In another

embodiment, X is between 5.0 and 9.3 (inclusive) and Y is between 75 and 90. In an

embodiment, the composition of the magnet 100 is such that the one or more elements selected from the group consisting of Si, Ge, Al, HE, W, Ru, Ir, Ta, Cr and Mo are uniformly distributed throughout the volume of the magnet 100. In an embodiment, the composition of the magnet 100 is such that the one or more elements selected from the group consisting of Si, Ge, Al, HE, W, Ru, Ir, Ta, Cr and Mo are distributed with a gradient throughout the volume of the magnet 100. When the magnet 100 is utilized in a pSTTM material layer stack, the thickness of the magnet 100 is determined by the function of the magnet 100 in the pSTTM material layer stack, as will be discussed below. In an embodiment, the magnet 100 is utilized as a free magnet. In another embodiment, the magnet 100 is utilized as a fixed magnet. In another embodiment, the magnet 100 is utilized as a follower magnetic layer that is coupled with a free magnet. In yet another embodiment, the magnet 100 can be utilized as a free magnet as well as a free magnet in the same pSTTM material layer stack.

Figure 2A illustrates a cross-sectional view of a perpendicular STTM (pSTTM) device 200A disposed on a conductive interconnect structure 201, in an accordance with an embodiment of the present disclosure. The pSTTM device 200A includes a bottom electrode 202 disposed on the conductive interconnect structure 201, a fixed magnet 204 disposed above the bottom electrode 202, a tunnel barrier 206, such as an MgO, disposed above the fixed magnet 204 and a free magnet 208 disposed on the tunnel barrier 206.

In an embodiment, the free magnet 208 is a magnet that is similar or substantially similar to magnet 100 described above in association with Figure 1. In an embodiment, the free magnet 208 has a chemical composition (ΡεγΒιοο-γ)ιοο-χΜο _χ , where X and Y each represent an atomic percent. In an embodiment, X is less than 10 and Y is greater than or equal to 80. In another embodiment, X is between 5.0 and 9.3 (inclusive) and Y is between 75 and 90. In a specific embodiment, the free magnet 208 has a composition (Fe8oB2o)9o.7Mo9.3. In an embodiment, the magnet 208 has a thickness that is between l .Onm and 3.0nm. In an embodiment, the free magnet 208 having a chemical composition (ΡεγΒιοο-γ)ιοο-χΜο _χ has a thickness that is between l .Onm and 3.0nm. In an embodiment, a free magnet 208 having a chemical composition

(ΡεγΒιοο-γ)ιοο-χΜθχ and having a thickness between l .Onm and 3nm results in the free magnet 208 having a perpendicular magnetic anisotropy. In an embodiment, the fixed magnet 204 includes materials and has a thickness sufficient for maintaining a fixed magnetization. Fixed magnetization indicates that a magnetization in the fixed magnet 204 does not change direction during spin transfer torque-current flow. In an embodiment, the fixed magnet 204 includes a magnetic metal such as cobalt, nickel and iron. In an embodiment, the fixed magnet 204 includes an alloy such as CoFe or CoFeB. In an embodiment, the fixed magnet 204 includes a layer of Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 204 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In another embodiment the fixed magnet 204 has a thickness that is between 1.5nm- 2.5nm. In an embodiment, a fixed magnet 204 having a thickness between 1.5nm and 2.5nm has perpendicular magnetic anisotropy.

Referring again to Figure 2A, in an embodiment, the tunnel barrier 206 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 206, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 206. Thus, the tunnel barrier 206 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 206 includes an oxide such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 206 is MgO and has a thickness of approximately 1 to 2 nm.

Referring again to Figure 2A, the pSTTM device 200A further includes an oxide layer 210 disposed above the free magnet 208. In an embodiment, when the free magnet 208 includes iron, the oxide layer 210 provides a source of oxygen that enables oxygen-iron hybridization at an interface 205 located between an uppermost surface of the free magnet 208 and a lowermost surface of the oxide layer 210. Oxygen-iron hybridization at the interface 205 can enable a high interfacial perpendicular magnetic anisotropy in the free magnet 208. In an embodiment, the oxide layer 210 is MgO. In an embodiment, the oxide layer 210 has a thickness that is between 0.3nm-0.7nm. In an embodiment, the oxide layer 210 has a thickness that is less than the thickness of the tunnel barrier 206. An oxide layer 210 having a thickness of less than 0.8nm is sufficiently thin to allow electron current to flow through.

Referring again to Figure 2A, a follower magnetic layer 212 is disposed above the oxide layer 210. The follower magnetic layer 212 is magnetically coupled to the free magnet 208 to form a coupled system of switching magnetic layers. In an embodiment, the follower magnetic layer 212 has a weaker perpendicular magnetic anisotropy than the perpendicular magnetic anisotropy of the free magnet 208. A follower magnetic layer 212 having a weaker perpendicular magnetic anisotropy undergoes current induced magnetization switching more easily than a free magnet 208 having a stronger perpendicular magnetic anisotropy. The presence of the follower magnetic layer with a weaker perpendicular magnetic anisotropy does not increase the magnitude of the switching current requirement of a pSTTM device.

An interface 207 formed between the follower magnetic layer 212 and the oxide layer

210 increases the interfacial perpendicular magnetic anisotropy of the follower magnetic layer 212. The interfacial perpendicular magnetic anisotropy of the follower magnetic layer 212 at the interface 207 is less than the interfacial perpendicular magnetic anisotropy of the free magnet 208 at the interface 205. In an embodiment, the follower magnetic layer 212 has a thin uppermost portion that can be non-magnetic. In such an embodiment, the follower magnetic layer 212 has a material composition and thickness sufficient for perpendicular magnetic anisotropy and to remain magnetically coupled to the free magnet 208.

In an embodiment, the follower magnetic layer 212 includes an alloy such as but not limited to FeB, CoFe or CoFeB. In an embodiment the follower magnetic layer 212 is CoFeB. In an embodiment, the follower magnetic layer 212 has a thickness between 0.6nm-2.0 nm. In an embodiment, a CoFeB follower magnetic layer 212 having a thickness of at least 0.6nm is sufficiently thick to possess perpendicular magnetic anisotropy. Moreover, the interfacial perpendicular magnetic anisotropy arising from iron-oxygen hybridization at the interface 207 aids in maintaining the overall perpendicularity of the follower magnetic layer 212.

In an embodiment, the pSTTM device 200A further includes a top electrode 214 disposed above the follower magnetic layer 212, as illustrated in Figure 2 A. In an embodiment, the top electrode 214 includes a material such as Ta or TiN. In an embodiment, the top electrode 214 has a thickness between 30-70nm.

Referring again to Figure 2A, in an embodiment, the bottom electrode 202 is composed of a material or stack of materials suitable for electrically contacting the fixed magnet 204 side of the pSTTM device 200A. In an embodiment, the bottom electrode 202 includes an amorphous conductive layer. In an embodiment, the bottom electrode 202 is a topographically smooth electrode. In a specific embodiment, the bottom electrode 202 is composed of Ru layers interleaved with Ta layers. In another embodiment, the bottom electrode 202 is TiN. In an embodiment, the bottom electrode 202 has a thickness between 20nm-50nm. In an embodiment, the bottom electrode 202 and the top electrode 214 include a same metal such as Ta or TiN.

Referring again to Figure 2 A, the conductive interconnect structure 201 includes a conductive interconnect 230 disposed in an interlayer dielectric 234 formed above a substrate 220. In an embodiment, the conductive interconnect 230 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the interlayer dielectric 234 includes a dielectric layer such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. As illustrated in Figure 2A, the pSTTM device 200A has a width, WPSTTM, and the conductive interconnect 230 has a width Wei. In an embodiment, the pSTTM device 200A has a width, WPSTTM, that is less that the width Wei, of the conductive interconnect 230. In an embodiment, the pSTTM device 200A has a width, WPSTTM, that is greater that the width Wei, of the conductive interconnect 230. In another embodiment, the pSTTM device 200A has a width, WPSTTM, that is similar to the width Wei, of the conductive interconnect 230. In an embodiment, the substrate 220 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 220. Access transistors may be integrated with pSTTM devices such as pSTTM device 200A.

Figure 2B illustrates a cross-sectional view depicting the direction of magnetization in a free magnet 208 relative to the direction of magnetization in a fixed magnet 204, in accordance with an embodiment of the present disclosure. In an embodiment, when the direction of magnetization 245 (denoted by the direction of the arrow) in the free magnet 208 is opposite (anti-parallel) to the direction of magnetization 240 in the fixed magnet 204, a pSTTM device having a free magnet 208 and a fixed magnet 204 is said to be in a high resistance state.

Conversely, a pSTTM device is in a low resistance state when the magnetization 245 in the free magnet 208 is parallel to the direction of magnetization 240 in the fixed magnet 204 as illustrated in Figure 2C. A change in resistance (high to low or low to high) in the pSTTM device 200A results when a spin polarized electron current passing into the free magnet 208 through the tunnel barrier 206 brings about a change in the direction of the magnetization 245 in the free magnet 208.

In an embodiment, the free magnet 208 and the fixed magnet 204 can have similar thicknesses and an injected electron spin current which changes the direction of the

magnetization 245 in the free magnet 208 can also affect the direction of magnetization 240 of the fixed magnet 204. In an embodiment, to make the fixed magnet 204 more resistant to accidental flipping the fixed magnet 204 has a greater perpendicular magnetic anisotropy than the free magnet 208. In another embodiment, a synthetic antiferromagnetic (SAF) structure is disposed between the bottom electrode 202 and the fixed magnet 204 in order to prevent accidental flipping of the direction of magnetization 240 in the fixed magnet 204. The SAF structure is ferromagnetically coupled with the fixed magnet 204.

Figure 2D illustrates cross-sectional view of the synthetic antiferromagnetic (SAF) layer 250 in an accordance of an embodiment of the present disclosure. In an embodiment, the SAF structure 250 includes a non-magnetic layer 250B between a first ferromagnetic layer 250A and a second ferromagnetic layer 250C as depicted in Figure 2D. The first ferromagnetic layer 250A and the second ferromagnetic layer 250C are anti-ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 250A includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, the non-magnetic layer 250B includes a ruthenium or an iridium layer. In an embodiment, the second ferromagnetic layer 250C includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, a ruthenium based non-magnetic layer 250B has a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnetic layer 250A and the second ferromagnetic layer 250C is anti-ferromagnetic in nature.

In an embodiment, an additional layer of non-magnetic spacer material may be disposed between the SAF structure 250 and the fixed magnet 204. A layer of non-magnetic spacer material enables antiferromagnetic coupling between the second ferromagnetic layer 250C and the fixed magnet 204. In an embodiment, a layer of non-magnetic spacer material may include metals such as Ta, Ru or Ir. In an embodiment, the thickness of the layer of non-magnetic spacer material is greater than 0. lnm but less than 0.23nm.

Figure 3A illustrates a cross-sectional view of a pSTTM device 300A in an accordance with an embodiment of the present disclosure. In an embodiment, pSTTM device 300A includes a fixed magnet 304 disposed above the bottom electrode 202. In an embodiment, fixed magnet 304 is similar or substantially similar to the magnet 100 described above in association with Figure 1. In an embodiment, the fixed magnet 304 includes an alloy consisting of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo. In an exemplary embodiment, the fixed magnet 304 includes an alloy with a chemical composition of (ΡεγΒιοο-γ)ιοο-χΜο _χ , where X and Y each represent an atomic percent. In an embodiment, X is less than 10 and Y is greater than or equal to 80. In an embodiment the fixed magnet 304 has a thickness that is between l .Onm- 3.0nm. In an embodiment, a fixed magnet 304 having a chemical composition (ΡεγΒιοο-γ)ιοο-χΜο _χ has a thickness that is between l .Onm and 3.0nm. In an embodiment, a fixed magnet 304 having a chemical composition (ΡεγΒιοο-γ)ιοο-χΜθχ and having a thickness between l .Onm and 3nm results in the fixed magnet 304 having a perpendicular magnetic anisotropy. It is to be appreciated that a fixed magnet 304 having a chemical composition (ΡεγΒιοο-γ)ιοο-χΜο _χ enables the thickness of the fixed magnet 304 to be increased and yet have a perpendicular magnetic anisotropy. In contrast, in an embodiment, a fixed magnet 304 including a CoFeB, CoFe, or a FeB having a thickness greater than 2.5nm will have an in-plane magnetic anisotropy.

It is to be appreciated that incorporating the one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo into the alloy consisting of iron and boron can reduce the saturation magnetization, M _s , of the fixed magnet 304 and make it less resistant to switching. However, in order to prevent the magnetization of the fixed magnet 304 from accidentally flipping during cycling of the pSTTM device 300A, a SAF structure such as SAF structure 250 can be inserted between the fixed magnet 304 and the bottom electrode 202. In an embodiment, the SAF structure 250 can anti-ferromagnetically couple with the fixed magnet 304 and help to pin the magnetization of the fixed magnet 304.

Referring again to Figure 3A, in an embodiment, a free magnet 308 is disposed above the tunnel barrier 206. In an embodiment, the free magnet 308 is composed of Co, Ni, Fe. In an embodiment, the free magnet 308 of the pSTTM device 300A includes an alloy such as CoFe or CoFeB. In an embodiment, the free magnet 308 comprises a Coi-x-yFe _x By, where X and Y each represent atomic percent, further where X is between 0.5-0.8 and Y is between 0.1-0.4, and further where the sum of X and Y is less than 1. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the free magnet 308 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In other embodiments, free magnet 308 includes magnetic alloys of Ni. In an embodiment the free magnet 308 has a thickness that is between lnm- 2.5nm. In an embodiment, free magnet 308 having a thickness between l .Onm and 2.5nm results in the free magnet 308 having a perpendicular magnetic anisotropy.

Figure 3B illustrates a cross-sectional view of a pSTTM device 300B, where a follower magnetic layer 312 includes a magnetic alloy, in an accordance with an embodiment of the present disclosure. In an embodiment follower magnetic layer 312 is similar or substantially similar to the magnet 100 described above in association with Figure 1. In an exemplary embodiment, follower magnetic layer 312 includes an alloy with a chemical composition of (ΡεγΒιοο-γ)ιοο-χΜθχ, where X and Y each represent an atomic percent. In an embodiment, X is less than 10 and Y is greater than or equal to 80.

In an embodiment, follower magnetic layer 312 has magnetic properties that are similar or substantially similar to follower magnetic layer 212. In an embodiment, the follower magnetic layer 312 has a thin uppermost portion that can be non-magnetic. In an embodiment, a follower magnetic layer 312 including an alloy with a chemical composition of (ΡεγΒιοο-γ)ιοο-χ Μθχ has a thickness between 0.6nm-2.0 nm. In an embodiment, the pSTTM device 300B further includes a free magnet 308 described in association with Figure 3 A and a fixed layer 204 described in association with Figure 2A.

Figures 4 A illustrate a cross-sectional view of a pSTTM device 400 A, where an additional magnetic layer 402 is inserted below a free magnet 408 to create a storage layer 410. In an embodiment, the free magnet 408 is similar or substantially similar to free magnet 208. The storage layer 410 acts as a coupled free magnet where the magnetization in the two individual layers, the free magnet 408 and the magnetic layer 402, switch in response to a spin polarized current. When the magnetic layer 402 is directly adjacent to and lattice matched with the tunnel barrier 206, the TMR ratio of the pSTTM device 400A can be higher than in the pSTTM device 200A where the magnetic layer 402 is absent. In an embodiment, the magnetic layer 402 includes a material that is substantially similar to free magnet 308. In an embodiment, the magnetic layer 402 is a CoFeB having a (001) crystal structure that is lattice matched with a (001) crystal structure of the tunnel barrier 206. In an embodiment, the magnetic layer 402 has a thickness that is between O. lnm-l .Onm to (a) preserve a lower saturation magnetization M _s , and (b) maintain perpendicular magnetic anisotropy of the storage layer 410. In an embodiment, the combined total thickness of the storage layer 410 is between 1.0nm-2.8nm. In an embodiment, the free magnet 408 has a thickness between 0.8nm-2.6nm.

Figures 4B illustrate a cross-sectional view of a pSTTM device 400B, where an additional magnetic layer 404 is inserted above a fixed magnet 440 to create a reference layer 412. The reference layer 412 acts as a coupled fixed magnet where the magnetization in the two individual layers, the fixed magnet 440 and the magnetic layer 404 stay pinned in a given direction. In an embodiment, the fixed magnet 440 is similar or substantially similar to fixed magnet 304. When the magnetic layer 404 is directly adjacent to and lattice matched with the tunnel barrier 206, the TMR ratio of the pSTTM device 400B can be higher than the TMR ratio of the pSTTM device 300A where the magnetic layer 404 is absent. In an embodiment, magnetic layer 404 is similar or substantially similar to magnetic layer 402. In an embodiment, the magnetic layer 404 is a CoFeB having a (001) crystal structure that is lattice matched with a (001) crystal structure of the tunnel barrier 206. In an embodiment, the magnetic layer 404 has a thickness that is between O. lnm-l .Onm to (a) preserve a lower saturation magnetization M _s , and (b) maintain perpendicular magnetic anisotropy of the reference layer 412. In an embodiment, the total thickness of the reference layer 412 is between 1.0nm-2.8nm to maintain perpendicular magnetic anisotropy.

Figures 4C illustrate a cross-sectional view of a pSTTM device 400C having a reference layer 412 and a storage layer 410. In an embodiment, the fixed magnet 440 is similar or substantially similar, in composition and in thickness, to the free magnet 408. In an embodiment, the fixed magnet 440 is different, in composition and in thickness, from the free magnet 408. In an embodiment, the magnetic layer 404 is similar or substantially similar, in composition and in thickness, to the magnetic layer 402. In an embodiment, the magnetic layer 404 is different, in composition and in thickness, from the magnetic layer 402. In an

embodiment, the storage layer 410 has a total thickness that is between lnm-2.8nm and the reference layer 412 has a total thickness that is between 2nm-2.8nm.

Figure 5 A-5E illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM device.

Figure 5 A illustrates a conductive interconnect 502 surrounded by a dielectric layer 501 formed above a substrate 500 and the formation of a bottom electrode layer 503 on the conductive interconnect 502. In an embodiment, the conductive interconnect 502 is formed in a dielectric layer 501 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 502 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the conductive interconnect 502 is fabricated using a subtractive etch process when materials other than copper are utilized. In an embodiment, the dielectric layer 501 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 501 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 502. In an embodiment, the dielectric layer 501 has a total thickness between 70nm-300nm. In an embodiment, conductive interconnect 502 is electrically connected to a circuit element such as a transistor (not shown).

In an embodiment, the bottom electrode layer 503 is blanket deposited onto an uppermost surface of the conductive interconnect 502 and onto an upper most surface of the dielectric layer 501. In an embodiment, the bottom electrode layer 503 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the bottom electrode layer 503 includes a metal such as but not limited to W, Ru, Ti or Ta or an alloy such as but not limited to WN, TiN or TaN. In an embodiment, the bottom electrode layer 503 is deposited to a thickness between 20nm to 50nm.

In an embodiment the bottom electrode layer 503 is first blanket deposited on an uppermost surface of the conductive interconnect 502 and on an upper most surface of the dielectric layer 501, and subsequently polished to achieve a surface roughness of 1 nm or less. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process to form a topographically smooth uppermost surface having a surface roughness of less than lnm. A surface roughness of less than 1 nm is sufficient to enable a subsequent fixed magnetic layer and a tunnel barrier layer to be formed with well-ordered crystal planes. In an embodiment, the planarization process removes 5nm-10nm of bottom electrode material. In one such embodiment, the as deposited thickness of the bottom electrode layer 503 is between 30nm- 60nm.

In an embodiment, the substrate 500 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrates 500 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

Figure 5B illustrates a cross-sectional view of the structure in Figure 5 A following the formation of various layers of a material layer stack for a pSTTM device, in an accordance with an embodiment of the present disclosure. A fixed magnetic layer 505 is deposited on the bottom electrode layer 503. In an embodiment, the fixed magnetic layer 505 is blanket deposited using a physical vapor deposition (PVD) process. In an embodiment, a fixed magnetic layer 505 deposited by a PVD process is amorphous in nature. In an embodiment, the fixed magnetic layer 505 includes an alloy such as but not limited to CoFe, CoFeB and FeB. In an embodiment, fixed magnetic layer 505 includes a Coi-x-yFe _x By, where X and Y each represent atomic percent. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the fixed magnetic layer 505 is blanket deposited to a thickness between lnm-2.5nm. The PVD deposition process ensures that the fixed magnetic layer 505 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate.

A tunnel barrier layer 507 is then blanket deposited on the fixed magnetic layer 505. The low or high resistance of an MTJ device is determined by the material type, quality and thickness of the tunnel barrier layer. In an embodiment, the tunnel barrier layer 507 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 507 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the MgO is deposited to a thickness between 0.8 to lnm. In an embodiment, the reactive sputter deposition process is carried out in a manner that yields a tunnel barrier layer 507 having a mostly crystalline structure. In another embodiment, the tunnel barrier layer layer 507 is not crystalline as deposited but becomes highly crystalline after an anneal process.

A free magnetic layer 509 is then deposited on the uppermost surface of the tunnel barrier

507. In an embodiment, the free magnetic layer 509 is blanket deposited using a PVD process. In an embodiment, the free magnetic layer 509 is formed by a co-sputter depositing iron and boron, along with one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo. In one embodiment, the free magnetic layer 509 includes an alloy with a chemical composition of (ΡεγΒιοο-γ)ιοο-χΜο _χ , where X and Y each represent an atomic percent. In an embodiment, X is less than 10 and Y is greater than or equal to 80. In another embodiment, X is between 5.0 and 9.3 (inclusive) and Y is between 75 and 90. In an

embodiment, the co-sputter deposition process including three or more elements is carried out in a manner that results in a free magnetic layer 509 having a uniform composition. In another embodiment, an ultrathin layer of FeYBioo-γ, where Y is greater than or equal to 80, is first sputter deposited and an ultrathin layer containing the one or more elements selected from the group consisting of Si, Ge, Al, HE, W, Ru, Ir, Ta, Cr and Mo is sputtered on the FeYBioo-γ layer. The process is repeated 2-15 times and a high temperature anneal is performed to form a free magnetic layer 509 consisting of FeYBioo-γ and one or more elements selected from the group consisting of Si, Ge, Al, HE, W, Ru, Ir, Ta, Cr and Mo. In one such embodiment, the resulting free magnetic layer 509 formed by a process of layering is virtually distinguishable from the free magnetic layer 509 formed from a co-sputtering process.

In an embodiment, the free magnetic layer 509 is deposited with a boron content of 10- 20% to ensure an amorphous free magnetic layer 509 is formed. In an embodiment, free magnetic layer 509 is deposited to a thickness between 1.0nm-2.8nm. Exemplary thickness of the free magnetic layer is between 1.5nm - 2.3nm.

Figure 5C illustrates a cross-sectional view of the structure of Figure 5B following the formation of an oxide layer 511 to complete formation of a pSTTM material layer stack 550, in an embodiment of the present disclosure. The oxide layer 511 is formed on the uppermost surface of the free magnetic layer 509 to increase the interfacial perpendicular magnetic anisotropy of the pSTTM material layer stack 550. In an embodiment, the oxide layer 511 is deposited using a process that is substantially similar to the process of depositing the tunnel barrier layer 507. In an embodiment, the oxide deposition process includes depositing a layer of metal onto an uppermost surface of the free magnetic layer 509 and then oxidizing the layer of metal to form the oxide layer 511. In an embodiment, the oxidation process creates an oxide layer 511 is not crystalline compared to a crystalline oxide layer 511 formed by a reactive co- sputter process. However, unlike the tunnel barrier layer 507, the oxide layer 511 acts less as a spin filter but more as a conductive layer. In an embodiment, an oxide layer 511 formed by a metal deposition followed by an oxidation process is sufficiently conductive. In an

embodiment, a metal such as magnesium is first sputter deposited onto the surface of the free magnetic layer 509. In an embodiment, the process includes DC sputter deposition carried out at ambient temperatures of less than 300K. In an embodiment, an oxidation process is carried out to oxidize the as sputtered magnesium metal. In an embodiment, the oxidation process includes subjecting the first metal to an 0 ₂ gas at a pressure between 3mtorr-750mtorr. In an

embodiment, the oxide layer 511 is deposited to a thickness between 0.3nm-0.7nm. In an embodiment, the follower magnetic layer 513 is blanket deposited on the uppermost surface of the oxide layer 511. In an embodiment, the follower magnetic layer 513 is similar or substantially similar to the follower magnetic layer 212. In an embodiment, the deposition process includes a physical vapor deposition (PVD) process. In an embodiment, an RF or a DC sputtering process is utilized to form the various layers in the follower magnetic layer 513. The follower magnetic layer 513 is deposited to a thickness to ensure that the perpendicular magnetic anisotropy of the follower layer is not greater than perpendicular magnetic anisotropy of the free magnetic layer 509.

In an embodiment, the top electrode layer 515 is blanket deposited on the surface of the follower magnetic layer 513. In an embodiment, the top electrode layer 515 includes a material suitable to provide a hardmask for etching the pSTTM material layer stack 550 to form a pSTTM device. In an embodiment, the top electrode layer 515 includes a material such as Ta. In an embodiment, the thickness of the top electrode layer 515 ranges from 30-70nm. The thickness is chosen to accommodate the various sizes of the pSTTM devices that will subsequently be fabricated as well as to provide etch resistivity during etching of the pSTTM material layer stack 550.

In an embodiment, after all the layers in the pSTTM material layer stack 550 are deposited, an anneal is performed under conditions well known in the art to promote solid phase epitaxy of the free magnetic layer 509 following a template of a crystalline layer of the tunnel barrier layer 507. A post-deposition anneal of the pSTTM material layer stack 550 is carried out in a furnace at a temperature between 300-500 degrees Celsius in a forming gas environment. In an embodiment, the anneal is performed immediately post deposition but before patterning of the pSTTM material layer stack 550 to enable a crystalline MgO-tunnel barrier layer 507 to be formed. The post-deposition anneal process also enables boron to diffuse away from an interface 519 between the tunnel barrier layer 507 and the free magnetic layer 509. The process of diffusing boron away from the interface 519 enables lattice matching between the free magnetic layer 509 and the tunnel barrier 507.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 505 and the free magnetic layer 509. An applied magnetic field that is directed parallel to the vertical axis of the pSTTM material layer stack 550, during the annealing process, enables a perpendicular magnetic anisotropy to be set in the fixed magnetic layer 505 and in the free magnetic layer 509. The annealing process initially aligns the magnetization of the fixed magnetic layer 505 and the free magnetic layer 509 to be parallel to each other.

In an embodiment, a material layer stack to form a SAF structure such as a SAF structure 250 is also deposited after forming the bottom electrode layer 503. While the pSTTM material layer stack 550 depicts the material layer stack utilized to form the pSTTM device 200A described in association with Figure 2A, material layer stacks for any of the embodiments described in Figures 3 A-3B and in Figures 4A-4C may be formed using the processes described above. In an embodiment, all layers formed above the bottom electrode layer 503 may be sequentially deposited in a single introduction without breaking vacuum.

In an embodiment, a material layer stack for forming the storage layer such a storage layer 410 described in association with Figure 4 A includes depositing a thin layer of a magnetic material including Co, Fe and Bo on the tunnel barrier and then depositing a free magnetic layer including a (ΡεγΒιοο-γ)ιοο-χΜο _χ on the thin layer of magnetic material including Co, Fe and Bo.

In an embodiment, a material layer stack for forming the reference layer such a reference layer 412 described in association with Figure 4B includes forming a fixed layer including a (ΡεγΒιοο-γ)ιοο-χΜθχ above the bottom electrode layer 202 and then forming a thin layer of a magnetic material including Co, Fe and Bo on the fixed layer including a (ΡεγΒιοο-γ)ιοο-χΜο _χ .

Figure 5D illustrates a cross-sectional view of the structure in Figure 5C following an etch process to pattern the pSTTM material layer stack 550 to form a pSTTM device 570. In an embodiment, a layer photoresist (not shown) is formed above the top electrode layer 515. In an embodiment, the photoresist is patterned using well known lithographic processes known in the art. The lithography process defines the shape and size of the pSTTM device and a location where the pSTTM device is to be formed with respect the conductive interconnect 502. In an embodiment, the top electrode layer 515 is first patterned to form a top electrode 516 and the top electrode 516 is utilized to act as a hardmask for patterning the remaining portion of the pSTTM material layer stack 550 to form a pSTTM device 570 as illustrated in Figure 5E. In an embodiment, a plasma etch process is utilized to etch the pSTTM material layer stack 550 and form the top electrode 516, a magnetic follower 514, an cap oxide 512, a free magnet 510, a tunnel barrier 508, a fixed magnet 506 and a bottom electrode 504. In an embodiment, almost 30-50% of the as deposited top electrode layer 515 may be consumed during the complete etch process. In an embodiment, the plasma etch forms a pSTTM device 570 with a tapered profile (indicated by dashed lines 560). While a highly energetic plasma etch can produce a vertical profile of the pSTTM material layer stack 550, a tapered profile results when nonvolatile etch residue is deposited onto the sidewalls of the patterned pSTTM material layer stack 550. In an embodiment, the nonvolatile etch residue extending from the fixed magnet 506 to the free magnet 510 may be conductive and can lead to electrical shorting between the fixed magnet 506 and the free magnet 510. In an embodiment, a second clean-up etch process is carried out to remove the etch residue from sidewalls of the tunnel barrier 508 to electrically isolate the free magnet 506 from the fixed magnet 510.

Figure 5E illustrates a cross-sectional view of the pSTTM device 570 in Figure 5D following the formation of a dielectric spacer 580 on the sidewalls of the pSTTM material layer stack 550, and on an uppermost surface of the dielectric layer 501. In an embodiment, a dielectric spacer layer is deposited immediately following the plasma etch process utilized to form the pSTTM device 570. In an embodiment, the dielectric spacer layer is deposited immediately following the plasma etch process without breaking vacuum.

In an embodiment, the dielectric spacer layer includes a material such as silicon nitride, silicon dioxide or carbon doped silicon nitride. In an embodiment, the dielectric spacer layer 580 is chosen to exclude oxygen containing material to prevent oxidation of magnetic layers after the clean-up etch process. In an embodiment, the dielectric spacer layer is deposited at a process temperature of less than 300 degrees Celsius. In an embodiment, the dielectric spacer layer is deposited to a thickness between 10nm-20nm. In an embodiment, the dielectric spacer layer is etched by a plasma etch process to form a dielectric spacer 580 on sidewalls of the pSTTM device 570. In an embodiment, the etch process may cause an uppermost portion of the dielectric layer 501 to become partially recessed.

In an embodiment, a second anneal process can be performed after formation of the pSTTM device 570. In an embodiment, the second anneal process is carried out at a process temperature of at least 300 degrees Celsius but less than 400 degrees Celsius. In an embodiment, the post process anneal can help to recrystallize sidewalls of the tunnel barrier 508 that may have become potentially damaged during the etching process utilized to form the pSTTM device 570.

Figure 6 illustrates a plot of stability versus thickness of the storage layer for a variety of free magnetic or storage layers in pSTTM devices, in accordance with embodiments of the present disclosure. The plot 600 illustrates that a pSTTM material layer stack including a (FeYBioo-Y)ioo-xMoxfree magnet 208 has a higher stability than a pSTTM material layer stack not including the element molybdenum in a free magnet over a similar range of thicknesses of the free magnet. The plot 600 illustrates that a pSTTM material layer stack with a free magnet 208 including (ΡεγΒιοο-γ)ιοο-χΜο _χ has a stability that is 3-150 times greater than a stability of a pSTTM material layer stack consisting of a free magnet 208 including FeB over a similar range of thicknesses for a free magnet 208. Specifically, when the free magnet 208 includes a 2nm thick (FeYBioo-Y)ioo-xMoxfree magnet 208, the 2nm thick (FeYBioo-Y)ioo-xMo _x free magnet 208 has a stability of approximately 0.0008 J/m ³ , a value that is approximately 3 times greater than a stability of a 2nm thick free magnet 208 including FeB. In an embodiment, a free magnet 208 including a (ΡεγΒιοο-γ)ιοο-χΜο _χ that is 2.25nm thick has a stability of approximately 0.00075 J/m ³ . A free magnet 208 including a (ΡεγΒιοο-γ)ιοο-χΜο _χ that is 2.25nm thick has a stability that is approximately 150 times greater than a stability of a 2.25nm thick free magnet 208 that includes FeB.

The plot 600 also illustrates that a pSTTM material layer stack with a storage layer, such as the storage layer 410 has lower stability compared to stability of a single free magnet 208 over a similar range of thicknesses of the free magnet 208 and thicknesses of the storage layer 410. In an embodiment, a pSTTM device with a single free magnet 208 including (ΡεγΒιοο-γ)ιοο-χΜο _χ has a stability that is 1.1-1.2 times greater than a stability of a pSTTM device consisting of a storage layer 410 including a CoFeB/(FeYBioo-Y)ioo-xMo _x dual layer over a similar range of thicknesses for a perpendicular free magnet 208.

Figure 7 illustrates a plot of damping versus thickness of the storage layer for a variety of free magnetic or storage layers in pSTTM devices, in accordance with embodiments of the present disclosure. The plot 700 illustrates that a pSTTM material layer stack with a single free magnet, such as the free magnet 208 including an alloy (ΡεγΒιοο-γ)ιοο-χΜο _χ has damping that is 20% lower than damping obtained in a pSTTM material layer stack having a single free magnet 208 not including molybdenum such as CoFeB. The plot 700 illustrates that a pSTTM material layer stack with a storage layer, such as the storage layer 410 including a (ΡεγΒιοο-γ)ιοο-χΜο _χ / CoFeB dual layer has damping that is 40-75% lower than damping obtained in a pSTTM material layer stack not including the storage layer having molybdenum, such as CoFeB.

Figure 8 illustrates a cross-sectional view of a pSTTM device, such as the pSTTM device 570 formed on a conductive interconnect 502 coupled to an access transistor 808. In an embodiment, the pSTTM device 570 includes the bottom electrode 504, the fixed magnet 506, the tunnel barrier 508 such as an MgO, the free magnet 510 including a magnetic alloy such a magnet 100, the cap oxide 512, the magnetic follower 514 and top electrode 516. In an embodiment, the pSTTM device 570 has a width, WPSTTM, that is greater than the width, Wei, of the conductive interconnect 502. In one such embodiment, a portion of the bottom electrode 504 of pSTTM device 800 is also disposed on a dielectric layer 803. In an embodiment, the pSTTM device 800 has a width less than the width of the conductive interconnect 502. In an

embodiment, the pSTTM device 800 has a width equal to the width of the conductive

interconnect 502. In an embodiment, the conductive interconnect 502 is disposed on a contact structure 804 above and electrically coupled with a drain region 806 of an access transistor 808 disposed above a substrate 810.

In an embodiment, the underlying substrate 810 represents a surface used to manufacture integrated circuits. Suitable substrate 810 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 810 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 808 associated with substrate 810 are metal- oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 810. In various implementations of the disclosure, the access transistor 808 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, the access transistor 808 of substrate 810 includes a gate stack formed of at least two layers, a gate dielectric layer 814 and a gate electrode layer 812. The gate dielectric layer 814 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 814 to improve its quality when a high-k material is used.

The gate electrode layer 812 of the access transistor 808 of substrate 810 is formed on the gate dielectric layer 814 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 812 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 812 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 812 with a workfunction that is between about 4.9 eV and about 8.2 eV. For an NMOS transistor, metals that may be used for the gate electrode layer 812 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 812 with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode layer 812 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 812 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode layer 812 may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 812 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the disclosure, a pair of sidewall spacers 816 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 816 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 818 and drain region 806 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 818 and drain region 806 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 818 and drain region 806. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 818 and drain region 806. In some implementations, the source region 818 and drain region 806 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 818 and drain region 806 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 818 and drain region 806.

In an embodiment, a gate contact 820 and a source contact 822 are formed in a second dielectric layer 824 and in the dielectric layer 803 above the gate electrode layer 812 and source region 818, respectively.

Figure 9 illustrates a computing device 900 in accordance with one embodiment of the disclosure. The computing device 900 houses a motherboard 902. The motherboard 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the motherboard 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the motherboard 902. In further implementations, the communication chip 906 is part of the processsor 904.

Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the motherboard 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory devices, such as an pSTTM device 570, fabricated using a pSTTM material layer stack 550 in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes pSTTM memory elements integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device 900 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

Figure 10 illustrates an integrated circuit (IC) structure 1000 that includes one or more embodiments of the invention. The integrated circuit (IC) structure 1000 is an intervening structure used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for instance, an integrated circuit die. The second substrate 1004 may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an integrated circuit (IC) structure 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004. In some embodiments, the first and second substrates 1002/1004 are attached to opposing sides of the integrated circuit (IC) structure 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the integrated circuit (IC) structure 1000. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 1000.

The integrated circuit (IC) structure 1000 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 1000 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure 1000 may include metal interconnects 1008 and via 1010, including but not limited to through-silicon vias (TSVs) 1010. The integrated circuit (IC) structure 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, pSTTM devices such as pSTTM devices 200A, 300A, 300B, 400A, 400B, 400C and 570, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 1000. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 1000.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of a pSTTM device 570. A large array of consisting of pSTTM device 570 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and low damping and methods to form the same.

Specific embodiments are described herein with respect to pSTTM devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices such as in-plane STTM devices or spin orbit torque (SOT) memory devices.

Example 1 : A magnet includes an alloy consisting of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo, wherein the total amount of the one or more elements is less than or equal to 10 atomic percent of the total composition of the alloy.

Example 2: The magnet of example 1, wherein the alloy has a chemical composition (FeYBioo-Y)ioo-xMox, where X is less than 10 and Y is greater than or equal to 80.

Example 3 : The magnet of example 1, wherein the alloy has a chemical composition (Fe _Y Bioo-Y)ioo-xMo _x , where X = 9.3 and Y = 80. Example 4: A memory device includes a bottom electrode. A fixed magnet is disposed above the bottom electrode, a tunnel barrier is disposed on the fixed magnet, a free magnet is disposed on the tunnel barrier. In an embodiment, one of the free magnet or the fixed magnet includes a magnetic alloy consisting of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo, wherein the total amount of the one or more elements is less than or equal to 10 atomic percent of the total composition of the magnetic alloy. The memory device further includes an oxide layer disposed on the free magnet. A follower magnetic layer is disposed on the oxide layer, and a top electrode is disposed above the follower magnetic layer.

Example 5 : The memory device of example 4, wherein the magnetic alloy has a chemical composition (ΤεγΒιοο-γ)ιοο-χΜο _χ , where X is less than 10 and Y is greater than or equal to 80.

Example 6: The memory device of example 4, wherein the free magnet includes the magnetic alloy.

Example 7: The memory device of example 4, wherein the fixed magnet includes the magnetic alloy.

Example 8: The memory device of example 4 further includes a cap oxide on the free magnet, and a follower magnetic layer on the free magnet.

Example 9: The memory device of example 6, wherein the free magnet includes the magnetic alloy has a thickness between 1.Onm - 3nm.

Example 10: The memory device of example 7, wherein the fixed magnet includes the magnetic alloy has a thickness between l .Onm - 3nm

Example 1 1 : The memory device of example 8, wherein the follower magnetic layer includes the magnetic alloy and has a thickness between lnm -1.5nm

Example 12: The memory device of example 4 and 7, wherein the free magnet further includes a second magnetic alloy consisting of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo, wherein the total amount of the one or more elements is less than or equal to 10 atomic percent of the total composition of the alloy;

Example 13 : The memory device of example 4 or 6, wherein the free magnet further includes an intermediate magnetic layer between the tunnel barrier and the magnetic alloy.

Example 14: The memory device of example 4 or 7, wherein the fixed magnet further includes an intermediate magnetic layer between the tunnel barrier and the magnetic alloy.

Example 15 : The memory device of example 4, 6 or 13, wherein the intermediate magnetic layer has a thickness between 0. lnm and lnm and the magnetic alloy has a thickness between l .Onm and 2.9nm.

Example 16: The memory device of example 4, 7 or 14, wherein the intermediate magnetic layer has a thickness between 0. lnm and lnm and the magnetic alloy has a thickness between l .Onm and 2.9nm.

Example 17; The memory device of example 4, wherein the follower magnetic layer includes Co, Fe, and B.

Example 18: The memory device of example 4, wherein the tunnel barrier includes magnesium oxide (MgO).

Example 19: A method of fabricating a memory device includes forming a conductive interconnect structure above a substrate and forming a material layer stack for the memory device. Forming the material layer stack for the memory device includes forming a bottom electrode layer on the conductive interconnect structure, forming a fixed magnetic layer above the bottom electrode, forming a tunnel barrier on the fixed magnetic layer, forming a free magnetic layer including a magnetic alloy on the tunnel barrier layer, the magnetic alloy consists of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo. The method further includes forming an oxide layer on the free magnetic layer and forming a top electrode layer on the follower magnetic layer. The method further includes forming a mask above the top electrode and etching the material layer stack to form a memory device having sidewalls. The method further includes forming a dielectric spacer layer laterally adjacent to the sidewalls of the memory device.

forming a free magnetic layer including a magnetic alloy on the tunnel barrier layer, the magnetic alloy consisting of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo;

Example 20: The method of example 19, wherein the magnetic alloy is formed by a physical vapor deposition process.

Example 21 : The method of example 19 or 20, wherein the magnetic alloy is formed by co-sputtering iron and boron to form an iron-boron alloy and introducing one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo during the co- sputtering.

Example 22: The method of example 19, wherein forming the free magnetic layer includes first forming a thin layer of a magnetic material including Co, Fe and Bo on the tunnel barrier and then forming the magnetic alloy on the thin layer of magnetic material.

Example 23 : The method of claim 19, wherein the free magnetic layer comprising the magnetic alloy is formed to a thickness between l .Onm - 3nm.

Example 24: The method of claim 22, wherein the free magnetic layer comprising the magnetic alloy is formed to a thickness between 0.8nm-2.6nm.