FOR Low VOLTAGE BIPOLAR MEMORY DEVICES AND THEIR METHODS OF FABRICATION TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, phase change material based selector for low voltage bipolar memory devices and their methods of fabrication.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinkionenoteng transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Embedded memory with non-volatile memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. A non-volatile memory device such as magnetic tunnel junction (MTJ) memory device or resistive random access memory (RRAM) device is coupled with selector element to form a memory cell. A large collection of memory cells forms a key component of non-volatile embedded memory.

However, with scaling of memory devices, the technical challenges of assembling a vast number of memory cells presents formidable roadblocks to commercialization of this technology today. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a cross-sectional illustration of a memory cell disposed above a substrate, in accordance with an embodiment of the present disclosure.

Figure IB illustrates a plan view of the memory cell.

Figure 1C illustrates a cross-sectional illustration of a memory cell, in accordance with an embodiment of the present disclosure

Figure ID illustrates a cross-sectional view of a memory cell that includes a bipolar memory element such as a resistive random access memory (RRAM) device disposed above the conductive electrode, in accordance with an embodiment of the present disclosure.

Figure IE illustrates a cross- sectional view of a memory cell that includes a bipolar memory element such as a magnetic tunnel junction (MTJ) memory device disposed above a conductive electrode, in accordance with an embodiment of the present disclosure.

Figures 2A-2F illustrate cross-sectional and plan views of stacked memory cells, in accordance with an embodiment of the present disclosure.

Figure 2A illustrates a cross-sectional view of stacked memory cells that share a common wordline, in accordance with an embodiment of the present disclosure.

Figure 2B illustrates a cross-sectional view of stacked memory cells where the first selector element of the first memory cell shares a common wordline with the second selector element of a second memory cell, in accordance with an embodiment of the present disclosure.

Figure 2C illustrates a cross-sectional view of stacked memory cells where the first memory element of the first memory cell shares a common wordline with the second memory element of a second memory cell, in accordance with an embodiment of the present disclosure.

Figure 2D illustrates a cross-sectional view of stacked memory cells that share a common wordline, in accordance with an embodiment of the present disclosure.

Figure 2E illustrates a plan view of the memory cell along the direction A-A' in Figure

2A.

Figure 2F illustrates a plan view of the memory cell, along the direction B-B' in Figure 2A.

Figures 3A-3E illustrate cross-sectional views representing various operations in a method of fabricating a memory cell.

Figure 3A illustrates a wordline formed in an opening in a dielectric layer formed above a substrate.

Figure 3B illustrates the structure of Figure 3A following the formation of a selector material layer, a conductive electrode layer and a bipolar memory material layer stack

Figure 3C illustrates the structure of Figure 3B following the patterning of the bipolar memory material layer stack and the conductive electrode layer.

Figure 3D illustrates the structure of Figure 3C following the patterning of the selector material layer.

Figure 3E illustrates the structure of Figure 3D following the formation of a second dielectric layer on the wordline and on the dielectric layer and on the active memory device.

Figure 3F illustrates the structure of Figure 3E following the formation of a bitline on the uppermost surface of the memory element and on the uppermost surface of the second dielectric layer to complete formation of a memory cell.

Figure 4 shows simulated results depicting dependence of amorphous volume dependence on normalized current through an isolated selector element.

Figure 5 illustrates a current-voltage plot of an isolated selector element including a phase change material that has been cooled with a sharp trailing edge current pulse, in accordance with an embodiment of the present disclosure. Figure 6 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 7 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Phase change material based selector for low voltage bipolar memory devices and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations is described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Non-volatile memory devices such as a magnetic tunnel junction (MTJ) memory device or a resistive random access memory (RRAM) device depend on a phenomenon of resistance switching to store information The non-volatile memory device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. A non-volatile memory device may be coupled with a selector element to form a memory cell. The selector may be a volatile switching element that is placed in series with the non-volatile memory device. A large collection of such memory cells forms a key component of non-volatile embedded memory. Operating a memory cell including a selector and a nonvolatile memory element may require sufficiently low threshold selector turn-on voltages (e.g. less than or equal to IV) in order to minimize power consumption.

In an embodiment, a selector element includes a phase change material that does not undergo a phase transition from an amorphous to a crystalline state during a memory cell operation. In an embodiment, prior to operation of a memory cell, by passing a current through the crystalline phase change material, heat is generated in the material (by Joule heating). In an embodiment, when the phase change material is cooled down, the phase change material can relax to an amorphous state, a crystalline state or a state where the phase change material is partially amorphous and partially crystalline, or fully amorphous. In an embodiment, the final state of the phase change material has a property where the threshold turn-on voltage depends on the final state attained after a cooling process. In an embodiment, a phase change material that can have a tunable threshold turn-on voltage of approximately IV, is highly desirable for applications where a selector element is coupled to a memory element to form a memory cell.

In accordance with an embodiment of the present disclosure, a memory cell includes a wordline disposed above a substrate. A selector element is disposed above the wordline, where the selector element includes a phase change material. In an embodiment, the selector element includes a phase change material that exhibits at least two different states, but is fixed in one state for memory cell operation. In an embodiment, transitions within an amorphous state can be selectively initiated by application of voltage as will be discussed further below. Generally, a phase change material that can maintain a fixed crystal structure may be utilized as a selector material. In some embodiments, however, thin-film chalcogenide alloy materials are particularly suitable. In an embodiment, thin-film chalcogenide alloy materials can be used a material for reversible switching, however, in the present disclosure, such materials are utilized as a low voltage volatile switch.

In an embodiment, a bipolar memory element is disposed above the phase change material. In an embodiment, the bipolar memory element includes a non-volatile memory device such as a magnetic tunnel junction (MTJ) memory device or a resistive random access memory (RRAM) device. The bipolar memory element is designed to operate at sufficiently low voltages such as IV or less. In an embodiment, the total voltage requirement for operation of the memory cell including the selector element and the non-volatile memory element is less than 2V. In an embodiment, a conductive electrode is disposed between the selector element and the bipolar memory element for practical reasons. The memory cell further includes a bitline disposed above the selector element. In an embodiment, a large collection of memory cells each including a selector element and a bipolar memory element are utilized to form a non-volatile memory array. The non-volatile memory array formed by a memory cell at each intersection of a wordline and a bitline is, herein, refered to as a non-volatile cross-point memory array. A nonvolatile cross-point memory array can offer significant advantages for scaling to achieve high density memory.

Figure 1A illustrates a cross-sectional illustration of a memory cell 100A disposed above a substrate 140. The memory cell 100A includes a wordline 102 disposed above the substrate. In an embodiment, a selector element 104 is disposed above the wordline, the selector element 104 includes a phase change material. In an embodiment, a conductive electrode 106 with negligible resistance is disposed on the selector element 104. In an embodiment, a bipolar memory element 108 is disposed above the conductive electrode 106, and a bitline 110 is disposed above the bipolar memory element 108.

In an embodiment, the selector element 104 includes a phase change material that exhibits at least two different states. In an embodiment, the phase change material includes Ge and Te. In an embodiment, the phase change material further includes Sb. In an embodiment, the phase change material includes a ternary alloy of Ge, Te and Sb such as Ge2Sb2Tes. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy including at least one one element from the group V periodic table such as Te, Se, or S. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy which comprises at least one of Te, Se, or S, where said alloy further comprises one element from the group V periodic table such as Sb. In an embodiment, the phase change material includes a dopant selected from the group consisting of indium, gallium, nitrogen and , Si and Ge. In an embodiment, the dopant concentration is between 5% and 20% of the total composition of the phase change material. In an embodiment, the phase change material exhibits at least two different states, amorphous and crystalline with marked differences in electrical resistance. In an embodiment, the phase change material is in an amorphous state for application as a volatile selector element. In an embodiment, the selector element 104 has a thickness between 20nm-60nm.

In an embodiment, the conductive electrode 106 is disposed on the selector element 104. In an embodiment, the conductive electrode 106 includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the conductive electrode 106 has a thickness between 5nm-10nm.

In an embodiment, the bipolar memory element 108 includes a magnetic tunnel junction (MTJ) memory device as will be described further below in association with Figure ID. In an embodiment, the bipolar memory element 108 includes a resistive random access memory (RRAM) device as will be described further below in association with Figure IE.

In an embodiment, the wordline 102 includes a layer of metal such as W, Ti, Ta and Ru and Cu. In an embodiment, the wordline 102 includes an alloy such as WN, TiN, TaN. The wordline 102 has a thickness between 20nm-40nm. In an embodiment, the bitline 110 includes a layer of metal such as W, Ti, Ta and Ru and Cu. In an embodiment, the wordline 102 includes an alloy such as WN, TiN, TaN. The wordline 102 has a thickness between 20nm-40nm.

Figure IB illustrates a plan view of the memory cell 100A. In an embodiment, the wordline 102 and the bitline 110 are arranged in an orthogonal manner. An outline 101 of the selector element 104, conductive electrode 106 and bipolar memory element 108, relative to the bitline 110 and the wordline 102 is also illustrated in Figure IB. An embodiment where the selector element 104, the conductive electrode 106 and the bipolar memory element 108 are within an intersection between the wordline 102 and the bitline 110 is herein, referred to as a cross point memory cell.

Figure 1C illustrates a cross-sectional illustration of a memory cell lOOC where the bipolar memory element 158 is disposed on the wordline 102, a conductive electrode 156 is disposed on the bipolar memory element 158 and a selector element 154 is disposed above the conductive electrode 156. In an embodiment, the bipolar memory element 158 is substantially the same as the bipolar memory element 108, the conductive electrode 156 is substantially the same as the conductive electrode 106 and the selector element 154 is substantially the same as the selector element 104.

Figure ID illustrates a cross-sectional view of a memory cell 100D that includes a bipolar memory element such as a resistive random access memory (RRAM) device 120 disposed above the conductive electrode 106. In an embodiment, the RRAM device 120 includes a bottom electrode 122, a switching layer 124 including a metal oxide disposed on the bottom electrode 122, an oxygen exchange layer 126 disposed on the switching layer 124, and a top electrode 128 disposed on the oxygen exchange layer 126. In an embodiment, the RRAM device 120 has a combined total thickness of the individual layers between 60nm-100nm and width between lOnm and 50nm.

Figure IE illustrates a cross- sectional view of a memory cell 100E that includes a bipolar memory element such as a magnetic tunnel junction (MTJ) memory device 150 disposed above a conductive electrode 106. In an embodiment, the MTJ device 150 includes a bottom electrode 1 2 disposed above the conductive electrode 106, a fixed magnet 154 disposed above the bottom electrode 152, a tunnel barrier 156 including an MgO disposed on the fixed magnet 154, a free magnet 158 disposed on the tunnel barrier 156 and a top electrode 160 disposed on the free magnet 158. In an embodiment, the MTJ device 150 has a combined total thickness of the individual layers between 60nm-100nm and width between lOnm and 50nm.

Figures 2A-2D illustrate cross-sectional views of stacked memory cells, in accordance with embodiments of the present invention.

Figure 2A illustrates a cross-sectional view of stacked memory cell 200A where a first memory cell 204 and a second memory cell 214 share a common wordline. In an embodiment, the stacked memory cell 200A includes a first bitline 202, a first memory cell 204 on the first bitline 202. In an embodiment, the first memory cell 204 includes a first selector element 206 including a phase change material disposed on the first bitline 202, a first conductive electrode 208 disposed on the first selector element 206 and a first bipolar memory element 210 disposed on the first conductive electrode 208. A wordline 212 is disposed on the first memory cell 204.

In an embodiment, a second memory cell 214 is disposed on the wordline 212. In an embodiment, the second memory cell 214 includes a second selector element 216 including a phase change material disposed on the wordline 212, a second conductive electrode 218 disposed on the second selector element 216 and a second bipolar memory element 220 disposed on the second conductive electrode 218. A second bitline 222 is disposed on the second memory cell 214.

In an embodiment, the first selector element 206 includes a phase change material that exhibits at least two different states. In an embodiment, the phase change material includes Ge and Te. In an embodiment, the phase change material further includes Sb. In an embodiment, the phase change material includes a ternary alloy of Ge, Te and Sb such as Ge2Sb2Tes. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy including at least one of Te, Se, or S. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy which comprises at least one of Te, Se, or S, where said alloy further comprises one element from the group V periodic table such as Sb. In an embodiment, the phase change material includes a dopant selected from the group consisting of indium, gallium, nitrogen and, Si and Ge. In an embodiment, the dopant concentration is between 5% and 20% of the total composition of the phase change material. In an embodiment, the phase change material exhibits at least two different states, amorphous and crystalline with marked differences in electrical resistance. In an embodiment, the phase change material is in an amorphous state for application as a volatile selector element. In an embodiment, the first selector element 206 has a thickness between 20nm-60nm. In an embodiment, the second selector element 216 is substantially the same as the first selector element 206.

In an embodiment, the first conductive electrode 208 is disposed on the selector element 104. In an embodiment, the first conductive electrode 208 includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the first conductive electrode 208 has a thickness between 5nm-10nm. In an embodiment, the second conductive electrode 218 is substantially the same as the first conductive electrode 208.

In an embodiment, the first memory device 210 includes a magnetic tunnel junction (MTJ) memory device as described in association with Figure ID. In an embodiment, the memory device 210 includes a resistive random access memory (RRAM) device as described in association with Figure IE. In an embodiment, the second memory device 220 is substantially the same as the first memory device 210. In an embodiment, when the first memory device 210 includes a magnetic tunnel junction (MTJ) memory device, then the second memory device 220 also includes a magnetic tunnel junction (MTJ) memory device to ensure variation between the various memory cells are minimized during stacked memory cell operation. In an embodiment, when the first memory device 210 includes a resistive random access memory (RRAM) device, then the second memory device 220 also includes a resistive random access memory (RRAM) device.

In an embodiment, the wordline 212 includes substantially the same material as the wordline 102 described in association with Figure 1 A. In an embodiment, the first bitline 202 and the second bitline 222 each include substantially the same material as the bitline 110 described in association with Figure 1 A.

Figure 2B illustrates a cross-sectional view of a memory cell 200B where the first selector element 206 and the second selector element 216 share a common wordline. In an embodiment, a first memory cell 230 includes the first bipolar memory element 210 disposed on the first bitline 202, the first conductive electrode 208 disposed on the first bipolar memory element 210 and the first selector element 206 disposed on the first conductive electrode 208. The wordline 212 is disposed on the first memory cell 230. In an embodiment, the second memory cell 214 is disposed on the wordline 212. The second memory cell 214 includes the second selector cell 216.

Figure 2C illustrates a cross-sectional view of stacked memory cell 200C where the first memory element 210 of the first memory cell 204, shares a common wordline 212 with the second memory element 220 of a second memory cell 240. In an embodiment, the first memory cell 204 is disposed on the first bitline 202. The wordline 212 is disposed on the first memory cell 204. In an embodiment, the second memory cell 240 includes the second memory element 220 disposed on the wordline 212, the second conductive electrode 218 disposed on the second memory element 220 and the second selector element 216 disposed on the second conductive electrode 218.

Figure 2D illustrates a cross-sectional view of a stacked memory cell 200D where the second memory cell 240 is disposed above the first memory cell 230. In an embodiment, wordline 212 is disposed between the second memory cell 240 and the first memory cell 230.

Figure 2E illustrates a plan view of the memory cell 200A along the direction A-A' in Figure 2A. In an embodiment, the wordline 212 and the first bitline 202 are arranged in an orthogonal manner. An outline of the first memory cell 204 relative to the first bitline 202 and the wordline 212 is also illustrated in Figure 2E. An embodiment where a first memory cell such as first memory cell 204 is within an intersection between the wordline 212 and the first bitline 202, is referred to as a first cross point memory cell.

Figure 2F illustrates a plan view of the memory cell 200A, along the direction B-B' in Figure 2A. In an embodiment, the wordline 212 and the second bitline 222 are arranged in an orthogonal manner. An outline of the second memory cell 214 relative to the second bitline 222 and the wordline 212 is also illustrated in Figure 2B. An embodiment where the second memory cell 214 is within an intersection between the wordline 212 and the second bitline 222, is referred to as a second cross point memory cell.

Figures 3A-3E illustrate cross-sectional views representing various operations in a method of fabricating a memory cell.

Figure 3 A illustrates a wordline 300 formed in an opening in a dielectric layer 301 formed above a substrate 302.

In an embodiment, the substrate 302 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 302 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

In an embodiment, the wordline 300 is formed in a dielectric layer 301 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the wordline 300 includes a barrier layer, such as titanium nitride, ruthenium, tantalum, tantalum nitride, and a fill metal, such as copper, tungsten. In another embodiment, the wordline 300 includes a layer of a single material such as TiN or TaN. In an embodiment, the wordline 300 is fabricated using a subtractive etch process when materials other than copper are utilized. In one such embodiment, the wordline 300 includes a material such as but not limited to titanium nitride, ruthenium, tantalum, tantalum nitride. In an embodiment, the dielectric layer 301 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 301 has an uppermost surface substantially co- planar with an uppermost surface of the wordline 300. In an embodiment, the dielectric layer 301 has a total thickness between 70nm-300nm. In an embodiment, wordline 300 is electrically connected to a circuit element such as an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory.

Figure 3B illustrates the structure of Figure 3A following the formation of a selector material layer 309 on the wordline 300, formation of a conductive electrode layer 311 on the selector material layer 309, formation of a bipolar memory material layer stack 313 on the conductive electrode layer 311.

In an embodiment, the selector material layer 309 including a phase change material is blanket deposited on the wordline 300 and on the dielectric layer 301 by an evaporation or by chemical vapor deposition (CVD) process. In an embodiment, the chemical vapor deposition process is enhanced by plasma techniques such as RF glow discharge (plasma enhanced CVD) to increase the density and uniformity of the film. In an embodiment, a gas mixture including chalcogen atoms such as tellurium, sulfur, or selenium is introduced into a CVD or PECVD chamber along with argon gas and reacted with an element such as but not limited to Sb, Hf, Ti, Ta, Ge, Si and W to form a phase change material that is amorphous. In an embodiment, the phase change material is crystalline as deposited. In an embodiment, the deposition takes place at temperatures between 100-500 degrees Celsius. In an embodiment, the selector material layer 309 includes phase change material. In an embodiment, the phase change material includes a ternary alloy of Ge, Te and Sb such as Ge2Sb2Te5. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy including at least one of Te, Se, or S. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy which comprises at least one of Te, Se, or S, where said alloy further comprises one element from the group V periodic table such as Sb. In an embodiment, the selector material layer 309 is doped during the deposition process with one or elements selected from the group consisting of indium, gallium, nitrogen or silicon. In an embodiment, doping the selector material layer 309 enhances conductivity through the selector material layer 309. In an embodiment, an increase in conductivity can lower a threshold voltage at which a selector layer 309 can be operated. In an embodiment, the total amount of the one or more doping elements is between 5% and 20% atomic percent of the total composition of the selector material layer 309. In an embodiment, the phase change material exhibits at least two different states, amorphous and crystalline with marked differences in electrical resistance. In an embodiment, the phase change material is in an amorphous state for application as a volatile selector element. In an embodiment, selector material layer 309 is deposited to a thickness between 20nm-60nm.

In an embodiment, the conductive electrode layer 311 is blanket deposited on the selector material layer 309. In an embodiment, the conductive electrode layer 311 is deposited by a PVD process. In an embodiment, the conductive electrode layer 311 is deposited to a thickness between 5nm-10nm. The conductive electrode layer 311 includes a material that is substantially the same as the material of the conductive electrode 106. Exemplary materials for the conductive electrode include TiN or TaN and provide significant ease during memory cell fabrication.

In an embodiment, the bipolar memory material layer stack 313 is blanket deposited on the on the conductive electrode layer 311. In an embodiment, the bipolar memory material layer stack 313 includes at least 3 or more layers to fabricate a magnetic tunnel junction (MTJ) memory element. In one embodiment, the bipolar memory material layer stack for an MTJ memory element is deposited using a PVD process. In another embodiment, the bipolar memory material layer stack 313 includes at least 3 or more layers to fabricate a resistive random access memory (RRAM) memory element. In one embodiment, the bipolar memory material layer stack for an RRAM memory element is deposited using a PVD process.

In an embodiment, an uppermost layer of bipolar memory material layer stack 313 includes an uppermost electrode layer 313 A (contained within dashed lines) that will act as a hardmask for patterning the bipolar memory material layer stack 313 as well as the selector material layer 309. In an embodiment, the uppermost electrode layer has a thickness between 70nm-100nm.

In an embodiment, when the bipolar memory material layer stack 313 includes layers for an MTJ memory element the bipolar memory material layer stack 313 undergoes a process of anneal. In an embodiment, the process of anneal is carried out at temperatures between 300-400 degrees Celsius.

Figure 3C illustrates the structure of Figure 3B following the patterning of the bipolar memory material layer stack 313 and the conductive electrode layer 31 1. In an embodiment, a photoresist mask is formed on an uppermost surface of the bipolar memory material layer stack 313. In an embodiment, the photoresist mask defines a location where a memory cell will be subsequently formed. In an embodiment, a plasma etch process is utilized to pattern the bipolar memory material layer stack 313 and the conductive electrode layer 31 1 to form a memory element 314 and a conductive electrode 312. In an embodiment, the plasma etch also etches the uppermost electrode 313 A to form an uppermost electrode 314A.

Figure 3D illustrates the structure of Figure 3C following the patterning of the selector material layer 309. In an embodiment, a plasma etch process is utilized to pattern the selector material layer 309 to form a selector element 310. In an embodiment, the plasma etch process erodes over 50% of the uppermost electrode 314A to form memory element 314, a conductive electrode 312 and selector element 310. The memory element 314, a conductive electrode 312 and selector element 310 are herein referred to as an active memory device 316.

Figure 3E illustrates the structure of Figure 3D following the formation of a second dielectric layer 318 on the wordline 300 and on the dielectric layer 301 and on the active memory device 316. In an embodiment, a second dielectric layer 318 is blanket deposited on the surface of the memory element 314, on sidewalls of the conductive electrode 312, on sidewalls of the selector element 310, on the wordline 300 and on the dielectric layer 301. In an embodiment, the dielectric layer 301 includes an insulating material such as but not limited to silicon oxide, silicon carbide, carbon doped nitride and silicon nitride. In an embodiment, the second dielectric layer 318 is planarized. In an embodiment, the planarization process removes a portion of the uppermost electrode 314A. In an embodiment, the planarization process forms a second dielectric layer 318 having an uppermost surface that is co-planar or substantially coplanar with an uppermost surface of the memory element 314.

Figure 3F illustrates a bitline 320 formed on the uppermost surface of the memory element 314 and on the uppermost surface of the second dielectric layer 318 to complete formation of a memory cell 370. In an embodiment, a layer of a conductive material is blanket deposited on the uppermost surface of the memory element 314 and on the uppermost surface of the second dielectric layer 318. The layer of a conductive material is then patterned to form a bitline 320. In an embodiment, the layer of a conductive material includes a material such as W, TiN, TaN or Ru. In an embodiment, the bitline 320 is formed by using a dual damascene process (not shown) and includes a barrier layer such as Ru, Ta or Ti and a fill metal such as W or Cu.

The various process operations described in association with Figures 3 A-3F can also be utilized to fabricate the memory cell lOOC depicted in Figure 1C, although details of the sequences are not described here. In an embodiment, when the memory element 108 includes an MTJ device, where the MTJ device is formed below a selector element 104 as depicted in Figure 1C , a selector material layer utilized to form the selector element 104 cannot be deposited at temperature greater than the temperature of the MTJ anneal process described in connection with Figure 3B. In an embodiment, the MTJ anneal process is carried out temperatures less than or equal to 400 degrees Celsius.

Figure 4 shows simulated results depicting dependence of amorphous volume on normalized current through an isolated selector element such as a selector element 310. In an embodiment, the selector element 310 has a length, L that forms a dimension of the volume of the selector element. In an embodiment, by passing a current, I, through the crystalline phase change material, heat is generated in the material (by Joule heating). In an embodiment, by passing a critical current, Ic, the heat generated in the phase change material is in a melted state. In an embodiment, in a melted state the entire phase change material is fully

conductive In an embodiment, the extent to which the phase change material is in a melted state depends on the magnitude of the current injected through the phase change material and the duration of the current pulse.

In an embodiment, when the phase change material is cooled down, the phase change material can relax to an amorphous state, a crystalline state or a state where the phase change material is partially amorphous and partially crystalline. In an embodiment, the manner in which the material is cooled down controls to an extent the final state of the phase change material attained. In an embodiment, when a fast trailing edge pulse is utilized to cool down a phase change material, the phase change material can attain an amorphous state. In an embodiment, by changing the extent of the cross sectional area of an amorphous portion of the phase change material, the resistance of the phase change material can be set.

The vertical axis of the plot in Figure 4 illustrates the length of the phase change material that has become amorphous as a function of the current through the selector element 310 having a crystalline phase change material. In an embodiment, X represents the point below which no phase change takes place. In an embodiment, when X is between 0. ImA-lmA there is no phase change to an amorphous state. In an embodiment, Y represents the length, L, of the selector element. In an embodiment, when X is between 0. ImA-lmA, Y is between 5nm-50nm.

In an embodiment, in order to conduct current through a phase change material that is relaxed to a amorphous state, a voltage greater than a threshold voltage, VTH, must be applied between two terminals of a phase change material. Referring again to the plot in Figure 4, in an embodiment, the device threshold voltage, VTH, depends on the height of the amorphous region. Depending in embodiment, the height can be tuned to provide a specific threshold voltage, VTH.

Figure 5 illustrates a current-voltage plot of an isolated selector element such as a selector element 310, in accordance with an embodiment of the present disclosure. In an embodiment, the volume of the amorphous phase change material is set such that the threshold voltage, VTH, is approximately 0.7V - IV. In an embodiment, when the voltage through the selector element is increased, there is no current conduction until a value of approximately 0.9V is reached. In an embodiment, at 0.9V an isolated selector element such as a selector element 310 conducts.

Figure 6 illustrates a computing device 600 in accordance with one embodiment of the disclosure. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606 The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., cross point memory), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 6G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more embedded memory modules with a large collection of memory cells such as memory cell 370, fabricated using a selector element 310 and a memory element 314 described in association with Figure 3F, in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes embedded memory with a large collection of memory cells such as memory cell 370 including a magnetic tunnel junction based memory device or a resistive random access memory device coupled with a volatile selector including a phase change material, that is integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device 600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements such as memory cell 370, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Figure 6 illustrates an integrated circuit (IC) structure 600 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 600 is an intervening structure used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die. The second substrate 604 may be, for instance, a memory module, a computer mother, or another integrated circuit die. The memory module may include one or more memory cells such as a memory cell 370 or one or more memory cells 200A, 200B, 200C and/or 200D. Generally, the purpose of an integrated circuit (IC) structure 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the integrated circuit (IC) structure 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the integrated circuit (IC) structure 600. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 600.

The integrated circuit (IC) structure 600 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 600 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a

semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials

The integrated circuit (IC) structure 600 may include metal interconnects 608 and via 610, including but not limited to through-silicon vias (TSVs) 610. The integrated circuit (IC) structure 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, memory device that include a large collection of memory cells such as memory cell 370, 200A, 200B, 200C and 200D, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 600. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 600.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a memory cell 370. A large array of consisting of memory cell 370 may be used in an embedded non-volatile memory application.

Figure 7 illustrates an integrated circuit (IC) structure 700 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 700 is an intervening structure used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer mother, or another integrated circuit die. The memory module may include one or more memory devices such as a memory device 100 or a memory device 370. Generally, the purpose of an integrated circuit (IC) structure 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the integrated circuit (IC) structure 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the integrated circuit (IC) structure 700. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 700.

The integrated circuit (IC) structure 700 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 700 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a

semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure 700 may include metal interconnects 708 and via 710, including but not limited to through-silicon vias (TSVs) 710. The integrated circuit (IC) structure 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, memory device such as memory devices 100 and 370, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 700. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 700.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a memory device 370. A large array of consisting of memory device 370 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include selectors for low voltage bipolar memory devices and methods to form the same.

Specific embodiments are described herein with respect to memory devices such as magnetic tunnel junction based memory devices and resistive random access based memory devices coupled with a selector including a phase change material. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory

devices. Such non-volatile memory devices may include, but are not limited to, certain class of ferroelectric memory devices or conductive bridge memory devices.

Example 1 : A memory device includes a wordline above a substrate. A selector element is disposed above the wordline, where the selector element includes a phase change material. A bipolar memory element is disposed above the wordline. A conductive electrode is disposed between the selector element and the bipolar memory element and a bitline is disposed above the wordline.

Example 2: The memory device of example 1, wherein the phase change material inlcudes Ge and Te.

Example 3 : The memory device of example 2, wherein the phase change material further inlcudes Sb.

Example 4: The memory device of example 1, 2 or 3 wherein the phase change material inlcudes a dopant selected from the group consisting of indium, gallium, nitrogen and silicon.

Example 5: The memory device of example 4, wherein the dopant concentration is between 5% and 20% of the total composition of the phase change material.

Example 6: The memory device of example 1, wherein the selector element has a threshold voltage that is less than or equal to IV.

Example 7: The memory device of example 1 or 6, wherein the selector element is above the bipolar memory element.

Example 8: The memory device of example 1 or 6, wherein the selector element is below the bipolar memory element.

Example 9: The memory device of example 1, wherein the bipolar memory element inlcudes a resistive random access memory (REAM) device.

Example 10: The memory device of example 1, wherein the bipolar memory element inlcudes a magnetic tunnel junction (MTJ) device.

Example 11 : A memory device includes a first bitline above a substrate. A first memory cell is disposed on the first bitline, where the first memory device includes a first selector element above the first bitline, and further where the first selector element includes a phase change material. A first bipolar memory element is disposed above the first bitline. A first conductive electrode is disposed between the selector element and the bipolar memory element. A wordline is disposed on the first memory device. A second memory device is disposed on the wordline, where the second memory device includses a second selector element above the wordline. The second selector element includes a phase change material. A second bipolar memory element is disposed above the wordline, a second conductive electrode between the second selector element and the second bipolar memory element, and a second bitline on the second memory device.

Example 12: The memory device of example 11, wherein the phase change material inlcudes Ge and Te.

Example 13 : The memory device of example 12, wherein the phase change material further inlcudes Sb.

Example 14: The memory device of example 11, 12 or 13, wherein the phase change material inlcudes a dopant selected from the group consisting of indium, gallium, nitrogen and silicon.

Example 15 : The memory device of example 14, wherein the dopant concentration is between 5 and 20 atomic percent of the total composition of the phase change material.

Example 16: The memory device of example 11, wherein the first selector element and the second selector element each have a threshold turn on voltage that is less than or equal to IV.

Example 17: The memory device of example 11, wherein the first selector element is above the first bipolar memory element, and the second selector element is below the second bipolar memory element.

Example 18: The memory device of example 11, wherein the first selector element is below the first bipolar memory element and the second selector element is above the second bipolar memory element. Example 19: The memory device of example 11, wherein the first bipolar memory and the second bipolar memory element each comprise a resistive random access memory (RRAM) device.

Example 20: The memory device of example 11, wherein the first bipolar memory and the second bipolar memory element each comprise a magnetic tunnel junction (MTJ) device.

Example 21 : Method to fabricate a memory device includes forming a bitline in a first dielectric layer above a substrate. The method further includes forming a bipolar memory material layer stack above the bitline and forming a conductive electrode layer above the bipolar memory material layer stack. The method further includes forming a selector material layer comprising a phase change material on the conductive electrode layer. The method further includes forming a hardmask layer above the selector material layer and patterning the hardmask layer to form a hardmask. The method further includes forming using the patterned hardmask to pattern the selector material layer to form a selector element and patterning the conductive electrode layer to form a conductive electrode. The method further includes forming using the hardmask to pattern bipolar memory material layer stack and forming a second dielectric layer on the hardmask, on sidewalls of the selector element and on sidewalls of the bipolar memory element. The method further includes forming planarizing the second dielectric layer to expose an uppermost surface of the bipolar memory element and forming a wordline on the uppermost surface of the bipolar memory element and on an uppermost surface of the second dielectric layer.

Example 22: The method of example 21, further includes doping the selector material layer during a selector material layer deposition process with one or elements selected from the group consisting of indium, gallium, nitrogen or silicon, wherein the total amount of the one or more elements is between 5 and 20 atomic percent of the total composition of the selector material layer.

Example 23 : The method of example 21, wherein forming the bipolar memory material layer stack inlcudes forming a material layer stack for a resistive random access memory device.

Example 24: The method of example 21, wherein forming the bipolar memory material layer stack inlcudes forming a material layer stack for a magnetic tunnel junction device.

Example 2 : The method of example 21, wherein forming the bitline inlcudes forming a first electrode having a length along a first direction, and forming the wordline includes depositing a conductive material on the second dielectric layer and pattering the conductive material to form the wordline comprising an electrode having a length orthogonal to the first direction.