Phase Detector and Phase Locked Loop

The present invention relates to a phase detector and to a phase locked loop including such a phase detector.

Most frequency synthesizers using phase locked loop techniques nowadays use a phase detector comprising a phase-frequency detector (PFD) 2 and a charge pump 3 as shown in Figure 1 of the accompanying drawings. The PFD 2 comprises D-type flip- flops 4 and 5 having clock inputs CLK forming first and second inputs of the PFD for receiving a reference frequency signal F _REF and a signal Fvcofrom, or derived from, a voltage controlled oscillator (VCO) of the phase locked loop (PLL). The flip-flops have data inputs D connected to receive a logic level 1 and outputs Q for supplying output signals UP(lag) and DN(lead) of the PFD. The Q outputs of the flip-flops 4 and 5 are also connected to the inputs of an AND gate 6. The output of the gate 6 is connected to the input of a delay circuit 7, whose output is connected to reset inputs R of the flip- flops 4 and 5.

The charge pump 3 comprises a current source 8 connected in series with an electronic switch 9 between a positive supply line and an output "VCO control" of the phase detector. A current sink 10 is connected in series with an electronic switch 1 1 between a negative supply line and the phase detector output. The switches 9 and 10 are controlled by the output signals UP(lag) and DN(lead) of the PFD 2. The current source 8 is arranged to provide a constant current to the phase detector output of value Ip _{MP UP} whereas the current sink 10 is arranged to sink a constant current from the phase detector output of value I _PMP _ _DN - The current source 8 and the current sink 10 are effectively switched on or off by the switches 9 and 10 in accordance with the output signals of the PFD 2.

Figure 2 of the accompanying drawings illustrates waveforms occurring within the phase detector of Figure 1 when it is being used as part of a phase locked loop which is out of lock, i.e. with the frequencies of the signals F _REF and F _V co being substantially the same but with the signal F _V co lagging behind the signal F _REF - When the reference frequency signal F _REF rises, a logic level 1 is clocked into the flip-flop 4 and appears at the output Q. At the next rising edge of the signal F _V co the flip-flop 5 likewise clocks a logic level 1 to its Q output. Both inputs of the AND gate 6 now receive a logic level 1 and the gate therefore supplies a logic level 1 to the delay circuit 7. The delay circuit 7

delays the rising edge of this signal by a predetermined fixed amount and then supplies a reset signal to the reset inputs R of the flip-flops 4 and 5. The flip-flops 4 and 5 are thus reset simultaneously and the output signals at the Q outputs of the flip-flops fall to logic level 0 simultaneously.

The current source 8 is switched on (or into circuit) by the switch 9 whenever the output signal UP(lag) is at logic level 1. Similarly, the current sink 10 is switched on (or into circuit) by the switch 1 1 whenever the output signal DN(lead) is at logic level 1. In the circumstances illustrated in Figure 2, the output signal UP(lag) is at logic level 1 whereas the output signal DN(lead) is at logic level 0 between the rising edges of the input signals. During this period, the current source 8 is connected to the phase detector output so that the signal at the output rises. When the output signal DN(lead) rises, the current sink 10 is switched on while the current source 8 remains switched on until both output signals fall to logic level 0, when the current source 8 and the current sink 10 are switched off (or disconnected). The current source 8 and the current sink 10 are designed to pass the same current so that, when both are switched on, the voltage at the phase detector output should not change. Similarly, when the source 8 and the sink 10 are both switched off, the voltage at the phase detector output should remain constant.

Figure 3 of the accompanying drawings is a diagram similar to Figure 2 but illustrating the waveforms when the phase locked loop including the phase detector of Figure 1 is in frequency and phase lock. In this condition, the rising edges of the input signals F _REF and Fvco occurs simultaneously so that the logic level 1 is simultaneously clocked into the flip-flops 4 and 5 and the outputs signals UP(lag) and DN(lead) rise simultaneously. The output of the AND gate 6 rises substantially simultaneously and the rising edge is delayed by the delay circuit 7 by the fixed predetermined amount before resetting the flip-flops 4 and 5. The output signals thus fall to the logic level 0 simultaneously.

In this condition, the source 8 and the sink 10 operate simultaneously so that there is no net flow of current into or out of the output of the phase detector. The output signal "VCO control" thus remains at a constant voltage.

The use of a PFD in a phase detector has the advantage that it is able to achieve both frequency and phase lock so that there is no need for a separate frequency acquisition loop within a phase locked loop. Also, when the loop is in lock, the charge pump may

be deactivated, for example by holding open the switches 9 and 1 1. The charge pump output thus enters a high impedance state, which allows the control voltage supplied by the phase detector to be "quiet" and therefore reduces VCO phase noise.

In practice, if the charge pump 3 is always off when the loop is locked, this results in a "dead zone" in the control characteristics of the PLL and this can result in higher levels of close-in phase noise. This is avoided by arranging for the current source 8 and the current sink 10 to be turned on for equal amounts of time when the PLL is in lock.

In practice, if the source and sink currents l _PM p up and I _{PMP DN} are not exactly matched, there will be a net injection of charge into the VCO during each cycle of operation. Further, there may be various sources of leakage current at the VCO control node or between the output of the phase detector and the VCO node. For example, current leakages may occur in the devices forming the charge pump 3 when in the off state or through components of a loop filter between the phase detector and the VCO. Further, leakages may occur through electrostatic discharge (ESD) protection diodes at connection pads of the circuit and at the VCO input.

The net effect of such current mismatches and leakages is to cause the VCO control voltage to drift away from the value required to maintain frequency and phase lock. The negative feedback action of the phase locked loop compensates for this by injecting an equal and opposite amount of charge at the output of the phase detector so as to compensate for the total leakage. The waveform diagram of Figure 4 of the accompanying drawings illustrates this.

Figure 4 illustrates the effect of the signal F _V co starting to lag the reference signal F _REF because of the leakage. The time offset between the input signals resulting from the drift caused by the leakage currents is illustrated as T. The width of the pulses of the output signal UP(lag) is thus greater than the width of the pulses of the output signal DN(lead) so that the current source 8 is turned on for longer than the current sink 10 during each cycle and injects charge into the output of the phase detector. The bottom waveform in Figure 4 shows the effect of this on the output signal "VCO control" to an exaggerated vertical scale as compared with Figures 2 and 3. The net injection of charge causes the VCO control voltage to rise. When the charge pump 3 has switched off, the current leakages cause the VCO control voltage to fall.

The phase locked loop thus settles into lock with the input signals aligned in frequency but with a small phase offset. The phase offset is a function of the leakage current and is given by:

φ = 2πτ / T = I leak /I pump

Where φ is the phase offset, T is the time offset between the input signals, T is the period of the reference signal, IJeak is the net leakage current and l_pump is the current produced by the current source 8. In the case where the total leakage current is of the opposite polarity, then the current produced by the current source 8 is replaced by the current produced by the current sink 10.

The current leakages thus give rise to a ripple in the VCO control voltage at the frequency of the reference signal F _REF - This has the effect of frequency-modulating the VCO so that spurious frequencies or "spurs" appear in the output spectrum of the VCO. This is generally highly undesirable.

As semiconductor processing technologies migrate towards deep submicron dimensions and oxide thicknesses decrease, leakage currents increase despite the introduction of insulation materials of high dielectric constants. Thus, in advanced process technologies, the effects of leakage such as those described above are becoming more severe.

US 6473485 discloses a known technique for providing leakage current compensation in a phase locked loop using a phase detector of the type illustrated in Figure 1 of the accompanying drawings. According to this known technique, a fixed calibration cycle is performed to measure and then compensate for charge pump leakage current. A digital circuit examines the phase offset between the up and down pulses and generates a corresponding digital word which is supplied to a digital-analog converter (DAC). The DAC converts the digital word to a corresponding current which is applied as a compensation current in the loop. The calibration process is completed when the difference between the up and down pulse widths is reduced to less than an acceptable value. The resulting digital word is then stored and supplied to the DAC during normal operation of the phase locked loop to apply a fixed and constant compensation current.

During operation of the phase locked loop, changes in the actual leakage current occur, for example because of changes in operating conditions such as temperature, supply voltage and operating frequency. When such changes occur, the compensation current supplied by the DAC is no longer appropriate and compensation of leakage current is lost. The problems described above therefore return and persist unless the calibration cycle is repeated. However, repeating the calibration cycle causes disturbances in the operation of the PLL and is therefore undesirable or impossible during normal operation.

According to a first aspect of the invention, there is provided a phase detector comprising: a phase-frequency detector having first and second inputs and being arranged to provide at least one output signal comprising a series of pulses, each of whose width is a function of the frequency and phase difference between signals at the first and second inputs; and a pulse width to current converter response to the output signal or signals for continuously supplying at an output a direct output current whose value is a function of the pulse width of the or each output signal.

The value may be a substantially continuous function of the pulse width.

The value may be a substantially monotonic function of the pulse width.

The converter may have an output stage comprising a controllable current source and a controllable current sink. As an alternative, the converter may have an output stage comprising at least one transconductance amplifier.

The converter may further comprise a charge pump arranged to be controlled by the phase-frequency detector and having an output connected to the output of the converter. The charge pump may be arranged to be disabled when the signals at the first and second inputs are at least substantially in phase lock.

The converter may comprise, for the or each output signal, an integrator for integrating each pulse and a sample-and-hold circuit for sampling and holding an output signal of the integrator.

The phase-frequency detector may be arranged to provide first and second output signals whose pulses have first edges triggered by first edges of pulses of the signals

at the first and second inputs, respectively. The first edges of the pulses of the first and second output signals may be rising edges. The first edges of the pulses at the first and second inputs may be rising edges. The phase-frequency detector may be arranged to provide the pulses of the first and second output signals with substantially simultaneous second edges. The second edges may be falling edges. The phase- frequency detector may be arranged to provide the second edges with a substantially fixed delay after the first edge of the later of the signals at the first and second inputs to have a first edge.

According to a second aspect of the invention, there is provided a phase-locked loop comprising a phase detector according to the first aspect of the invention.

It is thus possible to provide an arrangement which compensates for mismatches and leakage currents while avoiding ripple and the effects thereof. When used in a phase locked loop, calibration cycles can be avoided because compensation may be provided continuously and may be continuously adjusted so as to compensate for changes in leakage currents during operation. Frequency spurs in the output spectrum can be avoided or at least greatly reduced in amplitude.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a block schematic diagram of a known type of phase detector;

Figures 2 to 4 are waveform diagrams illustrating operation of the phase detector of Figure 1 ;

Figure 5 is a block schematic diagram of a phase detector constituting an embodiment of the invention;

Figure 6 is a waveform diagram illustrating operation of the phase detector of Figure 5;

Figure 7 is a more detailed block diagram of part of the phase detector of Figure 5;

Figures 8 and 9 are waveform diagrams illustrating operation of the part of the phase detector shown in Figure 7;

Figures 10 and 11 are more detailed block diagrams of alternative arrangements of part of the phase detector of Figure 5;

Figure 12 is a block schematic diagram of a phase detector constituting another embodiment of the invention; and

Figure 13 is a block schematic diagram of a phase locked loop including a phase detector constituting an embodiment of the invention.

The phase detector shown in Figure 5 comprises a phase-frequency detector (PFD) 2 of the type shown in Figure 1. However, any equivalent or similar PFD may be used in the phase detector. The phase detector of Figure 5 differs from that of Figure 1 in that the charge pump 3 is omitted and replaced by a current (I) control circuit 15 and an output stage 16. The net current leakage present in a phase locked loop containing the phase detector is illustrated in broken lines as a current sink 17 providing the total net leakage current L _EAK -

The output stage 16 comprises a continuously controllable current source 18, which supplies a continuously variable continuous direct current l _PO s, and a continuously controllable current sink 19, which sinks a continuously variable continuous direct current I _NEG - The control circuit 15 receives the output signals UP and DN from the PFD 2 and converts these into control signals for controlling the current source 18 and the current sink 19. In particular, the control circuit 15 controls the source 18 and the sink 19 so as to provide a pulse width to current converter providing a continuously supplied direct output current whose value is a function of the pulse widths of the output signals of the PFD 2.

Operation of the phase detector is illustrated in Figure 6 for the case where the signal Fvco has substantially the same frequency as the reference signal F _REF but lags it in phase. The output signals UP and DN of the PFD 2 comprise pulses of duration Tlag and Tlead, respectively. The current l _PO s and I _NEG are given by the following expressions:

IPOS = K(Tlag)

I _NEG = K(Tlead)

where K is a fixed gain of the control circuit 15 and the output stage 16. The net current required to balance the current leakages is given by:

IN _ET = K(Tlag-Tlead) and must be equal to the leakage current I _LEAK - Thus:

l _NET =K(Tlag-Tlead) = L _EAK

Which may be rewritten as:

K=l _LEA κ/(Tlag-Tlead)

Since (Tlag-Tlead) is the difference between the up and down pulse widths, it is desirable for K to have a higher value in order to provide a lower value of phase offset when the PLL is in lock. Any mismatch between the currents lpos and I _NEG causes an additional phase offset between the signals F _REF and F _V co, but this is generally not a problem. However, the frequency modulation effect of a varying VCO control voltage is substantially illuminated so that the frequency spurs resulting from such frequency modulation are substantially eliminated. Such frequency spurs occur at the frequency of the reference signal F _REF and, by substantially eliminating these spurs, there does not need to be as much attenuation at this frequency in a loop filter of a phase locked loop incorporating the phase detector. The loop filter bandwidth may therefore be wider and this reduces the close-in VCO phase noise.

Figure 7 illustrates one possible example of the control circuit 15 and the output stage 16. The UP and DN signals are supplied to integrators 20 and 21 , respectively, whose outputs supply voltages V_UP and V_DN to sample-and-hold (S/H) circuits 22 and 23, respectively. The integrators 20 and 21 and the S/H circuits 22 and 23 form the control circuit 15.

The outputs of the S/H circuits 22 and 23 supply voltages Vlag and Vlead to non- inverting and inverting transconductance amplifiers 24 and 25, respectively, which supply the currents lpos and IN _E G, respectively. The amplifiers 24 and 25 form the output circuit 16.

A timing generator (not shown) supplies reset and sample signals to the integrators and S/H circuits with the timings shown in the waveform diagrams of Figures 8 and 9. In particular, Figure 8 illustrates the waveform associated with the integrator 20, the S/H circuit 22 and the amplifier 24 whereas Figure 9 illustrates the waveforms associated with the integrator 21 , the S/H circuit 23 and the amplifier 25.

As shown in Figure 8, each pulse UP is supplied to the previously reset integrator 20, which integrates the pulse to form the voltage V_UP. After the trailing edge of the pulse UP, a "sample" signal is supplied to the circuit 22 and causes it to sample and hold the output voltage of the integrator. After the trailing edge of the sample signal, a reset signal is supplied to the integrator 20 to reset it for the next cycle of operation. The sampled voltage remains at the output of the circuit 22 at least until the next sampling pulse and is supplied to the amplifier 24, which converts it to a corresponding current Ipos-

The integrator 21 , the S/H circuit 23 and the transconductance amplifier 25 operate in the same way to provide the output current I _NEG - The output currents are given by:

l _NEG =-GM(Vlead)

where Vlag = K.TIag, Vlead=K.TIead and GM is the absolute value of the transconductance of each of the amplifiers 24 and 25.

Although the transconductance amplifiers 24 and 25 are described as forming the output stage 16, it is also possible for the outputs of the amplifiers to be supplied to separate controllable current sources and sinks, which would then form the output stage.

Figure 10 illustrates another example of the control circuit 15 and output stage 16. The signals UP and DN comprising pulses of widths Tlag and Tlead are supplied to a differencing circuit 30 forming the different (Tlag-Tlead). The differencing circuit 30 also provides a signal indicating the relative polarity of (Tlag-Tlead). The difference is supplied to an integrator 22, whose output is supplied to an S/H circuit 22. The

integrator 20 thus integrates the difference signal and this is sampled by the circuit 22 and supplied as the voltage Vcomp to the amplifier 24. The transconductance amplifier 24 converts the integrated and sampled difference to a current of the appropriate magnitude, whose polarity is controlled by the polarity-indicating signal from the differencing circuit 30. The resulting current I _COMP is then sourced or sunk by the amplifier 24. The output current I _COMP is given by:

lco _MP =GM.K(Tlag-Tlead)

Figure 11 illustrates another example of the control circuit and output stage 15, 16, which differs from the example shown in Figure 7 in that the individual transconductance amplifiers 24 and 25 are replaced by a differential transconductance amplifier 31.

A further example (not shown) of the control circuit 15 and output stage 18 subtracts the pulse widths UP and DN digitally and supplies the resulting number to a digital- analog converter (DAC), which converts the number into a corresponding current of the appropriate polarity.

In the control circuit and output stages described hereinbefore, the output current of the phase detector is supplied continuously and as a continuous monotonic function of the pulse widths of the pulses supplied by the PFD 2. The output current is a direct current whose absolute value and polarity represent the phase and/or frequency difference between the signals F _REF and F _V co supplied to the inputs of the PFD 2. However, it is also possible to use this arrangement in parallel with a charge pump and an embodiment of this type is illustrated in Figure 12.

The phase detector of Figure 12 differs from that of Figure 5 in that the output pulses UP and DN control a charge pump 3 provided in addition to the output stage comprising the controllable current source 18 and the controllable current sink 19. The charge pump shown in Figure 12 is of the same type as that shown in Figure 1. The outputs of the output stage 18, 19 and the charge pump 3 are connected together to form the output of the phase detector supplying the control signal "VCO control".

The PFD 2 is arranged to supply the control signals to the switches 9 and 11 of the charge pump 3 only when the loop of which the phase detector is part is out of lock.

When lock is established, the charge pump is disabled by opening both of the switches 9 and 1 1. The control circuit 15 and output stage 18, 19 then provide the output of the phase detector for holding the PLL locked while substantially avoiding ripple on the VCO control signal so as to substantially avoid frequency spurs at the output of the VCO. This arrangement thus provides compensation for leakage current as described hereinbefore but also provides compensation for leakage currents or mismatches in the charge pump 3.

Figure 13 illustrates a typical application of the phase detector 1 in a phase locked loop, for example for supplying oscillator output signals at an output 32 of selectable but stable frequency F _O uτ- The circuit arrangement shown in Figure 13 constitutes a frequency synthesiser, which has many applications.

The output of the phase detector 1 is connected to a loop filter 33, whose output is connected to the voltage control input of a voltage controlled oscillator (VCO) 34. The output of the VCO 34 constitutes the output 32 of the frequency synthesiser and is also connected via an optional frequency divider 35, which is optionally programmable in respect of its divisor M. The output of the divider 35 when present, or the output of the VCO 34 when the divider 35 is not present, is supplied to one of the inputs of the phase detector 1.

The frequency synthesiser further comprises a reference oscillator 36, which supplies at its output a signal of fixed highly-stable frequency F _R . The reference oscillator 36 is typically a crystal-controlled oscillator. The output of the oscillator 36 is supplied to an optional divider 37, which is optionally programmable and which performs frequency division by a divisor N. The output of the divider 37 when present, or the output of the oscillator 36 when the divider 37 is not present, is supplied to the other input of the phase detector 1.

The output frequency of the signal supplied at the output 32 of the frequency synthesiser is given by the expression;

Fouτ=M.F _R /N

By selecting the divisors M and N appropriately, the output frequency F _O uτ can be selected from among a plurality of discrete frequencies and has a frequency stability which is related to that of the reference oscillator 36.