Title:
PHASE ERRONEOUS-SYNCHRONIZATION DETECTING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2004/054165
Kind Code:
A1
Abstract:
A phase comparator circuit, particularly, a phase erroneous-synchronization detecting circuit for detecting a phase erroneous-synchronization occurring when the duty of data deviates from a hundred percent in comparison of phase difference between the data and the clock. In the phase comparator for detecting a phase difference between the data and the clock, the phase erroneous-synchronization detecting circuit comprises a first phase detecting part for detecting phase differences between the rising of the data and the phase of the clock to output an averaged phase difference; a second phase detecting part for detecting phase differences between the falling of the data and the phase of the clock to output an averaged phase difference; and a phase erroneous-synchronization deciding part for deciding an phase erroneous-synchronization when the difference between the averaged phase differences from the first and second phase detecting parts is beyond a predetermined range.
Inventors:
YAMAZAKI DAISUKE (JP)
Application Number:
PCT/JP2002/012977
Publication Date:
June 24, 2004
Filing Date:
December 11, 2002
Export Citation:
Assignee:
FUJITSU LTD (JP)
YAMAZAKI DAISUKE (JP)
YAMAZAKI DAISUKE (JP)
International Classes:
H03D13/00; H03K5/26; H03L7/08; H03L7/081; H03L7/091; H03L7/095; H04L7/033; (IPC1-7): H04L7/033; H03L7/095; H03L7/08
Foreign References:
| JP2000183731A | 2000-06-30 | |||
| JPH11112335A | 1999-04-23 | |||
| JP2002314518A | 2002-10-25 | |||
| JP2002111458A | 2002-04-12 |
Attorney, Agent or Firm:
Ishida, Takashi (ISHIDA & ASSOCIATES Toranomon 37 Mori
Bldg., 5-1, Toranomon 3-chom, Minato-ku Tokyo, JP)
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