TITLE OF THE INVENTION

[0001 ] PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

CROSS-REFERENCE TO RELATED APPLICATIONS [0002] The present application claims priority to U.S. Provisional Application No. 62 / 1 07,409 entitled "A DUAL RESET FLIP-FLOP PHASE- FREQUENCY DETECTOR FOR PHASE LOCKED LOOPS", filed on January 24, 201 5 , the entire content of wh ich is incorporated herein by reference. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR

DEVELOPMENT

[0003] N/A

NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT

[0004] N/A REFERENCE TO A "SEQUENCE LISTING"

[0005] N/A

BACKGROUND OF THE INVENTION Field of the I nvention

[0006] The present invention generally relates to a phase locked loop. More specifically, it relates to a phase locked loop utilizing a phase-frequency detector, loop filter and a voltage controlled oscillator. [0007] The present invention fu rther relates to a phase-frequency detector. More specifically, it fu rther relates to a phase-frequency detector utilizing no-added delay dual reset D flip-flops.

[0008] The present invention yet fu rther relates to voltage controlled oscillator. More specifically, it relates to a voltage controlled oscillator that utilizes two or more identical inverter-based staged ring oscillators with phase injection-locking by capacitive cou pling.

[0009] The present invention yet fu rther relates to a loop filter. More specifically, capacitance of the loop filter is adapted to transfer charge thereto and therefrom to effectively eliminate needs for cu rrent m irrors in a phase-locked loop.

Description of Related Art

[001 0] State-of-the-art phase locked loop (PLL) charge pu mps such as the single-ended examples shown in Figu res 3b and 3c, em ploy bu lky cu rrent m irrors (i.e. I N and IP) and relatively large transistor switches (i.e. 51 , 52 , 53 and 54) to flow su bstantial amou nts of cu rrent linearly to and from a loop filter to alter Vc. Although th is is effective, these charge pu m ps (CPs) of Figu res 3b and 3c have significant design concerns including: 1 ) relatively large active area, 2) wasted static power due to cu rrent mirrors and biasing always working even du ring PLL phase lock, 3) the large transistor switches take a relatively long time to open and close, hence there is an u nwanted control loop delay before the VCO frequency is altered, 4) extra matching circu itry for the CP U p/ Down output signal transitions is necessary for equal charge u p and charge down, 5) analog process extensions (i.e. cu rrent sou rces, large transistors, amplifiers) are sensitive to process variation, 6) Vc output errors easily occu r due to u ndesirable leakage cu rrent slipping through the large transistor switches, thu s affecting the VCO frequency while in phase lock, 7) limited headroom due to stacked transistors restricts u se at lower su pply voltages, and 8) scalability to deep su b-μηι technologies is severely restricted due to the large cu rrent mirror and switch transistors requ ired to flow considerable cu rrents and typically requ ires re-design when moving to a new process node.

[001 1 ] One of the most pertinent challenges in state-of-the-art phase frequency detector (PFD) designs is that the fast propagation delay, τ _ρ , of the digital flip-flops does not match the slower analog switching times, Ts, in the state-of-the-art CPs in a PLL. To cou nteract this "dead zone" issue, traditional approaches point to sim ply adding carefu lly timed su pplementary delay circu itry to the PFD reset path in order to allow for the Up/Down error signals to be extended, permitting the necessary extra time for the CP to react so that it may have the desired effect on the control voltage, Vc. The concern that resu lts with this widely-used method is that there is an u ndesi rable added delay, Td, introduced into the PLL control loop, which has the ability to contribute sign ificant noise, seen as j itter, in the PLL. The increased overall delay in the feedback loop is a sou rce of instability in the PLL. This u nsteadiness is a direct resu lt of the PFD output signals causing Vc dithering via the CP. The outcome is that the VCO's frequency, fvco, changes in either direction as the PLL

continually attem pts to acqu ire phase-frequency lock, but fails to do so, therefore u ndesirably increasing the phase noise of the VCO.

Ideally in a PLL, the PFD and CP wou ld have sim ilar switching times allowing for qu ick and symmetrical corrections of errors in the control loop in real time.

[001 2] Fu rthermore, state-of-the-art PFD designs, such as is shown in Figu re 1 1 b, typically are composed of a pair of DFFs with their D= 1 and Resets generated by a logic AND gate of both Q outputs, followed by carefu lly timed added delay ci rcu itry (e.g. buffers) to compensate for the slow switching time, z _{Sa b} , of cu rrent-based CPs, shown in Figu re 1 2b. This allows the critical Reset-to-Q propagation delay, τ _ρ , of the DFFs to be slowed down by r _d to match the CP switching time. While there are a variety of circu its and latches that cou ld be used in a PFD, the use of edge-triggered DFFs extends the phase detection range to span more than 1 period. Th is is essential for frequency lock over widely different frequencies. The main challenge in a state-of-the-art PFD design is in adding the correct amou nt of delay compensation to accommodate a traditional CP resu lting in minimal dead zone.

[001 3] To construct a flip-flop for a PFD, a variety of logic gates may be used. They are essentially a combination of (one, the other, or both) tri-state inverters or transmission-gate selector gates. The Master Latch selects either the D input or its inverted output and the Slave Latch selects either the Master Latch output or its inverted output, where each are selected with opposite phases of the clock. An example of a typical state-of-the-art D-flip flops (DFF) used in PFD designs is shown in Figu re 1 3. This particu lar DFF has a positive-edge triggered true and complement clock input, Clk, and a single asynchronou s reset, R. The output of the DFF is Q and its complement is Q.

[001 4] The propagation delay of this type of DFF is based on the most critical path, in this case Reset-to-Q as opposed to Clk-lo-Q , u nlike normal DFF design priorities which are optim ized for minimal clock delays. This reset delay, for the aforementioned reasons, is generally slowed down to work with a typical CP in the PLL. Beyond the negligible leakage cu rrent, the power of a DFF, and su bsequently a PFD of this type, is wholly dynamic due to the switch ing cu rrent incu rred in each DFF clock cycle. The PFD DFFs' contribution to power in a PLL is by and large the lowest overall. Fu rthermore, the area of this digital circu it is regu larly the smallest of all the blocks in the PLL.

[001 5]

BRIEF SUMMARY OF THE INVENTION

[001 6] The present invention generally relates to a phase locked loop. More specifically, it relates to a phase locked loop utilizing a phase-frequency detector, loop filter and a voltage controlled oscillator. [001 7] The present invention further relates to a phase-frequency detector. More specifically, it further relates to a phase-frequency detector utilizing no-added delay dual reset D flip-flops.

[001 8] The present invention yet further relates to voltage controlled oscillator. More specifically, it relates to a voltage controlled oscillator that utilizes two or more identical inverter-based staged ring oscillators with phase injection-locking by capacitive cou pling.

[001 9] The present invention yet further relates to a loop filter. More specifically, capacitance of the loop filter is adapted to transfer charge thereto and therefrom to effectively eliminate needs for current mirrors in a phase-locked loop.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0020] Figure 1 shows a block diagram of a prior art charge pump phase locked loop;

[0021 ] Figure 2a shows a block diagram of a charge pump of the present invention;

[0022] Figure 2b shows a switch view diagram of a prior art charge pump; [0023] Figure 3a shows a transistor-level schematic of a charge pump of the present invention; [0024] Figures 3b and 3c show transistor-level schematics of prior art charge pumps;

[0025] Figure 4 shows a switch view and general transient wave forms of the phase locked loop charge pump of the present invention in idle mode;

[0026] Figure 5 shows a switch view and general transient wave forms of the phase locked loop charge pump of the present invention in pump up mode;

[0027] Figure 6 shows a switch view and general transient wave forms of the phase locked loop charge pump of the present invention in pump down mode;

[0028] Figure 7 shows a simulated plot of output step and phase lock behavior of the phase locked loop charge pump of the present invention; [0029] Figure 8 shows simulated systematic percentage error between the phase locked loop charge pump of the present invention and the prior art charge pumps shown in Figures 3b and 3c;

[0030] Figure 9 shows a layout and die micrograph of the phase locked loop charge pump of the present invention with PLL, loop filter capacitor and phase frequency detector of the present invention; [0031 ] Figu re 1 0 shows a snapshot of the phase noise and spectru m characteristics of the physically tested phase locked loop with the charge pu mp of the present invention;

[0032] Figu re 1 l a shows a D-flip flop based phase frequency detector of the present invention;

[0033] Figu re 1 1 b shows a prior art D-flip flop based phase frequency detector;

[0034] Figu re 1 2a shows a switch view diagram of the charge- based charge pu mp of the present invention; [0035] Figu re 1 2b shows a switch view diagram of a prior art charge based charge pu mp;

[0036] Figu re 1 3 shows a schematic view of an example of D-flip flops used in a prior art phase frequency detector;

[0037] Figu re 1 4 shows schematic view of a phase frequency detector of the present invention,

[0038] Figu re 1 5 shows a block diagram of a phase frequency detector of the present invention;

[0039] Figu re 1 6 shows an example of the phase frequency detector from in pu mp u p mode to idle mode in the PLL of the present invention; [0040] Figure 1 7 shows an example of the phase frequency detector from in pump down mode to idle mode in the PLL of the present invention;

[0041 ] Figure 1 8 shows a layout and die micrograph of the phase frequency detector and D-flip flops of the present invention;

[0042] Figure 1 9 shows a block diagram of a capacitively phase- cou pled ring voltage controlled oscillator of the present invention;

[0043] Figure 20 shows a block diagram of a 2 x 3 ring voltage controlled oscillator of the present invention; [0044] Figure 21 shows a block diagram of a single stage unit of the voltage controlled oscillator rx s expansion and differential "gyrator" of the present invention;

[0045] Figure 22 shows an example of 4 x 3 quadratu re ring voltage controlled oscillator in accordance with the present invention; [0046] Figure 23 shows a graph of Vc versus the voltage controlled oscillator output frequency for the C _e q tuning bank;

[0047] Figure 24 shows a block diagram of a phase locked loop of the present invention;

[0048] Figure 25a shows a die micrograph of the 4 x 3 voltage controlled oscillator in a PLL of the present invention; [0049] Figure 25b shows a layout plan example of symmetric 4 x 3 voltage controlled oscillator;

[0050] Figure 26 shows a graph of measured phase noise and output spectrum at 28.0 GHz; [0051] Figure 27 shows K-Map for logic l's and 0's;

[0052] Figure 28 shows examples of resulting gate constructions;

[0053] Figure 29a shows a prior art schematic of logic

construction;

[0054] Figure 29b shows a schematic of logic constructions of the present invention;

[0055] Figure 30a shows a string diagram of the logic schematic of prior art;

[0056] Figure 30b shows a string diagram of the logic schematic of the present invention [0057] Figure 31 a shows a stick diagram of the logic schematic of prior art;

[0058] Figure 31 b shows a stick diagram of the logic schematic of the present invention;

[0059] Figure 32a shows a layout from the stick diagram of prior art; [0060] Figu re 32b shows a layout from the stick diagram of the present invention;

[0061 ] Figu re 33 shows a schematic of a constant amplitude com plementary injection field effect transistor (CiFET) based voltage controlled oscillator of the present invention;

[0062] Figu re 34 shows a schematic of an injection field effect transistor of the present invention;

[0063] Figu re 35 shows a schematic of a CiFET; and

[0064] Figu re 36 shows a schematic of a CiFET amplifier pair.

DETAILED DESCRIPTION OF THE INVENTION

[0065] The phase-locked loop (PLL) is a u biqu itous control system used for precise frequency and phase generation , clock synch ron ization, and signal recovery. PLLs are perhaps the most im portant and u biqu itou s circu it block in modern electronics as they can be fou nd in every computer processer, transceiver, and clocked system , including laboratory test equ ipment. Therefore, PLL cost, area, power, and performance— and u ltimately scalability— is continuou sly of main concern for integrated circu it (IC) designers and manufactu rers which will em ploy this circu it-based system in their next-generation devices.

[0066] For mu lti-GHz wireline and wireless IC applications there are two primary PLL design approaches: 1 ) analog and 2) digital.

Generally, analog PLLs, such as the charge pu mp PLL block diagram shown in Fig. 1 , have a larger IC footprint and are typically more power hungry as compared to their digital phase locked-loop counterparts. On the other hand, digital PLLs generally possess more complicated circuitry, are limited to frequencies significantly below 1 0GHz, and have a tendency to suffer from digital noise due to quantizing issues. Since PLLs in general are extremely usefu l in analog/radio frequency (RF), mixed-signal, and digital System on a Chip (SoC) applications for both wireless and wireline systems, much effort from both the industry and research sectors has been focused on finding new scalable low noise, high performance alternatives in Complementary metal-oxide- semiconductor (CMOS).

[0067] In recent years, analog PLLs have incrementally adopted digital circuit elements to their constituent blocks (e.g. dividers, phase detectors, and oscillators) which perform analog functions with less area and power. To date, a digital-like, portable circuit component for every block in the analog PLL has been created except for the charge pump circuitry; this is due to the analog process extensions (e.g.

cu rrent mirrors and switches which require large transistors and voltage swings) that have been necessary to design this block using state-of-the-art methods. This has been an important bottleneck in making analog PLLs scalable to and between ultra-deep su b-μηι CMOS technologies. The first section of this work is dedicated to applying the charge-mode approach, specifically charge-transfer, to create a simple, yet novel architectu re for the CP which is u ltra-low power and scalable to the newest CMOS process nodes. [0068] Charge Pump based PLL with Charge Transfer

[0069] Referring to Figure 1 , the main pu rpose of a charge pump based PLL 1 is to control the frequency 1 6 of the voltage controlled oscillator 1 4. The inputs to the charge pump (CP) 1 2 are Up/Down error signals generated by a digital phase-frequency detector 1 1 . The output of the CP 1 2 is a control voltage, Vc, stored as charge on the effective capacitance of the loop filter (LF) 1 3, CL. Raising or lowering VC will result in an increase or decrease of the VCO frequency of operation, fvco 1 6. [0070] A typical closed PLL control loop operation wou ld begin with the VCO as shown in Figure 1 , producing frequency, fvco, at phase, φν∞- This output frequency is generally divided down by an integer or fractional value to a lower "feedback" frequency, f FB, by the divider block 1 5. The stable reference frequency, fREF, and its phase, c()REF, is then compared to the feedback frequency, f FB, and phase, C()FB in a phase frequency detector (PFD) 1 1 . If there is a difference in frequency or phase between the reference and feedback signals, the PFD 1 1 produces an Up or Down error signal for the duration of the frequency or phase difference. The PFD 1 1 detects phase difference in the reference and feedback signals in less than 1 degree.

[0071 ] In this work, an Up=logic 1 error signal is produced by the PFD 1 1 when the phase of feedback phase C()FB lags behind reference phase C()REF and a Down = logic 0 error signal is given when feedback phase C()FB leads in front of C()REF. When the PLL 1 is in phase lock (i.e. no error signal is produced (i.e.

Up= Down = logic 0) and the loop 1 is essentially open with the ideal CP design 3 shown in Fig. 2 b. The values of the PFD's U p/ Down error signals determine the action of the CP 3: Up= logic 1 causes a transistor switch 31 of the CP 3 to close allowing charge to be placed on the LF's CL, effectively raising Vc and consequently fvco;

Down = logic 1 causes the opposite behavior in the CP 3 to occu r by closing the other switch 32 and taking charge away from Ci_, thus lowering Vc and fvco- [0072] State-of-the-art PLL charge pu m ps (CP) 50 and 60 shown in Figu re 3b and 3c employs bu lky cu rrent mirrors (i.e. IN and IP as shown therein) and relatively large transistor switches 51 , 52 , 53 and 54, and 61 , 62 , 63 and 64 to flow su bstantial amou nts of cu rrent linearly to and from a Loop Filter (LF) to alter Vc. Although this is effective, these CPs 50 and 60 have significant design concerns including: 1 ) relatively large active area, 2) wasted static power due to cu rrent m irrors and biasing always working even du ring PLL phase lock, 3) the large transistor switches take a relatively long time to open and close, hence there is an u nwanted control loop delay before the Vco frequency is altered, 4) extra matching circu itry for the CP

Up/ Down output signal transitions is necessary for equal charge u p and charge down, 5) analog process extensions (i.e. cu rrent sou rces, large transistors, amplifiers) are sensitive to process variation, 6) Vc output errors easily occu r due to u ndesirable leakage cu rrent slipping through the large transistor switches, thus affecting the VCO frequency while in phase lock, 7) limited headroom due to stacked transistors restricts use at lower supply voltages, and 8) scalability to deep sub-μηι technologies is severely restricted due to the large current mirror and switch transistors required to flow considerable currents and typically requires re-design when moving to a new process node.

[0073] The proposed PLL charge pump shown in the switch view in Figure 2a and transistor level schematic in Figure 3a is a new single-ended, capacitive charge transfer-based design that uses four (4) minimum-sized transistor switches 21, 22, 23 and 24, and 41 , 42, 43 and 44, and a relatively small metal interconnect capacitor 25 and 45 that is sized to be dominant over parasitics. There are no current mirrors or other analog process extensions as in the state-of-the-art designs. This CP circuit 2 or 40 uses the same inputs (i.e. Up/Down logic error signals from the PFD) and has a similar overall general result as the state-of-the-art CPs 3, 50 and 60 in that the VCO frequency is successfully controlled, yet there are a few marked differences including the architecture, how the charge is transferred and held, the output voltage behavior, and total power consumption. Additionally, the switched capacitor 25 or 45 acts in itself as a second order filter for the PLL control loop.

[0074] PLL Charge Pump Operation

[0075] As with any PLL charge pump, there are 3 explicit switching modes of operation, namely: 1 ) Idle, 2) Pump Up, and 3) Pump Down. The next 3 segments describe each of these modes in detail for the charge pump of the present invention in the PLL control loop while highlighting the unique output voltage behavior and the amount of energy transferred for each mode, which is necessary to find the total dynamic power consumed while the CP charges and discharges in the various modes.

[0076] 1). Idle Mode

[0077] Figure 4 illustrates the switch view of the Charge Pump (CP) 72 in Idle mode with a general transient waveform. The Idle mode is always characterized by the Up and Down error signals being low

(i.e. Up=Down = logic 0). There are two different times in which the Idle mode occurs in the PLL control loop, each with a specific purpose: 1) during phase lock to hold the Vc value constant (i.e. C()FB equals and 2) for the recharging of CP in between Pump Up and Pump Down modes (i.e., C()FB does not equal

[0078] At the start of the Idle mode, switches 721 and 722 are closed while 723 and 724 are open; meanwhile this action causes CP 72, to charge to VDD. After CP 72 charges to the supply voltage, VDD, the capacitor 725 holds its charge, QP, in an open loop fashion until the CP 72 is instructed by the PFD 71 to change modes to either Pump Up or Pump Down. Vc, will not change during Idle mode and, therefore, retains the voltage value, Vco, it held at the moment prior to starting Idle mode, namely: [0079] V _C = V _C0 [EQ. 1 ]

[0080] Due to the switched capacitor structu re of the CP circu it, there are relatively little to no errors in the Vc value, u ltimately reducing u nwanted PLL phase errors compared to the state-of-the-art. There is no static power being dissipated due to biasing in the proposed CP (no cu rrent-mode cu rrent m irrors) and we must look at the switching dynam ic power to find the total power consu med wh ile the CP sits qu ietly in the Idle mode. In order to do this, the energy at the start and end of the Idle mode needs to be analyzed. The energy utilized by the proposed CP 72 at the start of the Idle mode when Cp charges to VDD is:

[0081 ] E _CPwLEo = C _P V _DD ² = Q _P V _DD [EQ. 2]

[0082] It must be noted that the CP 72 charges only once at the very beginning of the Idle mode; this cou ld be a fu ll recharging or a partial recharging in EQ. 2 depending on the amou nt of charge requ ired to bring the voltage across Cp 725 , VP, to VDD. The energy consu med by the proposed CP 72 du ring the Idle mode after charging to VDD is:

[0083] E _CPlDLEi ^ 0 [EQ. 3] , [0084] due to no changes in the switches 721 and 722 of the CP 72 with the reasonable assu m ption that the leakage cu rrent flowing through the stacked switches 721 and 722 is negligible. Therefore, the total power dissipation of the proposed CP 72 for a complete Idle mode cycle may be fou nd via the dynamic power equation:

[0085] P _CPlDLE = af _REF AE _CPwLE = af _REF (E _CPwLEo - E _CP}DLE1 ) « [0086] where a is the activity factor (0≤ a≤ 1 ) for the proposed CP 72 working in 1 or more specific modes at the PLL reference frequency, fREF.

[0087] 2). Pu m p Up Mode

[0088] Figu re 5 depicts the Pu mp Up mode for the proposed CP 72 with a general transient waveform exam ple. In th is case, the Pu mp Up mode is activated by a lagging phase difference between C()FB and 4>REF; this causes the PFD 71 to produce a logic 1 U p error signal for the du ration of the phase difference between f FB and fREF. The CP 72 responds by transition ing out of Idle mode with an opening of the switch 72 1 and closing of switch 723 which allows the charge, QP, stored on CP 725 to transfer to Ci_ 725 , thus raising the voltage on Vc. The resu lt for one Pu mp Up cycle is an increasing of φν∞ and C()FB in order to match C()REF. At the end of every Pu mp Up cycle the CP 72 retu rns to Idle mode to fu lly recharge Cp 725. As the PLL 70

approaches phase lock, partial Pu m p U p cycles take place

incrementally raising Vc which allows for accu racy in obtain ing the correct frequency on the VCO 74. [0089] The exponential capacitive behavior of the CP output, Vc, for a single Pump Up charge sharing event may be modeled by the following first order equation:

[0090] V _c = V _co + ^- V _DD (l - e ^' ^u ^p ) [EQ. 5] [0091 ] where τ _υΡ is equal to the RC time constant for the switch 722-capacitor 725-switch 723 path which the charge must flow through to arrive at CL in the Pump Up mode. The time, t, is the exact time in which Up is high, whether a partial or full cycle. As the PLL 70 gets close to acquiring phase lock, a partial Pump Up cycle occurs where the charge transfer event will get cut off midway (t « τ _υΡ ) and the exponential portion of Eq. 5 may be linearly approximated to (1 - t/xup) as is shown in Eq. 6 when the PLL is near phase lock:

[0092] V _C * V _{C0 + 7} ^r V _DD (l - (1 - t/ _T ) = V _{C0 + 7} ^- V _DD (t/ _Tup )

[EQ. 6] [0093] This linear EQ. 6 results is precise phase lock at a high resolution for the proposed charge pump. The output step size is simply based on the ratio of capacitance Cp 725 to the LF's 73 CL 731 . For example, to increase the output step size, increasing Cp 725 would suffice. The change in energy of the charge pump system during a Pump Up mode charge sharing event is:

[0094] AE _CPup = E _CPupo - E _CPupi = - 0 _P V _DD + \ Q _L V _C0 1 (QP+QL) ²

2 C _P +C _L

[EQ. 7] [0095] where QP and Qi_ are the initial charges held by the capacitor, Cp 725 and capacitor, Ci_ 731 at the start of the Pump Up mode. Using EQ. 7, we can now calculate the power dissipated for the Pump Up cycle at the PLL 70 reference frequency fREF by using the following dynamic power equation:

[0096] P _CPup = af _REF AE _CPup = af _REF g Q _P V _DD + Q _L V _C0 -

[EQ. 8]

[0097] 3). Pump Down Mode

[0098] Figure 6 illustrates the Pump Down mode for the proposed CP 72 with a simple transient waveform example. The Pump Down mode occurs when the phase error swings in the opposite direction and cJ)FB leads C()REF, causing the PFD 72 to produce a logic 1 Down error signal for the du ration of the difference between f FB and fREF. Similar to the Pump Up mode, the CP 72 responds by moving out of the Idle mode, but instead opens the switch 722 and closes the switch 724 which allows the pulling of the stored charge, QP, away from the capacitor 731 of the loop filter 73 , thus lowering the voltage on Vc. This action decreases fvco and, consequently, f FB, in the closed PLL control loop. At the end of every Pump Down cycle, the CP 72 recharges CP 72 in the Idle mode.

[0099] Analogous to the Pump Up cycle, the Pu mp Down CP output can be modeled by the first order equation: [001 00] V _c = Vco - _C TTF i. ¹ - ^{e ~t/TDN} ) ^[EQ - ^9]

[001 01 ] where τ _ΟΝ is equal to the RC time constant for the switch 724-capacitor 725-switch 721 path that the charge mu st flow through to leave the capacitor 731 of the LF 73. The time, t, is the fu ll or partial cycle time that the Down error signal is high. As the PLL 70 draws near to phase lock, partial Pu mp Down cycles occu r, where the charge transfer event will get cut off midway (t « τ _ΟΝ ). In this case EQ. 9 may be linearly approximated to:

[001 02] Vc * Vco - z- V _DD (l - (1 - 7r _DJV )) = V _co ^~ ^ 7r _DJV )

[EQ. 1 0]

[001 03] The output Down step size of the CP 72 may be adjusted via the ratio of the capacitor C 725 to the capacitor, Ci_ 731 of the LF 73 and is equ ivalent to the Up step size due to CP 72 being utilized for both transitions, thu s eliminating the need for extra matching circu itry com pared to the state-of-the-art. The CP energy used du ring a Pu mp Down cycle is:

[001 04] AE _CPDN = E _CPDNO - E _CPdni = ^^- _Ρ ν _ΒΟ + - ₂ QLVCO

[EQ. 1 1 ]

[001 05] Finally, the power dissipated for the Pu mp Down mode is: [001 06] P _C p _DN = af _REF AE _C p _DN = af _REF Q _P V _DD + Q _L V _C0 )

[EQ. 1 2] [00107] Power Consumption of the PLL Charge Pump of the

Present Invention:

[00108] The total dynamic power of the proposed CP 72 may be found by adding EQs.4, 8, and 12 or via CP's stored energy over time: [00109] P _CPDYN = P _CPLDLE + P _CPUP + P _CPdown = (af _REF =

{af _REF ^≡) [EQ. 13]

[00110] Therefore, the total power of the proposed CP 72 with negligible leakage of the stacked transistor switches is simply:

[00111] P _CP = P _CPDYN + P _CPLEAK = (af _REF - ^C ^) + Q _leak V _DD ) = af _REF E _CP

[EQ. 14]

[00112] Experimental Results for the Proposed PLL Charge Pump

[00113] This section presents simulation and experimental results for the proposed charge-mode PLL CP 72. The proposed CP 72 was simulated in a 1 -10GHz ring VCO-based analog PLL with a varying supply voltage of 0.5-1.2V. The technology used was a TSMC digital 40nm CMOS process. The six transistors of the CP had a width of WN = 120nm or WP=240nm and a length of L=40nm. The CP capacitor, Cp 725, was 1 OOfF, while the LF capacitance, Ci_ 731 , was 1 pF, resulting in a 1:10 output step size ratio. The PFD 71 utilized was a dual-reset DFF from the reference, "A dual reset D flip-flop phase- frequency detector for phase locked loops," by S. Schober et al., IWS 2015, Proceedings of the XXI Iberchip Workshop, February 2015, with no added delay due to the comparable switching time between the minimum-sized switches of the PFD DFFs and the CP.

[001 1 4] Figure 7 is a graph, showing the simulated output for the Up and Down modes; the inset illustrates the high resolution, linear behavior of the CP output as phase lock is approached and acqu ired.

[001 1 5] Figure 8 depicts the % error mismatch simulation comparison results for the proposed CP and the state-of-the-art CPs in Figu re 3b to 3c utilizing the same PLL; the proposed CP output has less than a 0.05% error for 0.05V≤ Vc≤ 1 .1 5V. Simulation results shown were taken at fouT= 5GHz and f REF ⁼ 1 00MHz with a 1 .2V su pply and a divider of N = 50. The average power of the CP was 253pW in simulation, while (b) and (c) had a static power of 1 .1 2 mW and

1 .53mW, respectively, resulting in a 1 06 improvement in power consumption over the state-of-the-art. [001 1 6] The 1 -1 0GHz PLL was fabricated with the proposed CP in all-digital 40nm TSMC CMOS and physically tested. Figure 9 displays the layout and die micrograph of the proposed CP, with the PLL LF capacitor and PFD. The measu red performance results of the proposed CP with a comparison to state-of-the-art CPs is shown in Table 1 . [001 1 7]

Present Ref. 1 Ref. 2 Ref. 3 Ref. 4 Ref. 5 invention

Supply [V] 0.5- 1 .2 1 .2 1 .2 3.3 1 .8 1 .5 fvco[GHz] 1 -1 0 1 - 1 0 1 - 1 0 0.35-0.61 — 4.8-5

FREF[MHZ] 50-400 50-400 50-400 29 50-500 1 1 CP Power [W] 250p 1 .1 2m 1 .53m 1 .5m 940μ 2.2 m

CP Vc range [V] 0.0 - 1 .2 0.1 - 1 .1 0.1 - 1 .1 0.07-1 .05 0.1 - 0.9 0.1 - 1 .4

CP area [mm ^2] 0.0004 0.0045 0.0065 0.01 5 0.01 5 0.1 6

RMS jitter [ps] 0.80±0.05 2.3 1 .5 7.1 — —

Ref. spurs [dBc] < -70 < -60 < -65 — — < -70

Phase error [ ° ] 0.1 - 0.3 2.3 0.9 — 1 - 5 —

Technology [m] 40n 40n 40n 0.35μ 0.1 8μ 0.24μ

Table 1 where:

Ref. 1 is based on simulated results from state-of-art CP example shown in Figure 3b; Ref. 2 is estimated value from state-of-art CP example shown in Figure 3c;

Ref. 3: X. Shi, K. Imfeld, S. Tanner, M. Ansorge, and P-A. Farine. "A low-jitter and low-power CMOS PLL for clock multiplication."

ESSCIRC'06, Proceedings of the 32 nd European Solid-State Circuits Conference, pp. 1 74-1 77, 2006;

Ref. 4: C. Charles and D. Allstot. "A buffered charge pump with zero charge sharing," ISCAS'08, IEEE International Symposium on Circuits and Systems, pp. 2633-2636, 2008; and

Ref: 5 : H. Rategh, H. Samavati, and T. Lee. "A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver," IEEE Journal of Solid-State Circu its, vol. 35, pp. 780-787, May 2000.

[001 1 8] Figure 1 0 illustrates a snapshot of the phase noise and spectrum characteristics of the physically tested PLL with the proposed CP. The unique, low power switched capacitor design of the proposed CP is responsible for the desirable minimal charge injection into the VCO control line. The power of the spu rious sidebands of the PLL thereby is greatly reduced allowing for the reference spu rs to be less than -70dBc.

[001 1 9] The CP design of the present invention overcomes the aforementioned state-of-the-art CP design concerns efficiently by eliminating cu rrent mirrors and adopting a switched capacitor approach to transferring charge to and from the LF's capacitance. The resu lt is a dramatic reduction of power and active area. Fu rthermore, the proposed CP in accordance with the present invention is scalable to and between smaller process nodes and able to be used at very low voltages (< 1 V). The proposed CP of the present invention possesses no analog process extensions that are parametrically sensitive to process variation, allowing for a matched Up and Down output step when acquiring phase lock. The use of the proposed CP allows for a low jitter, low phase-noise analog PLL with reduced reference spurs.

[001 20] PLL PFD Designed with Charge/Discharge Path

Optimization: [001 21 ] Many types of PLLs, both digital and analog, employ a phase detection block for determining differences (i.e. errors) between the divided-down feedback oscillator frequency, f FB, and a stable reference frequency, fREF. An example of a PLL that utilizes a phase- frequency detector circuit 1 1 is the analog charge pump PLL 1 previously shown in Figu re 1 . Although over the past 30 years, there have been many varieties of phase and/or frequency detectors for PLLs in ICs, such as analog mu ltipliers or digital combinational circu its like an XOR gate, which cou ld be applied to the block 1 1 in Figu re 1 , the state-of-the-art PFD generally is a sequential flip-flop based circu it operating in 1 of 3 states (i.e. Up, Down, or Idle modes) while in a PLL. The u biqu itous use of this type of detector in a PLL is due to the advantageous combination of low power, stability, speed, noise, and area tradeoffs possessed by a flip-flop based PFD as compared to its cou nterparts.

[001 22] State-of-the-Art PLL PFDs

[001 23] One of the most pertinent challenges in state-of-the-art PFD designs is that the fast propagation delay, τ _ρ , of the digital flip- flops does not match the slower analog switch ing times, τ ₅ , in the state-of-the-art CPs in a PLL shown in the reference, Razavi, Behzad, "Challenges in the design of high-speed clock and data recovery circu its," IEEE Commu nications Magazine vol. 40, pp. 94- 1 01 , Aug. 2002. To cou nteract this "dead zone" issue, traditional approaches point to simply adding carefu lly timed su pplementary delay circu itry to the PFD reset path in order to allow for the U p/ Down error signals to be extended, perm itting the necessary extra time for the CP to react so that it may have the desired effect on the control voltage, Vc. The concern that resu lts with this widely-used method is that there is an u ndesi rable added delay, τ _α , introduced into the PLL control loop, which has the ability to contribute sign ificant noise, seen as j itter, in the PLL. The increased overall delay in the feedback loop is a sou rce of instability in the PLL. This u nsteadiness is a direct resu lt of the PFD output signals causing Vc dithering via the CP. The outcome is that the VCO's frequency, fvco, changes in either direction as the PLL

continually attem pts to acqu ire phase-frequency lock, but fails to do so, therefore u ndesirably increasing the phase noise of the VCO.

Ideally in a PLL, the PFD and CP wou ld have sim ilar switching times allowing for qu ick and symmetrical corrections of errors in the control loop in real time.

[001 24] Recently, a promising new type of fast-switch ing, accu rate charge-transfer based PLL charge pu m p, which was covered in the previous section, has been introduced facilitating the need for an im proved PFD design that works seamlessly with this advanced block in the PLL. Specifically, this CP does not requ ire a PFD with the traditional delay com pensation to account for the inability of the relatively large CP analog transistor switches to open and close qu ickly. Rather, this digital-like CP requ ires a PFD with min imal dual Reset-to-Q switch ing times on the same logic speed scale; th is allows for high resolution of phase error correction in the PLL resu lti ng in extremely low levels of added noise (i.e. dither arou nd phase lock) as com pared to the state of the art designs. Therefore, this work aims to introduce a no-added delay dual reset D flip-flop (DFF) based PFD design that when u sed in conju nction with a charge-transfer based CP in a multi-GHz PLL, results in very low jitter characteristics and reduced reference spurs in the PLL's frequency spectrum.

[001 25] State-of-the-art PFD designs, such as is shown in Figure

1 1 b, typically are composed of a pair of DFFs with their D= l and Resets generated by a logic AND gate of both Q outputs, followed by carefully timed added delay circu itry (e.g. buffers) to compensate for the slow switching time, r _{Sa b} , of current-based CPs, shown in Figure

1 2b. This allows the critical Reset-to- Q propagation delay, , of the DFFs to be slowed down by τ _α to match the CP switching time. While there are a variety of circu its and latches that could be used in a PFD, the use of edge-triggered DFFs extends the phase detection range to span more than 1 period. This is essential for frequency lock over widely different frequencies.

[001 26] The main challenge in a state-of-the-art PFD design is in adding the correct amount of delay compensation to accommodate a traditional CP resulting in minimal dead zone, which is directly responsible for phase noise and spurious tones. For instance, if there was no buffering of the PFD reset path to add the appropriate delay, nonlinearities between the PFD and CP would readily be introduced, thus resulting in an incorrect amount of charge delivered to the loop filter. This is due to the differences in timing of the PFD propagation delay and the CP switches. Invariably these charge differences cause a distortion in the CP current spectrum and adversely raise the in-band noise floor of the PLL. In a PLL that uses these components, it is then absolutely critical to match the timing of the PFD Up/ Down error outputs to the CP switches such that:

[001 27] τ _Ρυρ + τ _α = T _Pdn + τ _α = T _Sa = T _Sb [EQ. 1 5]

[001 28] A consequence of adding this delay is the u nwanted generation of a brief Up/Down 1 / 1 state for the length of th is dead zone in every cycle, even du ring phase lock, which u nfortu nately causes fluctuations in the CP producing PLL j itter.

[001 29] Additionally, at the circu it level, an ideal PFD will exh ibit the following list of desirable attributes when placed in a PLL: 1 ) Reset-to-Q propagation delays are equal to the CP switch time, 2) balanced Up/ Down error signal outputs for given phase error, 3) no digital glitch errors while in Idle mode, 4) wide frequency operating range, 5) compact area, 6) low power operation, 7) ability to be used with su pply voltages < 1 V, and 8) scalability to and between process nodes for ease of futu re reuse thus reducing design time. At the heart of PFD design are the flip-flop circu its utilized to meet these demands head on.

[001 30] State-of-the-Art PLL D Flip-Flops for PFDs

[001 31 ] An example of a typical state-of-the-art DFF used i n PFD designs is shown in Figu re 1 3. To construct a flip-flop, a variety of logic gates may be used. They are essentially a com bination of (one, the other, or both) tri-state inverters or transmission-gate selector gates. The Master Latch 1 31 selects either the D input or its i nverted output and the Slave Latch 132 selects either the Master Latch 131 output or its inverted output, where each are selected with opposite phases of the clock. This particular DFF has a positive-edge triggered true and complement clock input, Clk, and a single asynchronous reset, R. The output of the DFF is Q and its complement is Q.

[00132] The propagation delay of this type of DFF is based on the most critical path, in this case Reset-to- Q as opposed to Clk -to- Q, unlike normal DFF design priorities which are optimized for minimal clock delays. This reset delay, for the aforementioned reasons, is generally slowed down to work with a typical CP in the PLL. Beyond the negligible leakage current, the power of a DFF, and subsequently a PFD of this type, is wholly dynamic due to the switching current incurred in each DFF clock cycle. The PFD DFFs' contribution to power in a PLL is by and large the lowest overall. Furthermore, the area of this digital circuit is regularly the smallest of all the blocks in the PLL. With the new compact charge-based CPs, shown in Figure 12a, which switch fast and consume power in the pW range, there is much to be gained by optimizing a DFF for speed, power, and area in a PLL that employs a charge-based CP. [00133] Optimized Dual Reset DFF for Proposed PFD

[00134] The proposed PFD design is shown Figure 11 a and is made out of 2 unique dual reset DFFs to match the faster switching speed, τ _5ι _ ₄ , of a charge-based CP design shown in Figure 12a. In this

PFD, the output of the DFFs, Q and Q, directly supply the error signals, Up and Down, with their complements for use in the CP. There is no added delay in the Reset-to-Q path as typically seen in the state-of- the-art designs.

[001 35] The proposed DFF of Figu re 1 4 is an optimization of the DFF shown in Figu re 1 3 where D= l and an additional reset in put has been added to internalize the typical PFD AND gate into the Slave Latch 1 42. This DFF also consists of three sections: 1 ) Master Latch 1 41 , 2) Slave Latch 1 42 , and 3) Output Buffers 1 43. Both latches 1 41 and 1 42 are made entirely out of asymmetric complex gates for maximu m performance. Th is charge/discharge path optimization approach is known as Complementary-Com plex Logic (C2L). Here the p-channel devices are not a direct De-Morgan complement of the n- chan nel structu re, but instead a logic fu nction complement observed by using zeros for the pu ll-down and ones for the pu ll-u p realization asvisualized on a Karnaugh-Map as described in 1 ). V. Kantabutra et al., "A state assignment approach to asynchronous CMOS circu it design ," IEEE Transactions on Computers, vol. 43, pp. 460-469, Apr. 1 994; and 2). C. Piguet, "Memory element of the master-slave flip-flop type, constructed by CMOS technology," U.S. Patent No. 5 ,748, 522. May 1 998. This approach may u se some "can't-happen," which are extremes of "don't-care," conditions differently between the n-channel pu ll-down trees and the p-channel pu ll-u p trees yielding dissimilar looking tree structu res. A "can't-happen" condition does not need to have the same logic state for both the pu ll-down and pu ll-u p structu res. Utilizing the Complementary Complex Logic approach as shown in US Patent No.6,198,324 and 6,297,688 enables a more compact, fast, and lower power DFF design through reduction of interconnect parasitics and transistors in the critical path as realized by combining or sharing the active nodes instead of the normal metal interconnect in the circuit's physical layout.

[00136] Note that the proposed DFF in Figure 14 uses a single phase clock, as opposed to Figure 13, so that the delay difference between the internal Clk and Clk is not a consideration in the flip-flop response. The Slave Latch complex-gate structure in Figure 14 combines a fast clock path with the optimized Reset-to-Q signal paths at node C for minimal delay. When Clk goes HIGH, node C is directly pulled LOW and when the last of both resets go LOW, node C is directly pulled HIGH. It only remains to get the Q signal and its complement out with nominal delay to form the UP or DOWN CP commands.

Observe that Q needs to be buffered before being tied back to the flip- flop's R ₂ through an inversion of Q, otherwise the complex gate's output node C would be directly controlling its own gate inputs. The delay to perform this self-reset defines the minimum Up/Down phase detector output pulse width as a couple of fast inverter propagations. This smallest possible PFD output pulse width is on the same scale as the charge-based CP switching time, allowing for an excellent match in operational speeds between these two blocks, which is unlike traditional PFD-CP designs. [00137] The 1 st inverter delay starts to turn the switch ON and the 2nd pulls it back OFF in the Output Buffers 143. Note that the reset R ₂ is directly tied to the final buffered Q output for the case of the charge-based CP. If a state-of-the-art current-based CP was utilized, additional delay would normally be added before both resets. This direct connection for the charge-based CP is reflected in both Figures 11 a and 14.

[00138] Proposed PFD Operation in a PLL

[00139] The implementation of the proposed PFD 71 ' in

combination with the charge-based CP 72' in a PLL 70' is then relatively straightforward as shown in Figure 15: cross-couple the resets, eliminate the AND gate and traditional delay circuitry found in state-of-the-art PFDs, and connect directly to the charge-based CP

72'. With the charge-based CP 72', the switches 721 ', 722', 723' and 724' are not the typical large slow opening/closing analog transistors required to flow large amounts of current from the current mirror, but rather minimum sized and relatively quick to open and close to transfer discrete amounts of charge from/to the LF 73' capacitance, CL (e.g. T _SI _ ₄ « _Sab ). For a PLL that uses a charge-based CP, there is no added delay requirements (e.g. τ _ά = 0 ) for the PFD as the propagation delay of the switches of the CP are on the same order as the DFFs in the PFD. The timing issue therefore gets mitigated to the actual sizing of the transistors within the DFFs. Notably, the Reset-to-Q timing constraints now simply become: [001 40] τ _Ρην = r _Pdown = _¾ = _T¾ = _¾ = _¾ [EQ. 1 6]

[001 41 ] Figu res 1 6 and 1 7 display the Up to Idle and Down to Idle waveform characteristics of the proposed PFD in a PLL, respectively. Both examples reflect the new timing constraints. [001 42] The proposed PFD was implemented in a 1 -1 0GHz PLL with the charge-based CP and a ring-based VCO. This PLL was fabricated in an all-digital TSMC 40n m process with a variable su pply voltage of 0.5-1 .2V. Figu re 1 8 shows the layout and die micrograph of the PFD, CP, and LF portion of the PLL; the PFD, wh ich consists of two DFFs in its entirety, has a total active area of 1 6μηι ² . The PLL with the PFD was physically tested; the silicon measu rements of the PFD are shown in Table 2.

[001 43]

Table 2 where,

Ref. 6: H. Rategh and T. Lee, Mu lti-GHz frequency synthesis & division: frequency synthesizer design for 5 GHz wireless LAN systems.

Springer, 2001 ; Ref. 7: W. Chen, M. Inerowicz, and B. Ju ng, "Phase frequency detector with minimal blind zone for fast frequency acqu isition," IEEE

Transactions on Circu its and Systems II: Express Briefs, vol. 57, pp. 936-940, Dec. 201 0; Ref: 8: W. Lee, J. Cho, and S. Lee. "A high speed and low power phase- frequency detector and charge-pu mp," ASP-DAC'99, Proceedings of the Asia and South Pacific Design Automation Conference, pp. 269- 272 , 1 999;

Ref: 9: M. Mansu ri, D. Liu , and C. Yang, "Fast frequency acqu isition phase-frequency detectors for GSa/s phase-locked loops," ESSCIRC '01 , Proceedings of the 27th Eu ropean Solid-State Circu its Conference, pp. 333-336, 2001 ; and

Ref: 1 0: J. Lan, F. Lai, Z. Gao, H. Ma, and J. Zhang, "A nonlinear phase frequency detector for fast-lock phase-locked loops," ASICON '09, IEEE 8th I nternational Conference on ASIC, pp. 1 1 1 7- 1 1 20, 2009.

[001 44] Notably, the PFD consu mes 61 8.5 nW with a 1 .0V su pply and a reference frequency of 1 OOMHz, where the VCO frequency was 5GHz and a N = 50 divider was used to produce the feedback

frequency. Fu rthermore, due to the PFD-CP combination, there is Ops dead zone, a low 0.1 -0.3° phase error, and 0.80±0.05 ps j itter for the entire operating range of the PLL.

[001 45] Figu re 1 0 displays an example of the phase noise and spectru m characteristics with reference spu rs <-70dBc for this PLL. [001 46] Table 3 provides a snapshot of the PLL performance in which the proposed PFD was utilized; these results are compared to other PLLs which use DFF-based PFDs in their architecture.

[001 47]

Table 3 where:

Ref 1 1 : A. Loke, R. Barnes, T. Wee, M. Oshima, C. Moore, R. Kennedy, and M. Gilsdorf, "A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking," IEEE Journal Solid-State Circu its, vol. 41 , pp. 1 894-1 907, Aug. 2006; and

Ref: 1 2: W. Chiu, Y. Huang, and T. Lin, "A dynamic phase error compensation technique for fast-locking phase-locked loops," IEEE Jou rnal Solid-State Circu its, vol. 45, pp. 1 1 37-1 1 49, July 201 0.

[001 48] This work has introduced a low power, fast, and compact dual reset D flip-flop based phase-frequency detector design for use in multi-GHz PLLs. The no-added delay PFD design is composed of complex-complementary logic DFFs which were optimized for use with a discrete charge-transferring charge pu mp by matching the Reset-to- Q propagation delay to the charge pump's switching time directly, resu lting in zero dead zone between these two blocks. The desirable outcome of using this PFD-CP combination in a PLL is an overall decreased PLL control loop delay and an advantageous reduction in the phase noise and jitter in the PLL, providing a fast, accurate phase lock. Furthermore, the PFD is scalable to and between su b-μηι process nodes and is able to be utilized at low supply voltages well below 1 V.

[001 49] Proposed Voltage Controlled Oscillator Designed with Charge Coupling: [001 50] A preferred embodiment of the present invention provides a novel tunable wide-operating range capacitively phase-cou pled low noise, low power ring-based voltage controlled oscillator for use in multi-GHz phase-locked loops. The basic building blocks of the ring oscillator (RO) design are discussed along with a technique to expand the VCO to a variety of phases and frequencies without the use of physical inductors. Improved performance with minimal phase noise are achieved in this ring VCO design through distributed passive- element injection locking (IL) of the staged phases via a network of symmetrically placed metal interconnect capacitors. Using this method, a 0.8-to-28.2 GHz quadratu re ring VCO was designed, fabricated, and physically tested with a PLL containing the charge pump and phase-frequency detector, in an all-digital 40nm TSMC CMOS process.

[001 51 ] State-of-the-Art Ring VCOs: [001 52] Ring oscillators based on digital logic building blocks are a popular choice for multiprotocol phase-locked loops operating in the 0.5-1 2GHz range due to their minimal area, wide-tuning range, low power consumption, scalability to and between sub-μηι

technologies, and general lack of required analog process extensions. Compared to tuned, high-Q LC oscillators which target specific higher frequencies at the expense of an increased power and area trade-off, ROs have inferior phase noise performance which restricts their use to only non-critical applications. Specifically, the "resonator" Q of a ring oscillator is low because the energy stored in every cycle at each output node capacitance is immediately discarded, then restored at the worst possible time at the resonator edges instead of at the ideal peak voltage as in an LC oscillator. In general, from a broad

perspective, this lack of energy efficiency accounts for the well-known overall poor phase noise performance exhibited by state-of-the-art ROs.

[001 53] Other factors which affect phase noise in both single- ended and differential ring oscillators such as flicker (i.e. 1 /f), shot, thermal, and white noise have been extensively studied over the last 20 years as stated in the references 1 ). A. Hajimiri, et al., "Jitter and phase noise in ring oscillators," IEEE J. Solid State Circuits, vol. 34; 2). A. Abidi et al., "Phase noise in inverter-based & differential CMOS ring oscillators," IEEE CICC'05 , 2005, pp. 457-460; and 3). A. Homayoun and B. Razavi, "Relation between delay line phase noise and ring oscillator phase noise," IEEE J. Solid State Circuits, vol. 49, pp. 384- 391 , Feb. 201 4. As IC technology scales to deep su b-μηι, nu merous works have been dedicated to applying these principles and

developing circu itry to improve the performance of ROs in PLLs which operate in the mu lti-GHz range. The importance of doing so lies in the in herent non-feasibility of fabricating LC oscillators at smaller featu re sizes due to large area and cost as well as the lack of necessary analog extensions being readily available for u ltra-deep su b-μηι CMOS processes.

[001 54] Among the various practices utilized to lower the phase noise of a ring oscillator operating in a phase-locked loop, two tech niques which have been proven successfu l at smaller featu re sizes stand out: 1 ) using additional injection locking circu itry and 2) exploiting creative, yet strict symmetry in the ring design and physical layout. For instance, in the reference, J. Chien, et al., "A pu lse- position-modu lation phase-noise-reduction technique for a 2-to- 1 6GHz injection-locked ring oscillator in 20nm CMOS," ISSCC Dig. Tech. Papers, pp. 52-53, Feb. 201 4, it u ses precisely timed IL which yields extremely low phase noise resu lts at frequencies u p to 1 6GHz while the another reference, M. Chen et al., "A calibration-free

800MHz fractional-N digital PLL with em bedded TDC," ISSCC Dig.

Tech. Papers, pp. 472-473 , Feb. 201 0, presents a u n ique sym metrical differential RO wh ich can loosely be classified as IL though the use of passive resistors. In the reference, W. Deng et al., "A 0.0066mm2 780MW fu lly synthesizable PLL with a cu rrent-output DAC and an interpolative phase-cou pled oscillator using edge-injection technique," ISSCC Dig. Tech. Papers, pp. 266-267, Feb. 201 4, IL techniques are applied to an innovative, highly symmetric ring oscillator structure composed of 3 single-ended logic-based rings. In these examples, IL techniques require extra circu itry which may increase the power and/or area. Additionally, symmetry may require extra design time and area.

[001 55] Proposed Expandable, Capacitively Charge-Coupled Ring VCO for PLLs:

[001 56] The present invention uses phase injection locking via a network of symmetrically placed passive metal interconnect cou pling capacitors to reduce the phase noise of an inverter-based ring VCO as shown in Figure 1 9. The result of the proposed RO design is a more energy efficient circu it which evenly distributes charge between the various nodes during oscillation. Furthermore, the fundamental basic building blocks of the proposed ring oscillator are discussed in order to provide a straightforward methodology for expanding the design to work for multiple phases and a variety of frequencies in the 0.5-to- 30GHz operating range. Using the aforementioned procedu re, a 0.8- to-28.2 GHz quadrature ring VCO was designed, fabricated, and physically tested with a PLL in an all-digital 40nm TSMC CMOS process.

[001 57] The ring VCO discussed here is designed using a cu rrent- starved inverter-based ring oscillator structu re. One advantage of using this type of RO is its simplicity. More importantly, rings of this natu re can be built using basic circuit elements readily available in any given IC process. In fact, multiple-staged inverter-based ring oscillators are used extensively on practically all silicon dies for process monitoring. However, traditional ROs suffer from two major disadvantages which have limited their usefulness in PLL designs: 1 ) poor jitter (noise) characteristics and 2) lack of spectral pu rity

(distortion).

[001 58] Here a design approach is presented which takes two or more identical inverter-based staged-ROs and uses phase injection- locking via capacitive coupling to provide a VCO with improved phase noise performance and spectral pu rity properties su perior to state-of- the-art RO designs, making the proposed ring VCO design more comparable to those of LC-based ones. Additionally, the application of the proposed ring VCO offers many other desirable properties beyond low noise attributes including: ability to have precise quadratu re with many additional phase outputs available, wide range tunability, inductor-like spectral pu rity quality and stability without using inductors, full scalability to and between ultra-deep sub-μηι IC process nodes, compact physical size with minimal sized inverters, and the ability to work at supply voltages at 1 V and below with extremely low power operation due to the capacitors not dumping their energy on a cycle by cycle basis as in a ring oscillator.

[001 59] The building blocks of the proposed ring VCO, shown in Figure 20 include: 1 ) current-starved inverters for control voltage, VC, tu ning, 2) two or more rings, r, made u p of a nu mber of odd cu rrent- starved inverter stages, s, and 3) relatively small symmetrically laid— out intercon nect capacitors, Co=C _eq , to cou ple the phases of the neighbou ring input and output nodes of the rings, and optionally, 4) a logic-controlled bank of interconnect capacitors, C 1 -C2 , for wider frequency range tu ning using transmission gate switches.

[001 60] I n a preferred embodiment of the present invention rail to rail com plementary injection field effect transistor (CiFET) based bypass control voltage controlled oscillator 74" shown in Figu re 33 may be used instead of the bu ilding block shown in Figu re 20. The voltage controlled oscillator 74" includes three stages of CiFET am plifier pairs 741 a, 741 b and 741 c. While the exemplary figu re shows three stages, the nu mber of stages can be any odd nu mber. Each of the CiFET am plifier pairs 741 a, 741 b and 741 c com prises P- type iFET 741 p and N-type iFET 741 n, and bypass transistor 742. The bypass transistors 742 provides the alternative path for the cu rrent that wou ld otherwise go to the inveter's output terminal and charge the capacitance of the next input. Thus, the operating frequency is at the a maximum with no control voltage and slows down as a control voltage 743 is applied.

[001 61 ] The N-type iFET 741 n is a cu rrent inverter as shown in Figu re 34, which is the dual concept of a normal voltage-inverting FET. The total cu rrent th rough the iFET is fixed by the gate-to-sou rce voltage and when a change in cu rrent at the mid-chan nel cu rrent port (or "iPort") 81 node is noted, the inverse of that current change can be seen at the iFET drain output making the iFET a current inverter. The iFET source channel current is fixed by Vqs and thus any current change is steered from the drain to the iPort 81 . This type of charge- movement or cu rrent-based logic concept originated in bipolars as cu rrent-mode logic (CML) where the inputs and outputs are in voltage, but the computation takes place with fast current signal swings in a staged differential BJT circuit. The tradeoff with bipolar CML is that the power dissipation is great and it is only used when extremely fast digital logic is desired with little regard to a battery, and this CML requires a bipolar IC process.

[001 62] Assembling an N-type 741 n and P-type iFET 741 p

together yields the seminal CiFET cell 741 as shown in Figure 35. Both the PiPort 81 p and the NiPorts 81 n effect a + change to the output voltage port 81 o at the common drain connection.

[001 63] Here though, in the CiFET, its power dissipation is minimal as the current changes involved are in the pico- to nano-Amp range depending on the sizing of the CiFET. On the other hand, the resu lts are similar, as there is a way to build logic gates out of the CiFET based on cu rrent, resulting in ultra-fast logic which has essentially no voltage change at both the input and output logic interconnect wires, and the inputs are referenced at the iPort termination resistance instead of the logic voltage transmitter providing very high noise immunity. This makes the logic parasitic insensitive and noise immune yielding very low power and extremely high frequency operation. There are also methods of throttling the speed/power relationship, or turning the circuits off and back on again at logic speed. When a current is injected into the iPort, it substitutes for its portion of the existing source channel current. This is because this total source channel current is controlled by its voltage between the gate and source, which has not been caused to change by the iPort cu rrent injection. Thus the origin of sou rce channel cu rrent is steered around the drain channel through the iPort. [001 64] This wou ld result in an exact subtraction of iPort cu rrent from the output drain current as there is no other cu rrent path. This introduces an entirely new MOS device: the ultra-fast precision

"cu rrent inverter." It is built out of digital parts and is process independent. More iPort cu rrent, yields less drain cu rrent, which is the output current. A current mirror operates the other way and is fragile. Also, the current can go in either direction passing through zero, truly bidirectional as compared to the base cu rrent of a bipolar.

[001 65] The source channel is exceptionally low resistance because it has a high overdrive on the gate while the voltage gradient along this sou rce channel is clamped to near zero by the self-cascode structu re of the iFET. This is similar to operating this channel in weak inversion, thus the channel cu rrent is driven by carrier diffusion (exponential), and not a voltage gradient (square-law) along this sou rce channel. We have named this channel condition "super- satu ration." In contrast, weak inversion has few carriers which pass along the su rface where they pick u p noise from su rface carrier traps. Because this sou rce channel has an abu ndance of carriers and these carriers do not have to transit the chan nel length, the sou rce channel operates faster than any other MOS channel known. The carriers only have to push on adjacent carriers (diffusion).

[001 66] Since both the PiPort 81 p and NiPort 81 n are + cu rrent in puts, cu rrent can be removed from of one port and injected into the other port in effect bypassing the CiFET drain chan nel cu rrent wh ich charges and discharges the delay, or frequency control capacitance of a ring oscillator 74 as shown in Figu re 33.

[001 67] Figu re 36 depicts the joining of an NiFET 741 n and PiFET 741 p forming a CiFET 741 , but with the addition of a transistor 742 which bypasses cu rrent arou nd the CiFET drain output. Th is additional MOSFET can be either N- or P-chan nel where its gate control voltage performs the inverted fu nction of the other. This CiFET 741 of Figu re 36 illustrates the CiFET's operation in the VCO of Figu re 33.

[001 68] Th is cu rrent bypass is controlled by the gate voltage on a MOSFET connecting the two iPorts 81 p and 81 n. A major advantage of this delay control is that all the timing nodes maintain a constant am plitude and in the injection-locked VCO the noise critical threshold remains at the zero crossover where the slope is at its maximu m. [001 69] The simplest u nit form of the proposed ring VCO is the single-staged, dou ble-ring differential oscillator Figu re 2 1 . If the input is connected to the output of its respective ring with an appropriate im pedance, Z , the 2x1 ring will possess a behavior likened to that of a gyrator in that the capacitive circu it acts inductively due to its stru ctu re. This is due to a capacitor in the loop creating a "gyrator" that can masquerade as an inductor which fu nctions as a "dual" circu it element. These capacitors phase-cou ple the input and output nodes of the stages together forming a distributed spiral virtual inductor. This r= 2 , s= l gyrator example is not to be confused with a sim ple latch where r= l , s= 2. I n the latter case, the inverters act in series and do not oscillate due to oscillation conditions not being satisfied. The differential gyrator must be strictly cross-cou pled in the layout of the circu it and additionally, ZA and ZB mu st be set appropriately. As expected, from its simplicity, this is the highest frequency

configu ration .

[001 70] Additionally, the requ irements for oscillation can be expedited via sufficient delay through the layout wire parasitics, which are readily fou nd on any chip due to imperfect isolation and slight process variation, and therefore shou ld be used to an advantage in this circu it. Although exploratory exam ples of this gyrator point to very high frequencies being obtainable u p to 75GHz, the circu it suffers from poorer phase noise performance as compared to mu ltiple stages of s= 3 and higher. This is due to the noise being correlated to a minimum number of nodes. Increasing the nu mber of nodes to 3 or 5 significantly improves the performance of the proposed ring VCO. Silicon measurements showing this can be found in the experimental results shown below.

[00171 ] The single-stage unit may be easily expanded to a more useful ring VCO which provides multiple phases. The output phases available for the rxs tuned ring VCO may be found at every Θ:

[00172] θ = —vailable = 1 r*^s1 [EQ. 17]

# of phases a

[00173] where s is an odd, positive integer representing the number of inverter stages in a single ring; r is a positive integer greater than 1 representing the number of rows. For the ring VCO in Figure 20, there are s=3 ring inverter stages and r=2 rows connected by neighboring node capacitances. Θ for this example is then calculated to be 60°; therefore, there are 6 output phases available at 0°, 60°, 120°, 180°, 240°, and 300° in this ring. [00174] The frequency of a general rxs ring VCO is governed by the propagation delay of the s current starved inverters in a single ring. The finely-tuned VCO output frequency, fvco, is controlled by means of Vc, by starving current through either (or both) the top pMOS or bottom nMOS transistors shown Figure 20; in this work, the bottom nMOS transistors were used as the inverters' current control. The inverters symmetrically self-bias around their midpoint. Additionally, fouT is also affected by the intentional loading by the tuning capacitor(s) and any switch and wiring path resistance at each node; for instance, increasing the capacitance and/or resistance lowers fouT.

[001 75] The general output frequency of an rxs VCO may be found by the following equation: [001 76] f _vco = -^- =

^T total ^T ring ^Jr't interconnect _C i) + (r )R _e qC _e q)

[EQ. 1 8]

[001 77] where τ _ρά is the propagation delay of a single current- starved inverter in the ring; C _eq is the parallel combination of the cou pling capacitors C0-2 that are in-use; and R _eq is the equivalent parallel resistance of the wired path and any switch resistance connected to the coupling capacitors in use. Parasitic capacitances, Co, should be factored into this equation for accu racy. This basic rxs ring VCO structu re is reconfigurable to allow for a variety of phases (e.g. by adjusting r and s) and frequencies (e.g. by varying the VC for fine tuning and C _e q for course), an example of this will be presented in the next section for the quadratu re configuration.

[001 78] The proposed tuned ring 4x3 VCO in Figure 22 is one such expansion of the rxs ring oscillator. In this case, 4 of the 1 2 phases have been used to produce the quadrature outputs for the PLL. The 3D section of the ring in the u pper left of Figu re 22 provides a picture of how charge is differentially cross-coupled within the ring through relatively small yet symmetrically laid-out, spirally-linked neighboring interconnect capacitances at every node. The charge cou pling path creates a continuous, virtual inductor, adding to the resonance pu rity of the ring VCO. A capacitor in a feedback path of the oscillator acts much like an inductor allowing the VCO to operate in a linear (i.e. high-quality sine-wave) mode, similar to an LC oscillator as opposed to a RO which operates in a switching mode. As a resu lt of this virtual inductor in the feedback path, spectral purity (odd harmonics) is comparable to that of LC based oscillators, but this ring oscillator is scalable to deep sub-μηι processes and has the added featu re of a wide frequency tu ning range. This provides low distortion which can be seen in the experimental results section. All of the inverters are operating in concert to produce a single sine wave cycle in precisely equal incremental phase steps. The distributed pseudo- inductor causes the energy lost during a cycle to be restored at the phase angle that adds minimal noise (i.e. jitter), which is the exact opposite of a conventional ring oscillator where energy is added at the most jitter sensitive phase angle. Lastly, the wide operating range of the ring VCO of the present invention is due to the digital logic- controlled bank composed of 3 symmetrically laid-out interconnect cou pling capacitors, allowing for coarse tuning over 4 overlapping frequency ranges shown in Figure 23. It is also found that the VCO of the present invention is capable of outputting a sine wave signal comprising a fundamental and harmonics that are separated by at least 50 - 70dB.

[001 79] Experimental Results for the Proposed VCO in a PLL with the CP and PFD: [00180] Hereinafter provides overviews of the silicon

measurements of a variety of rxs expansions of the proposed ring VCO structure shown in Table 4 and the proposed quadrature 4x3 ring VCO implemented inside a charge pump PLL of the present invention, all of which were fabricated in a 40nm all-digital CMOS process and tested. The block diagram of the PLL which the VCO— along with the CP and PFD from earlier in this chapter— were places is shown in Figure 24. A die micrograph of the proposed 4x3 quadrature VCO in the PLL is shown in Figure 25a. Figure 25b shows a layout plan example for symmetric 4x 3 VCO. It is found that layout symmetry of devices and interconnect in VCO is of utmost importance to ensure constant capacitive charge balance and low noise operation. As it is shown in Figures 25a and 25b, to maintain symmetry of devices, wirings and capacitors are strategically placed in the center, and ring oscillators are placed therearound. The phase noise and output spectrum are shown in Figure 26. Table 5 compares the proposed 4x3 ring VCO results to state-of-the-art examples, while Table 6 compares similar PLLs to the one used for this work as is shown in Figure 24 which uses the CP from PFD described above. [00181] This work has introduced an expandable structure for a tunable wide-operating range capacitively phase-coupled low noise, low power ring-based VCO for use in multi-GHz PLLs. Using this technique, a quadrature ring-based VCO was implemented in an all- digital 40nm TSMC CMOS process. Most notably, the proposed 4x3 ring VCO occupies an area of 0.0024mm ² , consumes a power of 0.77mW at a 1 .OV supply voltage, and possesses a phase noise of - 1 24.5dBc/Hz at the 1 OMHz offset for a carrier frequency of 28.0GHz. Fu rthermore, the present invention has the widest reported operating frequency range of any pu blished VCO from 0.8-to-28.2 GHz. The 5 VCO FOM is also the best reported for ring-based VCOs and is

comparable to that of LC oscillators due to the passively-phase cou pled IL symmetric ring topology and inherent low power operation.

[001 82]

Table 4

1 0 [001 83]

Table 5 where:

¹ FOM for the VCO = PN - 20 log + lOlog (P/lmW); FOM for the PLL = lOlog [(σ,/ls) ² x (P/lmW)]. Ref. 13: L. Cai and R. Harjani, "1 -1 OGHz inductorless receiver in 0.13μηι CMOS," IEEE. RFIC'09, 2009, pp.61 -64;

Ref. 14: D. Fischette, D. Michael, A. Loke, M. Oshima, B. Doyle, R.

Bakalski, et al., "A 45nm SOICMOS dual-PLL processor clock system for multi-protocol I/O," ISSCC Dig. Tech. Papers, pp.246-247, Feb.2010;

Ref. 15: J. Chien, P. Upadhyaya, H. Jung, S. Chen, W. Fang, A. Niknejad, et al., "A pulse-position-modulation phase-noise-reduction technique for a 2-to-l 6GHz injection-locked ring oscillator in 20nm CMOS," ISSCC Dig. Tech. Papers, pp.52-53, Feb.2014; Ref. 16: M. Chen, D. Su, and S. Mehta, "A calibration-free 800MHz fractional-N digital PLL with embedded TDC," ISSCC Dig. Tech. Papers, pp.472-473, Feb.2010;

Ref. 17: W. Deng, D. Yang, T. Ueno, T. Siriburanon, et al., "A

0.0066mm ² 780μ\Λ/ fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique," ISSCC Dig. Tech. Papers, pp.266-267, Feb.2014;

Ref. 18: A. Elshazly, R. Inti, B. Young, and P.K. Hanumolu, "A 1.5GHz 890MW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1 b TDC," ISSCC Dig. Tech. Papers, pp.242-243, Feb.2012;

Ref. 19: M. Raj, S. Saeedi, and A. Emami, "22.3 A 4-to-l 1 GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS." ISSCC' l 5 , Proceedings of the 201 5 IEEE International Solid State Circuits Conference, Feb. 201 5; and

Ref. 20: J. Lee and H. Wang, "Study of su bharmonically injection- locked PLLs," IEEE J. Solid-State Circuits, vol. 44, no. 5 , pp. 1 539- 1 553, May 2009.

[001 84]

Table 6 where:

Ref. 21 : M. Brownlee, P. Hanumolu, K. Mayaram, and U. Moon, "A 0.5 to 2.5GHz PLL with fully differential supply-regu lated tuning," IEEE J. Solid State Circu its, vol. 41 , pp. 2720-2728, Dec. 2006; and

Ref. 22: A. Sai, Y. Kobayashi, S. Saigusa, O. Watanabe, et al., "A digitally stabilized type-Ill PLL using ring VCO with 1 .01 ps rms integrated jitter in 65 nm CMOS," ISSCC Dig. Tech. Papers, pp. 248- 250, Feb. 201 2. [001 85] The procedu re for Complementary complex logic (or C ² L) is simple and straightforward. In this section, we will give an example of a logic function and demonstrate how to construct the resulting gate for compactness and speed for a desired path. Examples of a normal digital circuit construction and the proposed C ² L optimization of the same function will be demonstrated here for a basic

understanding. This method can be applied to any digital or analog- in-digital circuit from which a truth table may be constructed and a function found, such as the PFD DFFs, shown in the next section. It is most useful when there is some complexity in the fu nction as opposed to very basic gates such as the inverter or 2-input AND.

[001 86] Step 1 : Construct the truth table for the desired function like the example in Table 7.

[001 87]

12 C 1 1 0 0 1

13 D 1 1 0 1 1

14 E 1 1 1 0 0

15 F 1 1 1 1 1

Table 7

[00188] Step 2: Construct the complementary Karnaugh Map (or K-Map) and resulting function equations for bothX.be grouped Logic 1 's and the Logic 0's as shown in Figure 27 for the truth table in Table 7. Please note that the K-Map is a method to simplify Boolean algebraic expressions invented in 1953. The K-Map takes truth table results and places these on a 2-dimensional grid in order to identify and eliminate race conditions where the output is dependent on other events. From the K-Maps, the resulting function equations are found to be:

[00189] Y (1) = AC + AD + BD [EQ. 19]

[00190] Υ(ϋ) = ACD + ABD + BCD [EQ.20]

[00191 ] By constructing both of the complementary K-Maps and deriving the complement EQs. 19 and 20 from this, we ensure that there is no doubling up or cross-over and that the final Y signal is logically correct.

[00192] Y(0) = ACD + ABD + BCD→ ACD +BD(A+C) [EQ.21]

[00193] The C ² L method does not use EQ.21 and De-Morgan, nor does it group for minimum numbers of nMOS transistors. Instead C ² L uses the opposite diffusion type of the P-channel transistors to perform the phase inversion which will be covered in the next step.

[00194] Step 3: Construct the pull-down nMOS or "N" network using the ungrouped Logic 0's equation from EQ.20 which results in Eq. (A.4).

[00195] Y(N) = ACD +ABD + BCD [EQ.22]

[00196] For the pull-up pMOS or "P" network we must first notice that the P-channel transistors use the opposite diffusion type as compared to the N-channel transistors in order to perform a phase inversion. This is invoked by simply using the opposite phase signals on the P-channel gate, thus all of the terms in EQ. 19 become inverted as shown in EQ.23 for the pull-up network:

[00197] Y(P) = AC + AD + BD [EQ.23]

[00198] It is now safe to wire-OR the P-channel pull-up to the N- channel pull-down "half" complex gates together from Y(P) and Y(N). This is how a CMOS inverter works.

[00199] To finish, combine the resulting half logics for the pull-up and pull-down gates from Figure 28 b) and c) to form the C ² L logic gate in Figure 28 d). [00200] Step 4: From the logic gate in Figure 28 d). which includes the pull-up and pull-down networks in Figures 28 b) and c), respectively, draw the corresponding schematics. This is shown in Figure 29 b), whereas the traditional method is shown in Figure 29 a), which is optimized form minimum nMOS transistors due to the original grouping in EQ. 21 .

[00201 ] Step 5 : Draw the sideways "string" diagrams from the schematics in Figure 29, which results in Figure 30. When doing this for the C ² L, make sure have no places where there are breaks in the active area and move transistors around to do so. The idea is that EQs. 22 and 23 produce the right amount of transistors to make su re of this; this is because transistors take up much less space than a gap in active area in the layout, while also producing less parasitics than traditional methods due to more efficient interconnect within the cell.

[00202] Step 6: Draw the layout stick diagrams directly from the string diagrams in Figure 30 which results in Figure 31 .

[00203] Step 7: From the layout stick diagrams in Figu re 31 , create the layout as shown in Figure 32 making sure to account for the -2.5 times in n-channel mobility, μ _η , as compared to the p-channel, μ . Please note that making the pMOS 2 to 2.5 (or even 3) times the size of the nMOS is generally sufficient based on the IC process due to the differences in electron and hole mobility for the process being used, (this can be determined by equating rise fall times in an inverter via sizing as covered by most digital CMOS design text books). If the path is extremely critical, a designer may increase the size of the pMOS (and the nMOS) in that path, but it is advisable to do this after a schematic simu lation to ensu re that the increased speed resu lts are worth the tradeoff in area, as the C ² L method is used to maxim ize for speed and area together at their peak. Note the difference in area between the traditional min imu m nMOS transistor layout Figu re 32 a) as compared to the C ² L method which has more small nMOS

transistors and less of the bu lky pMOS transistors Figu re 32 b). Also note the active areas in the nMOS region where there is a split in due to the split in active area in Figu re 32 a), whereas the C ² L method does not have this break. [00204] The normalized resu lts from the C ² L method in this specific example is a reduction of area and power by 25% and an increased speed of 1 .5 times that of the traditional method which is due to the reduction of the parasitic capacitances (e.g. less charging and discharging requ ired). Th is is a direct optimization of the power- delay product (PDP) and energy-delay product (EDP), where the PDP is a measu re of energy per cycle or operation, whereas the EDP is a quality metric of the gate, relationships through the reduction of parasitics:

(Qtota

[00205] PDP = O ^v dd _ ( ^c total ^v dd ^v dd _ ( ^C l parasitics

r Pavg t ^L p =

2 2 2

[EQ. 24]

QtotalVddt-p _ ( ^c total) ^v dd ² tp _

[00206] EDP - E _tota it _p:

2 2 2

[EQ. 25] [00207] where P _aV g is the average dynamic power dissipation, Etotai is the energy per operation, Qtotai is the charge which shifts (either charging or discharging) in a single operation, Ctotai is the total of the parasitic and output capacitances of the next gate, t _p is the average of the low-to-high and high-to-low propagation delays of the circuit given by:

[00208] t _p = ( ^VH - ^Vl~h ) [EQ.26]

[00209] The high-to-low propagation delay may be found by: [00211] with:

[00213] where the drain current in the saturation and linear regions may be calculated by:

[00214] Saturation: Quadradic when V _GS > V _thn and V _DS ≥ V _e ^

1 W 2 1 W

lD _S at = 2¾J^(¾) t ¹ + ^X i ^V DS - V _EFF )] « -μ _η — ^y ff ^X [QDI

(for finFETs like that in Fig.2.5b, let W = W _eff = n _fingers [W _fin + 2(h)]),

[EQ.29];

[00215] and: [0021 6] Triode / Ohmic: Linear when V _GS > V _th .n and V _DS < V _t h _lin - ½ -y Cox (y _e ff)VDs - -y

[EQ. 30]

[0021 7] for the nMOS transistor. EQ. 29 and EQ. 30 are general equations for the nMOS. The pMOS equations are exactly the same, but with the pMOS model values substituted with reversed polarities. These equations also assume that the bulk is separately tied to the sou rce of each nMOS and pMOS device, not accounting for back- biasing bulk effects. finFETS can be related to the basic nMOS and pMOS equations by recognizing the finFET's actual Weff in EQ. 29.

Notably, the finFET has 3 charge conduction channels long the 2 sides of height and single width of the fin. For EQ. 29, the channel length modu lations, λ, may be ignored for simplicity.

[0021 8] For the average current from low-to-high this same equation in EQ. 28 may be calculated for the pMOS then EQ. 27 calculated for the same transition. Matching the low-to-high and high-to-low delays is of utmost importance and is easily done with the C ² L method through normal sizing of transistors based on mobility (from Step 7). [0021 9] Finally, the C ² L method may be applied to any digital or AiD circuit for which a designer can make a truth table. It can also be applied to the phase-frequency detector DFFs in the next section for which a fast Reset-to-Q path must be established.