Title:
PHASE LOCKED LOOP PLL (PLLPHASE LOCKED LOOP) CIRCUIT AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/042911
Kind Code:
A1
Abstract:
In order to reduce a leak current flowing through a charge pump circuit when charge pump operation is stopped, the present invention is provided with a plurality of charge pump circuits that each generate a charge pump current at a common output node connected to a low-pass filter. Each of the charge pump circuits comprises a first current source as a discharge-type constant current source for the output node, a first switch for switching the connection between the first current source and the output node, a second current source as a suction-type constant current source for the output node, and a second switch for switching the connection between the second current source and the output node. At least one of the charge pump circuits has a potential equalization means for adjusting a first node between the first current source and the first switch, a second node between the second current source and the second switch, and the output node to have equal potentials when the charge pump operation of the charge pump circuit is stopped.
Inventors:
TAKAIRA TOORU (JP)
ARIMA DAISUKE (JP)
TOKIMATSU JUNJI (JP)
ARIMA DAISUKE (JP)
TOKIMATSU JUNJI (JP)
Application Number:
PCT/JP2015/070525
Publication Date:
March 24, 2016
Filing Date:
July 17, 2015
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
H03L7/093; H03L7/087
Foreign References:
| JP2000286700A | 2000-10-13 | |||
| JP2009246606A | 2009-10-22 | |||
| JPH09116430A | 1997-05-02 | |||
| JPH11127076A | 1999-05-11 | |||
| US7570105B1 | 2009-08-04 |
Attorney, Agent or Firm:
MATSUO KENICHIRO (JP)
Ken-ichiro Matsuo (JP)
Ken-ichiro Matsuo (JP)
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