Title:
PHASE LOCKED LOOP WITH SUB-HARMONIC LOCKING PREVENTION FUNCTIONALITY
Document Type and Number:
WIPO Patent Application WO/2016/061781
Kind Code:
A1
Abstract:
Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.
Inventors:
LUO KEXIN (US)
RUI YAN (US)
LU SHAOYONG (US)
YIN RUI (US)
SHEN YU (US)
RUI YAN (US)
LU SHAOYONG (US)
YIN RUI (US)
SHEN YU (US)
Application Number:
PCT/CN2014/089267
Publication Date:
April 28, 2016
Filing Date:
October 23, 2014
Export Citation:
Assignee:
LATTICE SEMICONDUCTOR CORP (US)
International Classes:
H03L7/06
Foreign References:
| CN1162219A | 1997-10-15 | |||
| CN1269640A | 2000-10-11 | |||
| US7230495B2 | 2007-06-12 |
Attorney, Agent or Firm:
SHANGHAI PATENT & TRADEMARK LAW OFFICE, LLC (Shanghai 3, CN)
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