Technical Field

The invention relates generally to the field of power electronics, more particularly to transfer power wirelessly. Aspects of the invention relate to a phase-shift modulated fullbridge power inverter configured for use in a wireless power transfer system. Another aspect of the invention relates to a method of operating a phase-shift modulated full-bridge power inverter in a wireless power transfer system. Another aspect of the invention relates to a method of fitting an augmented passive circuit to a phase-shift modulated full-bridge power inverter configured for use in a wireless power transfer system. Another aspect of the invention relates to a kit of augmented passive circuit parts for fitting to a phase-shift modulated full-bridge power inverter configured for use in a wireless power transfer system.

In this respect, it is worth noting the term "augmented passive circuit" is used in the sense that no active switches are required in the augmented passive circuit.

One aspect of the invention has particular, but not exclusive, application in reducing power loss in the power inverter. For instance, use of the techniques disclosed herein may allow for the power inverter to enable all power switches in a wireless power transfer power inverter to be soft-switched for all operating regions. Use of the techniques disclosed herein may allow for zero-voltage switching (ZVS) to be achieved in all of the power switches of the power inverter for all load conditions, without the need for coordinated control and communication with the receiver circuit.

Background

With improvements of switching speeds and power capabilities, power electronic devices such as power metal-oxide-semiconductor field-effect-transistors (MOSFETs) and insulated gate bipolar transistors (IGBT) have been widely used in electrical energy conversion. Recent advances in wide-band-gap (WBG) semiconductor technology further enhance the switching frequency range and power ratings of these power devices. Power converters based on power electronics technology can switch at hundreds of kilo-Hertz in commercial switched mode power supplies (SMPS) and are being considered for switching up to tens of MegaHertz for some emerging applications such as wireless power transfer (WPT).

A major limitation on the switching frequency is the switching power loss in the power switches of a power converter. During the turn-on and turn-off processes, the instantaneous voltage across and the current in the power switch change with time. The instantaneous product of this transient voltage and current contribute to the switching power loss of such power switch. The switching power loss results in heat loss and thermal stress on the structure of the power switch. The large rate of change of voltage (dv/dt) and rate of change of current (di/dt) also contribute to electromagnetic interference (EMI). Traditional switching methods without reducing the switching power loss is called "hard-switching" techniques. In the previous two decades, "soft-switching" methods have been developed and used for many power converters and power inverters. Soft-switching methods create zero voltage and/or zero current for the power switch during the turn-on and turn-off transient process so that the switching loss can ideally be eliminated. Soft-switching techniques can be classified as zero-voltage switching (ZVS) and zero-current switching (ZCS).

Soft-switching techniques for half-bridge and full-bridge power inverters, under 50% dutycycle pulse-width-modulation (PWM) control, were reported in the 1980s and 1990s in several seminal papers [l]-[3]. Switching the inverter at an operating frequency that falls into the inductive region of the load impedance can ensure ZVS on the condition that the load current is continuous. Under light load condition, the load current becomes discontinuous and ZVS condition is lost. This problem can be solved by adding an augmented inductive-capacitor (LC) circuit branch across the load to maintain a minimum continuous current to ensure ZVS [4],

For full-bridge power inverters under phase-shift modulation (PSM) control, discontinuous current occurs when the phase-shift angle is large (e.g., above 150°). Adding an additional LC circuit branch cannot achieve ZVS. This well-known problem has been a major technical challenge that has not yielded a good solution despite several proposals being made in the past. A recent review paper [5] provides a comprehensive coverage of various forms of symmetric PWM phase-shift converters [6] and asymmetric PWM phase-shift converters [7] with high-frequency isolation transformers for dc/dc power conversion. That said, the phase-shift converters in [6] and [7] were proposed as dc-dc power supplies for telecommunication applications which are different from WPT considerations, as herein, because the coupling coefficients in WPT applications are not always constant as in high- frequency isolation transformer. The uncertain and yet large leakage inductance in the loosely coupled transmitter and receiver coils in a WPT system could affect the soft- switching conditions in a phase-shift converter.

A partial solution to achieve soft-switching in phase-shift modulated power inverter is to use a quasi-resonant circuit as reported in [8], Another suggestion of achieving soft switching in phase-shift modulated inverter is to use the modified inverter as reported in [9], This is a rather complicated circuit when compared with a standard full-bridge inverter (with four switches with anti-parallel diodes). The extra components include 8 diodes and eight inductors. The authors of this reference claim that their circuit can achieve ZCS for a wide operating region (i.e., not full operating region). It is understood that this reference shows the quasi-resonant circuit cannot achieve soft switching for the full phase-shift angular range and hard switching occurs when the phase-shift angle exceeds 120 degrees. Industrial control integrated circuits for full ZVS of phase-shift inverter are available [10], but it requires coordinated control of the transmitter and receiver circuits.

Phase-shift control is commonly used in WPT systems as reflected in recent publications [11]-[18], In [11], the effects of the dead time on the harmonics were examined. Phase-shift control was used for power and signal transfer in [12] and balancing currents in three-phase WPT systems in [13], Phase-shift control is also used on the active rectifier on the receiver side of the WPT systems [14], Phase shift control for soft switching for a wide operating range [15] and improving efficiency at light load [16] has been reported. Other WPT control schemes for parameter estimation and maximum efficiency tracking based on phase-shift inverters can be found in [17] and [18], However, soft switching of phase-shift inverter for full operating range of phase-shift angle from 0° and 180° is difficult to achieve without communication and coordinated control between the transmitter (Tx) and receiver (Rx) circuits. Hard-Switching of Known WPT Systems with Phase Shift Control

A. Known SS-Compensated WPT Systems

The schematic diagram of a known SS-compensated WPT system is depicted in Fig. 1. The de voltage l/dc is converted to a high-frequency ac voltage v _p by a full-bridge inverter. The power is transmitted via the SS-compensated resonators. l _p and L _s are the self-inductance of the transmitting and receiving coils, respectively. M is the mutual inductance between the two coils. R _p and R _s are the equivalent series resistances (ESRs) of the resonators. The compensated capacitors C _p and C _s are designed in resonance with the self-inductances of the coils, such that the switching frequency and the resonant frequencies of the resonators are equal as where co is the switching angular frequency of the inverter. For the resonators, according to the Kirchoff's circuit laws, where / _pi and i _sl are the fundamental components of transmitter and receiver currents, and v _si is the fundamental component of the output voltage of the receiving resonator. By substituting (1) into (2.1) and (2.2) to eliminate l _p , C _p , L _s , and C _s ,

According to (3.1), the receiver current i _si can be regulated by the fundamental component of the input voltage of the transmitting resonator (i.e., v _p i). The diode-bridge rectifier converts the receiver current to / _re c, the harmonics of which is filtered by the shunt capacitor Ct, such that a de current lb can charge the battery load. The charging current has a linear relationship with the amplitude of v _pi (i.e., l/ _p i) . A larger l/ _pi results in a larger lb. According to (3.2), Vsi can be regulated by the transmitter current / _p i. The diode-bridge rectifier converts v _si to the charging voltage 14, which has a linear relationship with the amplitude of / _pi (i.e., /pi). A larger / _p results in a larger 14. Therefore, the battery charging current and charging voltage can be regulated by the outputs of the primary-side inverter [19], Here, both the battery charging current and output voltage are fed back into the phase shift controller to regulate the primary-side inverter. The schematic waveforms of the switching signals, i.e., Si, S2, S3, and S4, are plotted as shown in Fig. 2. The switching signals of each bridge leg are complementary and with the duty ratio of 0.5. A phase shift angle between the diagonal switching signals (i.e., a) is controlled by the primary-side controller. In Fig. 2, Si and S ₂ are the leading signals with respect to S ₄ and S ₃ . Thus, <X>i and (P2 can be considered as the leading bridge leg, while (P3 and On can be considered as the lagging bridge leg. Based on the sketchy waveforms (without considering the deadtime such that switching signals are complementary for one bridge leg), \Z _pi and / _pi can be calculated based on 14c and / _dc using Fourier analysis as:

The phase shift angle can be controlled for V _p and / _p regulations, such that the charging current and voltage can track the references during the constant current (CC) and constant voltage (CV) charging modes.

The control block diagram of the primary-side CC and CV charging control based on the phase shift control is depicted, as shown in Fig. 3. The battery output voltage 14 is compared to a threshold voltage l/ _vai to determine whether the WPT system operates in the CC or CV mode. Generally, the threshold voltage can be set as the as the reference voltage I4ref- If 14 is less than t/ _va i, the output is 0 such that the phase shift angle is derived by the current controller (i.e., Controlled). The charging current 4 is controlled to track the current reference /bref. The WPT system operates in the CC charging mode. On the contrary, when 14 is greater than V _va i, the output is 1 such that the phase shift angle is derived by the voltage controller (i.e., Controllerl). The charging voltage 14 is controlled to track the voltage reference I4ret. According to (3) and (4), both Controllerl and Controlled can be linear controllers (e.g., proportional-integral (PI) controllers).

B. Operating Principles of the Known Full-Bridge Inverter with Phase Shift Control Without losing generality, the equivalent impedance Zin of the resonators and nonlinear loads can be modelled as a pure resistor when the harmonics of the resonator currents are small [20], Thus, the transmitter current i _p is in phase with the input voltage of the transmitting resonator v _p . For WPT systems with light load conditions, the phase shift angle of the controller is generally large. Typical waveforms of i _p and v _p for a large phase shift angle are plotted, as shown in Fig. 2. During each full operating cycle of v _p from ti to ti ₃ , the waveform of v _p comprises eight steady states (SS), i.e., SSI: < t < t ₂ , SS2: t ₃ < t < t ₄ , SS3: t ₅ < t < t ₆ , SS4: t ₆ < t < t ₇ , SS5: t ₇ < t < t _e , SS6: t ₉ < t < t ₁₀ , SS7: t ₄₁ < t < t ₁₂ , and SS8: t ₁₂ < t < t ₁₃ , and four transient states (TS), i.e., TS1: t ₂ < t < t ₃ , TS2: t ₄ < t < t ₅ TS3: t ₈ < t < tg, and TS4: t ₁₀ < t < t ₄₁ . The equivalent circuits of the full-bridge inverter with phase shift control during the twelve states are shown in Fig. 4. Here, the parasitic capacitances (i.e., Ci, C ₂ , C ₃ , and C ₄ ) and diodes (i.e., Di, D ₂ , D ₃ , and D ₄ ) of the four power switches (i.e., Oi, 0 ₂ , 0 ₃ , and 0 ₄ ) are assumed to be identical, although it will be appreciated that, in practice, there may be some minor discrepancies in parameters due to manufacturing tolerances.

Turning now to Fig. 4. the principles of operation of the power inverter in equivalent circuits of a known WPT system during one cycle will now be described. In the following discussion paragraph references - e.g. (a), (b), etc. - refer to the corresponding one of the individual circuit diagrams.

(a) At ti, the switch (Z> ₃ is turned off, while the switch <X>i maintains the on-state and the switches (Z> ₂ and (Z> ₄ maintain off-state. The voltages across the parasitic capacitors C ₂ and C ₄ are l/dc, while the voltages across the parasitic capacitors G and G are 0. Due to the voltage cross the capacitor G is l/dc, the diode D ₃ is conducted. During the SSI (t ₄ < t < t ₂ ), The transmitter current is continuous to be positive (i.e., / _p >0).

(b) At t ₂ , the switch (Z> ₄ is turned on, while the switch (Di maintains the on-state and the switches (Z> ₂ and (Z> ₃ maintain off-state. During the TS1 (t ₂ < t < t ₃ ), The parasitic capacitor G is charged, while the parasitic capacitor G is discharged. Due to the existence of voltage across the capacitor G (i.e., l/d _s4 >0), the switch (Z> ₄ is turned on with hard switching. During this period, the inverter current is still positive (i.e., / _p >0). (c) At t3, the parasitic capacitor G is fully discharged and the parasitic capacitor C3 is fully charged. The switches (Di and 04 are on-state, while the switches 0 ₂ and 03 are off- state. During the SS2 (t ₃ < t < t ₄ ), the voltages across the capacitors G and C ₄ are 0, while the voltages across the capacitors C ₂ and C ₃ are l/dc- The transmitter current remains positive (i.e., / _p >0).

(d) At t ₄ , the switch 0i is turned off, while the switch 0 ₄ maintains on-state and the switches 0 ₂ and 0 ₃ maintain off-state. The voltages across the parasitic capacitors C ₃ and C ₄ remains unchanged, while the parasitic capacitor G is charged and the parasitic capacitor G is discharged. During the TS2 (t ₄ < t < t ₅ ), the capacitor G is charged from 0 to l/dc, while the capacitor G is discharged from l/dc to 0. The transmitter current remains positive (i.e., / _p >0).

(e) At ts, the parasitic capacitor G is fully discharged and the parasitic capacitor Ci is fully charged. Thus, the diode D ₂ is conducted. During the SS3 (t ₅ < t < t ₆ ), the switch 04 remains on-state, while the switches 0i, 0 ₂ , and 0 ₃ are off-state. The transmitter current is positive (i.e., / _p >0).

(f) At t ₆ , the switch 0 ₂ is turned on. The voltages across the parasitic capacitors G and G are l/dc, while the voltages across the parasitic capacitors G and G are 0. Therefore, the switch 0 ₂ is turned on with ZVS. During the SS4 (t ₆ < t < t ₇ ), the switches 0 ₂ and 0 ₄ are on-state, while the switches 0 ₂ and 0 ₃ are off-state. The transmitter current is positive (i.e., / _p >0) during the first half period and negative (i.e., / _p <0) during the second half period.

(g) At t ₇ , the switch 0 ₄ is turned off. The switch 0 ₂ remains on-state, while the switches 0i and 03 remain off-state. The voltage across the parasitic capacitor G is 0 and the transmitter current is negative (i.e., / _p <0). Hence, the diode D ₄ is conducted during the SS5 (t ₇ < t < t ₈ ).

(h) At ts, the switch 03 is turned on. The switch 0 ₂ remains on-state, while the switches 0i and 03 remain off-state. The voltages across the parasitic capacitors G and G are l/dc, while the voltages cross the parasitic capacitors G and G are 0. During the TS3 (t ₈ < t ₉ ), the capacitor G is discharged, while the capacitor C4 is charged. Due to the existence of voltage across the capacitor C3 (i.e., l/ds3>0), @3 is turned on with hard switching. The transmitter current is still negative

(i) At tg, the capacitor C3 is fully discharged and the capacitor C4 is fully charged. Hence, the voltages across the parasitic capacitors Ci and C4 are l/dc, while the voltages across the parasitic capacitors C ₂ and C ₃ are 0 at this moment. During the SS6 (t ₉ < t < t ₁₀ ), the switches @2 and (D3 are on-state, while the switches <X>i and (Du are off-state. The transmitter current remains negative

(j) At tio, the switch (D ₂ is turned off, while the switch (D3 maintains on-state and the switches <X>i and (Du are still off-state. The voltages across the parasitic capacitors C ₃ and C ₄ remain unchanged, while the capacitor Ci is discharged and the capacitor C ₂ is charged. During th he capacitor Ci is discharged from l/dc to 0, while the capacitor C ₂ is charged from 0 to l/dc The transmitter current is still negative (i.e., / _p <0).

(k) At tu, the parasitic capacitor C ₂ is fully charged and the parasitic capacitor Ci is fully discharged. Thus, the diode Di is conducted. During the SS7 (tn < t < t ₁₂ ), the switch 03 is still on-state, while the switches <X>i, <Z> ₂ , and (Du are off-state. The transmitter current is still negative (i.e., / _p <0).

(l) At ti ₂ , the switch (Di is turned on. The voltages across the parasitic capacitors C ₂ and C4 are l/dc, while the voltages across the parasitic capacitors Ci and C3 are 0. Therefore, (Di is turned on with ZVS. During the SS8 (t ₁₂ < t < t ₁₃ ), the switches <X>i and (D3 are on-state, while the switches (Z> ₂ and (Du are off-state. The transmitter current is negative (i.e., / _p <0) during the first half period and positive (i.e., / _p >0) during the second half period.

It can be seen from the analysis that ZVS can be naturally achieved by the leading bridge legs of the inverter with the known phase shift control, whereas hard switching occurs on the switches of the lagging bridge leg during the transient periods TS1 (t ₂ < t < t ₃ ) and TS3 (t ₈ < t < t ₉ ). As a result, the EMI emission of the full-bridge inverter could be high, especially the conducted EMI from 150 kHz to 30 MHz, which may violate the EMC standard EN55022.

Summary

Aspects of the invention are as set out in the independent claims. Some optional features are defined in the dependent claims.

Implementation of the techniques disclosed herein may provide significant technical advantages. For instance, as will be demonstrated below, zero-voltage switching (ZVS) can be achieved to enable airfares-shift modulator power inverter to enable all power switches to be soft-switched for all operating regions, including in the lagging bridge leg. Consequently, the power inverter can be operated with reduced switching power loss and attenuated electromagnetic interference. Thus, the converter can operate with a higher frequency while the EMI is still within the required boundaries.

In one arrangement, an "augmented passive circuit" comprises two diodes, two capacitors, and one inductor for a full-bridge inverter with known phase-shift control in wireless power transfer (WPT) systems. The operation may achieve soft switching and reduce the EMI radiation for a wide range of phase shift angles, up to the full range of phase shift angle from 0° to 180°. Such full-range ZVS operation may attained without any communication and/or coordinated control with the receiver circuit. Both simulation and experimental results show that ZVS can be achieved by the augmented circuit for a WPT system in both constant current (CC) and constant voltage (CV) control modes. Practical EMI tests demonstrate that the augmented circuit can mitigate the conducted EMI of the full-bridge inverter to meet the standard EN55022 with a full range of phase-shift angle from 0° to 180°. The proposed augmented circuit so adds soft-switching feature to a phase-shift inverter regardless of the types of resonant circuits in the WPT systems, therefore making it flexible for the inverter to drive different type of WPT systems in existing wireless charging standards.

Existing methods require more circuit components and cannot achieve soft switching for the entire operating range of the phase-shift-modulated inverter. The techniques disclosed herein have at least the following advantages: • fewer circuit components than existing methods, with reduced cost.

• There is no active power switch and therefore does not need extra gate drive circuit for power switch.

• The augmented passive circuit can be added to existing phase-shift modulated power inverter.

• The augmented passive circuit enables a phase-shift modulated power inverter to achieve soft switching (through zero-voltage switching) for the entire operating range.

An augmented passive circuit (with connections shown in Fig. 5) comprises two diodes, two capacitors and one inductor for achieving soft switching in all the power switches in a power inverter under phase-shift modulation control.

The augmented passive circuit can be added to a power inverter to achieve soft switching under either fixed-frequency or variable-frequency operations of power inverter.

The augmented passive circuit can reduce the switching power stress and power losses to improve the lifetime and conversion efficiency of power inverters.

The augmented passive circuit can be used to modify existing designs of wireless power transfer systems compliant with the standards of the Wireless Power Consortium and Society of Automotive Engineers without changing the control algorithms.

A design method for the augmented passive circuit is also herein disclosed, based on the equations (25) to (27) set forth below.

Power inverters are widely used for a large range of modern commercial applications such as switched mode power supplies, battery chargers and wireless charging systems with markets in tens of billions of US dollars. The techniques can be applied to a wide variety of applications, but are particularly useful in wireless charging, including with mobile phones and mobile robotics such as robotic lawn mowers and robotic vacuum cleaners Brief Description of the Drawings

The invention will now be described, by way of example only, and with reference to the accompanying drawings in which:

Fig. 1 is a schematic diagram of a typical SS-compensated WPT system;

Fig. 2 is a voltage- and current-time diagram illustrating schematic waveforms of the switching signals of a known power inverter for a WPT system;

Fig. 3 is a control block diagram of known phase shift control for WPT systems in achieving CC and CV charging as described in [19];

Fig. 4 is a series of equivalent circuit diagrams illustrating a cycle of operation of a power inverter of a known WPT system;

Fig. 5 is a circuit diagram of a power inverter implementing an exemplary passive augmented circuit in accordance with the techniques described herein;

Fig. 6 is a voltage- and current-time diagram illustrating schematic waveforms of the switching signals of a power inverter for a WPT system implementing an exemplary passive augmented circuit in accordance with the techniques described herein;

Fig. 7 is a series of equivalent circuit diagrams illustrating a cycle of operation of a power inverter implementing an augmented passive circuit in accordance with the techniques described herein;

Fig. 8 illustrates waveforms of lb, /bref, ip, v _p , and switching signals of the WPT system (a) without the augmented circuit, and (b) with the augmented circuit in a simulation case 1; Fig. 9 illustrates waveforms of drain currents and drain-to-source voltages of the four switches of the WPT system (a) without the augmented circuit and (b) with the augmented circuit in the simulation case 1;

Fig. 10 illustrates I s-/d curves of the four switches of the WPT system without and with the augmented circuit in case 1;

Fig. 11 illustrates waveforms of 14, 1 ref, ip, v _p , and switching signals of the WPT system (a) without the augmented circuit, and (b) with the augmented circuit in case 2;

Fig. 12 illustrates waveforms of drain currents and drain-to-source voltages of the four switches of the WPT system (a) without the augmented circuit and (b) with the augmented circuit in case 2;

Fig. 13 illustrates I s-/d curves of the four switches of the WPT system without and with the augmented circuit in case 2; Fig. 14 illustrates waveforms of Vds3, i<i3, ip, and v _p of WPT systems (a) without augmented circuit and (b) with augmented circuit for the current control;

Fig. 15 illustrates conducted EMI from full-bridge inverter (a) without augmented circuit and (b) with augmented circuit for the current control;

Fig. 16 illustrates magnified waveforms of Vds3 and /d3 of WPT systems (a) without augmented circuit and (b) with augmented circuit for the voltage control;

Fig. 17 illustrates conducted EMI from full-bridge inverter (a) without augmented circuit and (b) with augmented circuit for the voltage control;

Fig. 18 illustrates conducted EMI from full-bridge inverter without and with the augmented circuit when the phase shift angle is controlled at 120°, 90°, 60°, 30°, and 0°;

Fig. 19 illustrates background EMIs of the test chamber; and

Fig. 20 illustrates waveforms of Vds3, te, ip, and v _p of the WPT system with and without the augmented circuit for different phase shift angles.

Detailed Description

The circuit diagram of a power inverter implementing an exemplary augmented passive circuit in accordance with the techniques herein disclosed is depicted as shown in Fig. 5. In this, the proposed augmented passive circuit comprises an inductor IA, two diodes DAI and DA2, and two parallel-connected capacitors C _Ai and C _A 2- The circuit is termed an "augmented passive circuit" in as much as it is "passive" by not requiring any active switching components. The circuit "augments" a known phase-shift modulated full-bridge power inverter. In the example of Fig. 5, power inverter 500 is manufactured complete with the augmented passive circuit, however the augmented passive circuit may also be fitted (e.g. retro-fitted) to existing power inverters of known design.

As shown in Fig. 5, the phase-shift modulated full-bridge power inverter 500 comprises a leading bridge leg 502 comprising: a first power switch (Di, the first power switch having a first power switch parasitic capacitance Cr, and a second power switch 02, the second power switch having a second power switch parasitic capacitance C ₂ . The first and second power switches 0i and 0 ₂ are connected in series with one another at leading bridge leg connection point A of leading bridge leg 502. Power inverter 500 further comprises a lagging bridge leg 504 comprising: a third power switch 0 ₃ , the third power switch having a third power switch parasitic capacitance C ₃ ; and a fourth power switch 0 ₄ , the fourth power switch having a fourth power switch parasitic capacitance C . The third and fourth power switches CDs and O are connected in series with one another at lagging bridge leg connection point B of lagging bridge leg 504.

Exemplary types of power switches include, as noted above, MOSFETs and IGBTs.

In the example of Fig. 5, power inverter 500 comprises a capacitor circuit branch 506 comprising first augmented circuit capacitor C _i and second augmented circuit capacitor C _A 2 connected in series with one another at capacitor branch connection point Xi. Capacitor circuit branch 506 is connected in parallel with the leading bridge leg 502 and lagging bridge leg 504. Continuing in this example, the power inverter 500 comprises a diode circuit branch 508 comprising first augmented circuit diode D I and second augmented circuit diode D _A2 connected in series with one another at diode branch connection point X ₂ . Diode circuit branch 508 is connected in parallel with the leading bridge leg 502 and lagging bridge leg 504. In this example, capacitor circuit branch connection point Xi and diode circuit branch connection point X ₂ are electrically connected with one another.

Leading bridge leg connection point A is connected to a first output terminal 510 of the power inverter for connection to a load Z, in this case a wireless power transfer charging load. Lagging bridge leg connection point B is connected to a second output terminal 512 of the power inverter for connection to the load Z. In operation, a load voltage V _p is developed across the load Z and a load current i _p flows through load Z.

Power inverter 500 further comprises augmented circuit inductor L _A connected on a first side (at a first inductor terminal) to the capacitor branch connection point Xi and the diode branch connection point X ₂ . Inductor L _A is also connected on a second side (at the second inductor terminal) to one of the first and second output terminals 510, 512.

Together, augmented circuit inductor L _A , capacitor circuit branch 506 and diode circuit branch 508 together form an augmented passive circuit which operate to reduce or even remove discontinuous current which occurs, particularly when the phase-shift angle is large. In turn, this achieves soft-switching and reduces (or even removes) power loss and electromagnetic interference (EMI) arising from the switching of power switches. The schematic waveforms of the switching signals, / _p and v _p of the WPT system with the augmented circuit are plotted as shown in Fig. 6. During each cycle (i.e., from ti to ti ₃ ), the waveform of v _p comprises eight steady states (SS), i.e., SSI: t ₂ < t < t ₃ , SS2: t ₃ < t < t ₄ , SS3: t ₅ < t < t ₆ , SS4: t ₆ < t < t ₇ , SS5: t ₈ < t < t ₉ , SS6: t ₉ < t < t ₁₀ , SS7: t ₄₁ < t < t ₁₂ , and SS8: t ₁₂ < t < t ₁₃ , and four transient states (TS), i.e., TS1: t ₄ < t < t ₂ , TS2: t ₄ < t < t ₅ , TS3: t ₇ < t < t _s , TS4: t ₁₀ < t < t ₄₁ . The equivalent circuits during one cycle of operation are depicted, as shown in Fig. 7. In the following discussion paragraph references - e.g. (a), (b), etc. - refer to the corresponding one of the individual circuit diagrams.

(a) At ti, the switch 0 ₃ is turned off, while the switch 0i is kept on-state and the switches 02 and 04 are kept off-state. The transmitter current is positive (i.e., / _p >0). The voltages across the parasitic capacitors C ₂ and C ₄ are l/dc, while the voltages across the parasitic capacitors Ci and C ₃ are 0. During the TS1 (t ₄ < t < t ₂ ), the capacitor C ₃ is charged and the capacitor C ₄ is discharged. The augmented inductor 1A and the parasitic capacitors C ₃ and C ₄ can form an LC resonator, such that the energy stored in the parasitic capacitor C ₄ can be released before the switch 0 ₄ is turned on.

So, it will be appreciated that Figs. 5 and 6 and associated text illustrate and describe a phase-shift modulated full-bridge power inverter 500 configured for use in a wireless power transfer system, the power inverter 500 comprising: a leading bridge leg 502 comprising: a first power switch <2>i, the first power switch <2>i having a first power switch parasitic capacitance C ₂ ; and a second power switch ® ₂ , the second power switch having a second power switch parasitic capacitance C ₂ ; a lagging bridge leg 504 comprising: a third power switch ® ₃ , the third power switch having a third power switch parasitic capacitance C ₃ ; and a fourth power switch ® ₄ , the fourth power switch ® ₄ having a fourth power switch parasitic capacitance C ₄ ; wherein the power inverter 500 is configured for each of the power switches to be switched on and off in a switching cycle; and wherein the power inverter further comprises: an augmented passive circuit comprising an inductor L _A , wherein the power inverter 500 is configured for the inductor L _A to combine with the third power switch parasitic capacitance C ₃ and the fourth power switch capacitance C ₄ to form a resonator when a first one of the third and fourth power switches <t> ₃ , $4 (in this step (a), this is the third power switch <2> ₃ ) is switched off and a second one of the third and fourth power switches <P ₃ , <P ₄ (in this step (a), this is the fourth power switch $4) is in a switched off state, and for energy stored in the parasitic capacitance of the second one of the third and fourth power switches (in this step (a), this is C ₄ of $4) to be discharged before the second one of the third and fourth power switches (in this step (a), this is <P ₄ ) is switched on.

A corresponding method is also described.

The significance of this discharge of the energy stored in the parasitic capacitor C4 will become evident from step (c) below. The discharge/release of the parasitic capacitor C ₄ energy can be full or partial discharge.

According to the resonant circuit, the current flowing through the augmented inductor, and the voltages across the capacitors C ₃ and C ₄ can be expressed as

Here, the transmitter current is mainly determined by the resonators of the WPT system, which will not affect the amplitudes and frequency of the augmented inductor current and the voltages across the capacitors. Besides, the amplitude of the augmented inductor current is determined by the previous state of the system circuit due to its continuity. The TS1 period can be calculated based on (6) or (7) as

(b) At t2, the parasitic capacitor C ₃ is fully charged and the parasitic capacitor C ₄ is fully discharged. The switch <X>i is turned on, while the switches @2, <I>3, and (Z> ₄ are turned off. The augmented inductor current can be calculated by substituting (8) into (5), as During the SSI (t ₂ < t < t ₃ ), both the transmitter current and augmented inductor current are positive (i.e., / _p >0 and /LA>0).

(c) At t ₃ , the switch 0 ₄ is turned on. The switch 0i is kept on-state and the switches 0 ₂ and 03 are kept off-state. The transmitter current is still positive (i.e., / _p >0). During the SS2 (t ₃ < t < t ₄ ), the augmented inductor current is decreased when the DC source is connected, as

Since the voltage across the capacitor C ₄ is zero, 0 ₄ is turned on with ZVS. Thus, the incorporation of the augmented passive circuit into power inverter 500 is significant in reducing or even removing the undesirable power loss and EMI from the power switch present in the prior art.

(d) At t ₄ , the switch <X>i is turned off. The switch 04 is kept on-state and the switches 0 ₂ and 03 are kept off-state. The voltages across the parasitic capacitors Ci and C ₄ are 0, while the voltages across the parasitic capacitors C ₂ and C3 are l/dc. The transmitter current is still positive (i.e., / _p >0). During the TS2 (t ₄ < t < t ₅ ), the augmented inductor current is further decreased based on (10). By assuming the transmitter current to be

/p sin(r<j t + 0), the voltages across the parasitic capacitors Ci and C ₂ can be expressed as (wt + 0) (11) v _C2 (t) = Ide ( ¹² >

Then, the TS2 period can be calculated by

(e) At t ₅ , since C ₂ is fully discharged, the diode D ₂ is conducted. During the SS3 (t ₅ < t < t ₆ ), the transmitter current is still positive (i.e., / _p >0) and the augmented inductor current is further decreased based on (10). (f) At te, the switch (Di is turned on, while the switch (Dt, is kept on-state and the switches ( i and (Ds are kept off-state. Since the voltage across the capacitor Ci is zero, (Di is turned on with ZVS. During the SS4 (t ₆ < t < t ₇ ), the transmitter current is positive during the first half period, while it is negative during the second half period. The augmented inductor current is further decreased based on (10). When the inductor current is reduced to 0, the diode DAI is blocked. The inductor current becomes negative, which is the sum of the augmented capacitor currents (i.e., / _L A ⁼ ^CAI + /CAZ), as shown in Fig. 7(f2). When the augmented capacitor C _Ai is fully charged and the augmented capacitor C _A2 is fully discharged, the diode D _A2 is conducted and the augment inductor is kept unchanged at the minimum value as

Thus, summarising at this juncture, the augmented passive circuit further comprises a diode circuit branch 508, the diode circuit branch comprising a first diode D _A I and a second diode D _A2 connected in series with one another, the diode circuit branch 508 being connected in parallel to the leading bridge leg 502 and the lagging bridge leg 504, the power inverter 500 being configured for, when a first one of the first and second power switches (in this step (f), this is (Di) is switched on and a second one of the first and second power switches (in this step (f), this is (Di) is in a switched off state, the first one of the third and fourth power switches (in this step (f), this is (Ds) is in a switched off state and a second one of the third and fourth power switches (in this step (f), this is <Z> ₄ ) is in a switched on state, , for a first one of the first and second diodes (in this step (f), this is D _Ai ) to be in a conductive state and a second one of the first and second diodes (in this step (f), this is D _A2 ) to be in a non- conductive state; and wherein the power inverter 500 is configured for current in the inductor L _A to become zero, and for the first one of the first and second diodes (in this step (f), this is DAI) to be switched to a non-conductive state.

Further summarising, the augmented passive circuit further comprises a capacitor circuit branch 506, the capacitor circuit branch 506 comprising a first capacitor CAI and a second capacitor CA2 connected in series with one another, the capacitor circuit branch 506 being connected in parallel to the leading bridge leg 502 and the lagging bridge leg 504, the power inverter 500 being configured for a magnitude of the current in the inductor LA to increase (in this step (f), the inductor current becomes negative after having been zero), for a first one of the first capacitor and the second capacitor (in this step (f), this is C _A i) to be fully charged and for a second one of the first capacitor and the second capacitor to be fully discharged (in this step (f), this is C _A2 ), and for the second one of the first and second diodes (in this step (f), this is D _A2 ) to be switched to a conductive state.

(g) At tj, the switch 0 ₄ is turned off, while the switch 0 ₂ is kept on-state and the switches 0i and 03 are kept off-state. The transmitter current is negative (i.e., / _p <0). The voltage across the parasitic capacitors Ci and C ₃ are l/dc, while the voltages across the parasitic capacitors C ₂ and C ₄ are 0. During the TS3 (t ₇ < t < t ₈ ), the capacitor C ₃ is discharged and the capacitor C ₄ is charged. The augmented inductor 1 _A and the parasitic capacitors C ₃ and C ₄ can form an LC resonator, such that the energy stored in the parasitic capacitor C ₃ can be released before the switch 0 ₃ is turned on. The current flowing through the augmented inductor, and the voltages across the capacitors C ₃ and C ₄ can be expressed

The TS3 period can be calculated based on (16) or (17) as

Thus, in this step the augmented passive circuit again operates where the power inverter 500 is configured for the inductor LA to combine with the third power switch parasitic capacitance C ₃ and the fourth power switch capacitance C ₄ to form a resonator, but the switching arrangement is the reverse of that described above in step (a), viz: when a first one of the third and fourth power switches 0 ₃ , 0 ₄ (in this step (g), this is now the fourth power switch 0 ₄ ) is switched off and a second one of the third and fourth power switches 0 ₃ , 0 ₄ (now, in this step (g), the third power switch 0 ₃ J is in a switched off state, and for energy stored in the parasitic capacitance of the second one of the third and fourth power switches (in this step (g), this is C3 of (D3) to be discharged before the second one of the third and fourth power switches (in this step (g), this is <Z> ₃ ) is switched on.

(h) At t _B , the parasitic capacitor C ₄ is fully charged and the parasitic capacitor C ₃ is fully discharged. The switch @2 is on-state, while the switches <X>i, <Z> ₃ , and (Du are off-state. The augmented inductor current can be calculated by substituting (18) into (15), as

During the SS5 (t ₈ < t < t ₉ ), both the transmitter current and augmented inductor current are negative (i.e., / _p <0 and /LA<0).

(i) At tg, the switch @3 is turned on. The switch Oh is kept on-state and the switches (Di and 04 are kept off-state. The transmitter current is still negative (i.e., / _p <0). During the SS6 (t ₉ < t < t ₁₀ ), the augmented inductor current is increased when the DC source is connected, as

Since the voltage across the capacitor C ₃ is zero, (D3 is turned on with ZVS.

(j) At tw, the switch Oh is turned off. The switch @3 is kept on-state and the switches (Di and

04 are kept off-state. The voltages across the parasitic capacitors C ₂ and C ₃ are 0, while the voltages across the parasitic capacitors Ci and Q are l/dc. The transmitter current is still negative (i.e., / _p <0). During the TS4 (t ₁₀ < t < the augmented inductor current is further increased based on (20). By assuming the transmitter current is he voltages across the capacitors Ci and C ₂ can be expressed as

Then, the TS4 period can be calculated as

(k) At tn, since Ci is fully discharged, the diode Di is conducted. During the SS7 (tn t ₁₂ ), the transmitter current is still negative and the augmented inductor current is further increased based on (20).

(I) At ti2, the switch (Z>i is turned on, while the switch (ZU is kept on-state and the switches (Z>2 and (Z>4 are kept off-state. Since the voltage across the capacitor Ci is zero, (Z>i is turned on with ZVS. During the SS8 (t ₁₂ < t < t ₁₃ ), the transmitter current is negative during the first half period, while it is positive during the second half period. The augmented inductor current is further increased based on (20). When the inductor current is increased to 0, the diode D _A2 is blocked. The inductor current becomes positive, which is the sum of the augmented capacitor currents (i.e., Z _LA = Z _CA1 + Z _CA2 ), as shown in Fig. 7(12). When the augmented capacitor C _Ai is fully discharged and the augmented capacitor C _A2 is fully charged, the diode D _A I is conducted and the augment inductor is kept unchanged at the maximum value as

Thus, summarising again at this juncture, it will be seen once more that the power inverter

500 is configured for, a first one of the first and second power switches (in this step (I), this is (Di) is switched on and a second one of the first and second power switches (in this step (I), this is (D2) is in a switched off state, the first one of the third and fourth power switches (in this step (I), this is (ZU) is in a switched off state and a second one of the third and fourth power switches (in this step (I), this is (ZU) is in a switched on state, for a first one of the first and second diodes (in this step (I), this is DA2) to be in a conductive state and a second one of the first and second diodes (in this step (I), this is DAI) to be in a non-conductive state; and wherein the power inverter 500 is configured for current in the inductor L _A to become zero, and for the first one of the first and second diodes (in this step (I), this is DM) to be switched to a non-conductive state. Further summarising, it will be seen once more that the power inverter 500 is configured for a magnitude of the current in the inductor LA to increase (in this step (I), the inductor current becomes positive after having been zero), for a first one of the first capacitor and the second capacitor (in this step (I), this is C 2) to be fully charged and for a second one of the first capacitor and the second capacitor to be fully discharged (in this step (I), this is CAI), and for the second one of the first and second diodes (in this step (I), this is D I) to be switched to a conductive state.

Obviously, the WPT system with the known phase shift control can implement ZVS for both bridge legs with the integration of the augmented circuit. As a result, the EMI emission, especially the conducted EMI can be reduced.

Assume that the augmented inductor current takes about switching cycle to increase from 0 to the maximum value (i.e., /max), such as

^2L _A C _A = J (25)

Then, the parameters of the augmented inductor and capacitors can be calculated based on (24) and (25) as

Therefore, a passive augmented circuit is disclosed that can turn a phase-shift power inverter into a fully soft-switched power inverter for the entire operating range (i.e. phaseshift angle from 0° to 180°. The proposed passive circuit has the following advantageous features:

• Independent of the compensation topologies of the transmitter (Tx) and receiver (Rx) circuits. For wireless power transfer systems, the leakage inductances of the transmitting and receiving coils require capacitive compensation. The compensation networks can be various types, i.e., series-series (capacitors in series for both Tx and Rx coils), series-parallel (the capacitor in series with Tx coil and the capacitor in parallel with Rx coil), LCC-LCC, and so on;

• No requirement for the regulations of firing angles of the power switches or switching frequencies based on in-band or out-of-band communication between the Tx and Rx circuits;

• It may be implemented for full load operating conductions including light- and no-load conditions;

• It may be implemented for constant frequency operation of the inverter output voltage.

The proposed circuit has been tested for the full range of phase-shift angle from 0° to 180°. Practical measurements of the circuit waveforms and electromagnetic radiation are included to confirm its feasibility to achieve soft switching in the full operating range.

As noted above, the augmented passive circuit can be fitted (for example, retrofitted) to a phase-shift modulated full-bridge power inverter configured for use in a wireless power transfer system. Thus, a method of fitting (retrofitting) comprises connecting a capacitor circuit branch 506 in parallel to the leading bridge leg 502 and the lagging bridge leg 504, the capacitor circuit branch comprising a first capacitor C _i and a second capacitor C _A 2 connected in series with one another at a capacitor branch connection point Xi; connecting a diode circuit branch 508 in parallel to the leading bridge leg 502 and the lagging bridge leg 504, the diode circuit branch 508 comprising a first diode D I and a second diode D I connected in series with one another at a diode branch connection point X2; and connecting an inductor L _A at a first inductor terminal to the capacitor branch connection point Xi and the diode branch connection point X ₂ and connecting the inductor L _A at a second inductor terminal to one of the first and second output terminals 510, 512.

Components for the augmented passive circuit may be provided in the form of a kit of parts for fitting to a phase-shift modulated full-bridge power inverter configured for use any wireless power transfer system. Thus, a kit of augmented passive circuit parts for fitting to a phase-shift modulated full-bridge power inverter 500 configured for use in a wireless power transfer system, comprises: a first capacitor C _i and a second capacitor C _A2 to be connected in series with one another at a capacitor branch connection point Xi in a capacitor circuit branch 506, the capacitor circuit branch 506 to be connected in parallel to a leading bridge leg 502 and a lagging bridge leg 504 of the power inverter; a first diode DAI and a second diode DA2 to be connected in series with one another at a diode branch connection point X2 in a diode circuit branch 508 , the diode circuit branch 508 to be connected in parallel to the leading bridge leg 502 and the lagging bridge leg 504; and an inductor L to be connected at a first inductor terminal to the capacitor branch connection point Xi and the diode branch connection point X ₂ and to be connected at a second inductor terminal to one of power inverter first and second output terminals 510, 512.

Simulation Results

Simulations are carried out on a WPT system (schematic diagram as shown in Fig. 1) with the parameters given in Table 1 using PsimlO.O. The battery load is modelled as a pure resistive load RL without losing generality. The switching frequency is 100 kHz. The deadtime of the switching signal is 0.1 ^s. PI controllers are adopted for both current and voltage control.

The parameters of the current controller are / PI=1 and Xii=100000 and the parameters of the voltage controller are /CRV=0.1 and Km= 10000. The output current and voltage references are /bref=l-675A and Vbref=4.2V. Two cases are investigated in simulation. In case 1, the output current is controlled to track the current reference with the phase shift angle being greater than 120°. In case 2, the output voltage is controlled to track the voltage reference with the phase shift angle being greater than 165°, which means the on-pulse width of the input voltage of the transmitter (i.e., v _p ) is less than 15°. TABLE 1. Main Parameters of WPT System in Simulation

For case 1, the waveforms of the output current (i.e., lb), output current reference (i.e., /bret), transmitter current (i.e., / _p ), input voltage of the transmitting resonator (i.e., v _p ), and the four switching signals (i.e., Si, S ₂ , S ₃ , and S ₄ ) of the WPT system without the augmented circuit (known WPT system) and with the augmented circuit are shown in Fig. 8. Both output currents are well-regulated to track the current reference (i.e., /bref=l-675 A), and the transmitter currents are in phase with the input voltages of the transmitting resonators. The phase shift angles between the diagonal switching signals are controlled at 131.8° and 129.2° for the WPT systems without the augmented circuit and with the augmented circuit, respectively.

The waveforms of corresponding drain currents (i.e., 41, IM, IM, and IM) and drain-to-source voltages (i.e., l/dsi, 'AM, l/ds ₃ , and l/ds ₄ ) of the four switches are shown in Fig. 9. The four transient periods are labelled as TS _A I, TS _A2 , TS _A3 , and TS _A4 for the WPT system without the augmented circuit, and the transient periods are labelled as TS _B I, TS _B2 , TS _B3 , and TS _B4 for the WPT system with the augmented circuit. Apparently, hard switching occurs on the lagging bridge leg (i.e., (Z> ₃ and (Z> ₄ ) of the WPT system without the augmented circuit during TS _A I and TS _A3 , respectively. However, ZVS can be implemented for all the four switches of the WPT system with the augmented circuit.

The corresponding Vd _S -ld curves of the switches of the WPT system without and with the augmented circuit are plotted, as shown in Fig. 10. It is clear to observe that the enclosed areas of 0 ₃ and 0 ₄ of the WPT system with the augmented circuit are significantly shrunk. The hard-switching issue of 0 ₃ and 0 ₄ for the known WPT system with phase shift control is addressed by incorporating the augmented circuit.

For case 2, the waveforms of the output voltage (i.e., 14), output voltage reference (i.e., l/bret), transmitter current (i.e., / _p ), input voltage of the transmitting resonator (i.e., v _p ), and the four switching signals (i.e., Si, S ₂ , S ₃ , and S ₄ ) of the WPT system without the augmented circuit (known WPT system) and with the augmented circuit are shown in Fig. 11. He output voltages are regulated to track the reference (i.e., I4ret=4.2 V). The phase shift angle between the diagonal switching signals is controlled at 165.4° and 169.2° for the WPT system without and with the augmented circuit, respectively.

The corresponding l/ds-/d curves of the switches of the WPT system without and with the augmented circuit are plotted, are shown in Fig. 12. Similar to the results of case 1, hard switching occurs on the lagging bridge leg of the WPT system without the augmented circuit, while ZVS are implemented for all the switches of the WPT system with the augmented circuit.

The l/ds-/d curves of the switches of the WPT system without and with the augmented circuit are also plotted, as shown in Fig. 13. Similar to the results of case 1, the enclosed areas of 0 ₃ and 04 of the WPT system with the augmented circuit are significantly shrunk.

Experimental Verification

Experiments are conducted on a WPT system with the same parameters, as given in Table 1. The frequency and deadtime of the switching signals of the full-bridge inverter are also identical to those being used in the simulation. The MOSFETs of the full-bridge inverter is Infineon's IRFP250M. Rogowski coils are adopted to measure the drain currents of the four DIP MOSFETs. The conducted EMI of the full-bridge inverter are measured by Advantest's spectrum analyzer R3261C. Background EMIs of the EMC chamber are shown in "Further Data, Section A" below. RIGOL's DP832 is adopted as the DC power supply for the WPT system. The controller is implemented using Texas Instrument (Tl)'s digital signal processor (DSP) TMS320F28335. The parameters of the current controller are K _P! =0.00001 and Ku=0.1 and the parameters of the voltage controller are /<PV=0.00001 and /<,v= 10000. The output current and voltage references are also /bref=l-675A and l/bref=4.2V. In experiment, both CC and CV control are studied.

First, the output current of the WPT system (i.e., /b) is controlled to track the reference (i.e., /bret) at 1.675 A. The waveforms of drain-to-source voltages and drain currents of the switch 03 (i.e., Vd _S 3 and i^), transmitter currents (i.e., / _p ), and input voltages of the transmitting resonators (i.e., v _p ) for the WPT system without and with the augmented circuit are shown in Fig. 16. The phase shift angles are controlled at 148.6° for the WPT system without the augmented circuit and at 148.2° for the WPT system with the augmented circuit. The waveforms in Figs. 14(a2) and (b2) are magnified from the waveforms in Figs. 14(al) and (bl), respectively. The waveforms in Figs. 14(a3) and (b3) are magnified from the waveforms in Figs. 14(a2) and (b2), respectively. The waveforms of Vds3 and in Fig. 14(a3) show that hard switching occurs for the known WPT system without the augmented circuit. However, ZVS can be achieved when the augmented circuit is integrated into the full-bridge inverter, as shown in Fig. 14(b3). Comparisons of conducted EMI from 150 kHz to 30 MHz between the full-bridge inverter without and with the augmented circuit are shown in Fig. 15. Apparently, the conducted EMI of the full-bridge inverter without the augmented circuit exceeds the upper limit of the standard EN55022. By incorporating the augmented circuit, the conducted EMI of the full-bridge inverter is significantly mitigated below the upper limit.

Then, the output voltage of the WPT system (i.e., 14) is controlled to track the reference (i.e., l/bret) at 4.2 V. The phase shift angles are controlled at 166.2° and 169.8° for the WPT system without and with the augmented circuit, respectively. The comparisons of the magnified waveforms of Vds3 and /d3 within a 0.5^s transient state between the full-bridge inverters with and without the augmented circuit, are shown in Fig. 16. The magnified waveforms show that the hard switching occurs for the known WPT system without the augmented circuit, while ZVS can be achieved by integrating the augmented circuit, even if the phase shift angle has reached about 170° (i.e., the on-pulse width of v _p is only about 10°). Comparisons of conducted EMI from 150 kHz to 30 MHz between the full-bridge inverter without and with the augmented circuit are shown in Fig. 17. Obviously, the conducted EMI of the full-bridge inverter without the augmented circuit also exceeds the upper limit of the standard EN55022 for the voltage control. However, by integrating the augmented circuit, the EMI can be dramatically reduced.

Similar experiments are also conducted on the WPT system with the phase shift angle of 120°, 90°, 60°, 30°, and 0°, respectively. The corresponding waveforms of Vds3, te, ip, and v _p for the WPT system without and with the augmented circuit are shown in "Further data, Section B" below. The results reveal that the augmented circuit can also achieve ZVS for heavy load conditions. The corresponding conducted EMI of the full-bridge inverter without and with the augmented circuit are presented in Fig. 18. Obviously, conducted EMIs are mitigated by the augmented circuit for the heavy load conditions. However, it is worthy to 1 note that the EMI reduction is more significant for the WPT system with a lager phase shift angle.

Further data

A. Background EMIs of the EMC Chamber

Since both the full-bridge inverter and controller circuit are placed inside the test chamber, four background EMIs, including (i) the conducted EMI without the power supplies for auxiliary circuits of the full-bridge inverter and the controller circuit, (ii) the conducted EMI with the power supplies for auxiliary circuits of the full-bridge inverter but without the controller circuit, (iii) the conducted EMI without the power supplies for auxiliary circuits of the full-bridge inverter but with the controller circuit, and (iv) the conducted EMI with the power supplies for auxiliary circuits of the full-bridge inverter, are measured as references, as shown in Fig. 19.

B. Waveforms of vdss, ids, ip, and v _p of the WPT Systems with Different Phase Shift Angles Experimental waveforms of Vds3, ids, ip, and v _p of the full-bridge inverter without and with the augmented circuit for the phase shift angle at 120°, 90°, 60°, 30°, and 0° are shown in Fig. 20.

It will be appreciated that the invention has been described by way of example only. Various modifications may be made to the techniques described herein without departing from the spirit and scope of the appended claims. The disclosed techniques comprise techniques which may be provided in a stand-alone manner, or in combination with one another. Therefore, features described with respect to one technique may also be presented in combination with another technique.

The current application also describes the following concepts.

1 An augmented passive circuit (with connections shown in Fig. 5) comprising two diodes, two capacitors and one inductor for achieving soft switching in all the power switches in a power inverter under phase-shift modulation control.

2 The augmented passive circuit can be added to a power inverter to achieve soft switching under either fixed-frequency or variable-frequency operations of power inverter. 3 The augmented passive circuit can reduce the switching power stress and power losses to improve the lifetime and conversion efficiency of power inverters.

4 The augmented passive circuit can be used to modify existing designs of wireless power transfer systems compliant with the standards of the Wireless Power Consortium and Society of Automotive Engineers without changing the control algorithms.

5 The augmented passive circuit can be transformed as an augmented active circuit by replacing the inductor with an actively-controlled current source or an equivalent current source, while still maintaining the functions described in the above points 2 to 4.

6 A design method for the augmented passive circuit based on the equations (25) to (27).

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