SHASTRI BHAVIN J (CA)
WIGHTMAN DOUGLAS H (CA)
US8681982B2 | 2014-03-25 |
CLAIMS WHAT IS CLAIMED IS: 1. A photonic processor, comprising: a first photonic circuit configured to generate a plurality of new messages based at least in part on a plurality of input messages; and a second photonic circuit coupled to the first photonic circuit via a set of optical connections, the second photonic circuit configured, during a plurality of operational cycles, to: receive, from the first photonic circuit via the set of optical connections, the plurality of new messages, and update a plurality of keys based at least in part on the received plurality of new messages, wherein the second photonic circuit is further configured to generate at least one hash value based on the plurality of keys generated after the plurality of operational cycles. 2. The photonic processor of claim 1, wherein the second photonic circuit is further configured to: receive, from the first photonic circuit via the set of optical connections during each iteration of a plurality of iterations, a subset of the plurality of new messages; update the plurality of keys based at least in part on the received subset of new messages; and generate the at least one hash value based on the plurality of keys obtained after the plurality of iterations. 3. The photonic processor of claim 2, wherein the second photonic circuit is configured to update the plurality of keys based at least in part on the received subset of new messages, while the first photonic circuit generates another subset of the plurality of new messages. 4. The photonic processor of claim 1, wherein the second photonic circuit is further configured to update the plurality of keys over a plurality of pipeline stages of the second photonic circuit based at least in part on a corresponding subset of the plurality of new messages received at each of the plurality of pipeline stages. 5. The photonic processor of claim 1, further comprising: an array of photodetectors coupled to the second photonic circuit via another set of optical connections, the array of photodetectors configured to detect the at least one hash value received at the array of photodetectors via the other set of optical connections; and an interface circuit coupled to the array of photodetectors, the interface circuit configured to compare the at least one detected hash value with at least one target value. 6. The photonic processor of claim 1, further comprising an array of photodetectors coupled to the first photonic circuit via a first set of optical connections and to the second photonic circuit via a first set of electrical connections, the array of photodetectors configured to: receive at least a portion of the generated new messages from the first photonic circuit via the first set of optical connections; and transmit at least the portion of the received new messages to the second photonic circuit via the first set of electrical connections. 7. The photonic processor of claim 1, further comprising an array of photonic intensity modulators coupled to the second photonic circuit via another set of optical connections, the array of photonic intensity modulators configured to: receive at least a portion of initial key values for the plurality of keys, the portion of initial key values encoded in a plurality of optical wavelengths; and transmit the received portion of initial key values to the second photonic circuit via the other set of optical connections. 8. The photonic processor of claim 7, wherein the array of photonic intensity modulators comprises at least one of: an array of electro-optic effect modulators, an array of carrier- depletion effect modulators, and an array of thermo-optic effect modulators. 9. The photonic processor of claim 1, wherein the second photonic circuit is configured to update the plurality of keys by at least performing rotation and shifting of a subset of the plurality of keys to generate a rotated subset of the plurality of keys. 10. The photonic processor of claim 9, wherein the second photonic circuit is further configured to perform logical operations on the rotated subset of keys to generate a processed subset of the plurality of keys. 11. The photonic processor of claim 1, wherein the second photonic circuit is configured to generate at least a subset of the updated keys, each updated key in the subset generated by at least combining corresponding processed versions of the plurality of keys and at least one corresponding new message of the received subset of new messages. 12. The photonic processor of claim 11, wherein the second photonic circuit is further configured to split at least one of the corresponding processed versions of the plurality of keys before the updated key is generated. 13. The photonic processor of claim 1, wherein the second photonic circuit comprises at least one of: a plurality of photonic components, a plurality of photonic logic super-gates, a plurality of photonic regenerator stages, a plurality of photonic logic adder gates, a plurality of bit corrector gates, a plurality of photonic majority logic gates, a plurality of photonic choose logic gates, and at least one photonic splitter coupled to at least one of the plurality of the photonic logic adder gates. 14. The photonic processor of claim 13, wherein the plurality of photonic components comprises at least one of: a plurality of three-dimensional layout components, a plurality of photonic crossing devices, a plurality of photonic logic gates, a plurality of photonic wire bonds, and a plurality of optical fibers. 15. The photonic processor of claim 1, wherein the photonic processor is implemented as a silicon photonics platform. 16. A non-transitory computer-readable storage medium comprising stored instructions that, when executed by at least one processor, cause the at least one processor to: instruct a first photonic circuit of the photonic processor to generate a plurality of new messages based at least in part on a plurality of input messages; initiate, at a second photonic circuit of the photonic processor during a plurality of operational cycles, reception of the plurality of new messages from the first photonic circuit via a set of optical connections; instruct, during the plurality of operational cycles, the second photonic circuit to update a plurality of keys based at least in part on the received plurality of new messages; and instruct, after the plurality of operational cycles, the second photonic circuit to generate at least one hash value based on the plurality of keys obtained after the plurality of operational cycles. 17. The computer-readable storage medium of claim 16, wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to: initiate, at the second photonic circuit during each iteration of a plurality of iterations, reception of a subset of the plurality of new messages from the first photonic circuit via the set of optical connections; instruct, during each of the plurality of iterations, the second photonic circuit to update the plurality of keys based at least in part on the received subset of new messages; and instruct, after the plurality iterations, the second photonic circuit to generate the at least one hash value based on the plurality of keys obtained after the plurality of iterations. 18. The computer-readable storage medium of claim 16, wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to: initiate the second photonic circuit to update the plurality of keys over a plurality of pipeline stages of the second photonic circuit based at least in part on a corresponding subset of the plurality of new messages received at each of the plurality of pipeline stages; instruct an array of photodetectors coupled to the second photonic circuit via another set of optical connections to detect the at least one hash value received at the array of photodetectors via the other set of optical connections; and instruct an interface circuit coupled to the array of photodetectors to compare the at least one detected hash value with at least one target value. 19. The computer-readable storage medium of claim 16, wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to: instruct an array of photonic intensity modulators of the photonic processor coupled to the second photonic circuit via another set of optical connections to receive at least a portion of initial key values for the plurality of keys, the portion of initial key values encoded in a plurality of optical wavelengths; and instruct the array of photonic intensity modulators to send the received portion of initial key values to the second photonic circuit via the other set of optical connections. 20. A method comprising: generating, by a first photonic circuit of a photonic processor, a plurality of new messages based at least in part on a plurality of input messages; receiving, at a second photonic circuit of the photonic processor during a plurality of operational cycles, the plurality of new messages from the first photonic circuit via a set of optical connections; updating, by the second photonic circuit during the plurality of operational cycles, a plurality of keys based at least in part on the received plurality of new messages; and generating, by the second photonic circuit after the plurality of operational cycles, at least one hash value based on the plurality of keys obtained after the plurality of operational cycles. |
where, and K i is a constant. [0031] While the new messages 132, W i , are being generated at the message generation photonic circuit 130, the process of digesting the messages 132 and updating the key values 136 at the keys update photonic circuit 134 in accordance with equations (4)-(14) occurs in parallel as part of different pipeline stages of the processor 100. In one or more embodiments, initial values of eight keys (e.g., keys A, B, C, D, E, F, G, H) each having B bits (e.g., 32 bits) are input in parallel (e.g., as part of the optical input data 114 and the digital input data 108) using an array of Mach-Zehnder modulators (e.g., 32 x 8 = 256 Mach-Zehnder modulators) within the array of photonic intensity modulators 118. A bit sequence corresponding to the initial key values input into the array of Mach-Zehnder modulators of the array of photonic intensity modulators 118 may be split via the array of photonic splitters 124 and passed onto the keys update photonic circuit 124 as the initial key values 128. Since the initial key values 128 remain constant per hash value 144, the initial key values 128 may be encoded (e.g., as part of the optical input data 114 and the optical data 122) in N different optical wavelengths λ j (j = 1, …, N). [0032] It should be noted that keys A and E may require processing within the keys update photonic circuit 134 before interaction with other keys. Furthermore, keys A and E may complete a defined number of rotations (e.g., three rotations) at the keys update photonic circuit 134 before the interaction (e.g., via addition) with the new message 132 from the message generation photonic circuit 130 and the regenerated keys 138 from the photodetector array 140. The rotation operations may be performed at the keys update photonic circuit 134 by utilizing either, e.g., a three-dimensional layout or photonic wire bonds. Alternatively, the keys update photonic circuit 134 may employ a plurality of optical fibers for performing the rotation operations. [0033] Once the rotation operations are performed at the keys update photonic circuit 134, a plurality of XOR photonic circuits (e.g., four 32-bit XOR photonic circuits, 128 XOR photonic crystals, or two 32-bit inverse-designed three-input XOR photonic gates) of the keys update photonic circuit 134 may be used to generate values Σ 0 ( A ) and Σ 1 ( E), as defined by equations (17)-(18). Then, the value of Σ 0 ( A) may be added at the keys update photonic circuit 134 (e.g., via a 32-bit full photonic adder) to a value of a majority function (e.g., MAJ (A, B, C)) to obtain the value of T 2 , as defined by equation (5). Furthermore, the value of Σ 1 ( E) may be added at the keys update photonic circuit 134 (e.g., via a 32-bit full photonic adder) to a value of a choose function (e.g., CH (E, F, G)), as defined in equation (4). To obtain the value of T 1 , as defined by equation (4), the keys update photonic circuit 134 may add a sum of H, K i and W i to the resultant value of addition between the value of the choose function and the value of Σ 1 ( E). Each of the majority function and the choose function may be performed at the keys update photonic circuit 134 by utilizing a corresponding array of photonic circuits (e.g., an array of 32 x 2 = 64 inverse- designed photonic gates). [0034] The value of key H may be input (e.g., as part of the optical input data 114 or the digital input data 108) via an array of Mach-Zehnder modulators within the array of photonic intensity modulators 118 (e.g., 32 Mach-Zehnder modulators), and then passed via a portion of the array of photonic splitters 124 onto the keys update photonic circuit 134 as one of the initial key values 128. The constant value K i and the message 132, W i , may be different for each updated key value 136. Thus, each of the constant value K i and the message 132, W i , may be input using a corresponding array of micro-ring modulators (e.g., an array of 32 x N micro-ring modulators) within the array of photonic intensity modulators 116 and/or the array of photonic intensity modulators 118 before being passed onto the keys update photonic circuit 134. Alternatively, each of the messages 132, W i , may be input using a set of waveguides connected to the message generation photonic circuit 130. The values of H, K i and W i may be mutually added and then added to the resultant value of addition between the value of the choose function and the value of Σ 1 ( E) using a set of full photonic adders (e.g., three 32-bit full photonic adders) at the keys update photonic circuit 134 to generate the value of T 1 (e.g., 32-bit value), as defined by equation (4). [0035] The value of T 1 may be split (e.g., via a photonic splitter of the keys update photonic circuit 134) into two split values, ~T 1 , representing approximate values of T 1 . The first split value, ~T 1 , may be added at the keys update photonic circuit 134 (e.g., via a 32-bit full photonic adder) to the previously generated value of T 2 to generate a value (e.g., 32-bit value) with which the key A is updated, as per equation (14). The second split value, ~ T 1 , may be added at the keys update photonic circuit 134 (e.g., via a 32-bit full photonic adder) to the key D to generate another value (e.g., 32-bit value) with which the key E is updated, as per equation (10). The value of key D may be input via an array of Mach-Zehnder modulators (e.g., 32 Mach- Zehnder modulators) within the array of photonic intensity modulators 118, and then passed via a portion of the array of photonic splitters 124 onto the keys update photonic circuit 134 as one of the initial key values 128. The keys update photonic circuit 134 may further include at least one array of photonic splitters to update the remaining keys and generate the full set of updated key values 136 (e.g., updated key values A, B, C, D, E, F, G, H). The set of updated key values 136 may be wired to the photodetector array 140 where the updated key values 136 are stored in the electronic domain (e.g., at an array of 8 x 32 photodetectors). This process of updating key values may be repeated as many times as the number of messages 132 are available (e.g., 64 times or iterations). [0036] The photodetector array 140 may generate (i.e., detect) at least one resultant hash values 142 using the final set of key values 136. The final set of key values correspond to the set of updated key values 136 at the last iteration (e.g., the 64 th iteration). The at least one resultant hash values 142 may be then output onto the CMOS output interface circuit 144. The CMOS output interface circuit 144 may compare each resultant hash value 140 with a target value. The processor 100 may generate P resultant hash values 140 per block, where one block is defined by the operations performed by the processor 100. EXAMPLE PHOTONIC PROCESSOR [0037] FIG.2 illustrates an example block diagram of a photonic processor 200 for message generation, keys update and hash generation, in accordance with some embodiments. The photonic processor 200 may include an input photonic circuit 205, an input photonic circuit 210, a message generation photonic circuit 215, a keys update photonic circuit 220, and a photodetector array 230. The photonic processor 200 may include fewer or additional components not shown in FIG.2. [0038] The input photonic circuit 205 may receive input data 202 of a first size (e.g., 512 bits) via a first set of electrical connections. The input data 202 may be a digital data (e.g., a bit sequence) obtained from a digital network (not shown in FIG.2). In some embodiments, the input photonic circuit 205 encompasses a portion of the array of lasers 110, the array of photonic intensity modulators 116, and a portion of the array of photonic splitters 124. The input photonic circuit 205 may generate a plurality of input messages 212 of a second size (e.g., 32 bits) based at least in part on the received input data 202. A number of the input messages 212 generated by the input photonic circuit 205 may be equal to a ratio of the first size to the second size (e.g., 16 32-bit input messages 212 may be generated). A first portion of the received input data 202 may be associated with a first subset of the input messages 212 that do not comprise parts of a nonce, and a second portion of the received input data 202 may be associated with a second subset of the input messages 212 comprising a plurality of increments of the nonce. The first subset of input messages 212 may include at least one input message 212 received in a plurality of optical wavelengths or optical modes. Each input message 212 in the second subset may include a respective increment of the nonce represented as a respective optical wavelength of the plurality of optical wavelengths. [0039] The input photonic circuit 210 may receive digital input data 204 (e.g., generated by a digital network) via a second set of electrical connections. The input photonic circuit 210 may generate initial key values 214 based at least in part on the received digital input data 204. In some embodiments, the input photonic circuit 210 encompasses a portion of the array of lasers 110, the array of photonic intensity modulators, and a portion of the array of photonic splitters 124. To generate the initial key values 214, input photonic circuit 210 may encode information about the initial key values 214 in a plurality of optical wavelengths or optical modes. The input photonic circuit 210 may transmit the initial key values 214 to the keys update photonic circuit 220 via a fifth set of optical connections. [0040] The message generation photonic circuit 215 may receive the input messages 212 from the input photonic circuit 205 via a first set of optical connections. The message generation photonic circuit may generate a plurality of output messages 216 of the second size based at least in part on the input messages 212. The message generation photonic circuit 215 may generate each output message 216 (or new message) by summing a corresponding pair of processed versions of the input messages 212 and a corresponding pair of the input messages 212. The message generation photonic circuit 215 may comprise a plurality of photonic components configured to generate a subset of the output messages 216 by at least performing rotation and shifting of a subset of the input messages 212. The photonic components of the message generation photonic circuit 215 may include: a plurality of passive or active (e.g., electro-optic) three-dimensional layout components, a plurality of passive or active (e.g., electro-optic) photonic crossing devices, a plurality of photonic wire bonds, a plurality of optical fibers, a plurality of linear or nonlinear (and active or passive) photonic regenerator stages, other type of photonic component, or some combination thereof. The message generation photonic circuit 215 may further include: a plurality of passive or active (e.g., electro-optic) photonic logic gates, a plurality of passive or active (e.g., electro-optic) photonic super-gates, a plurality of passive or active (e.g., electro-optic) photonic logic adders, a plurality of passive or active (e.g., electro- optic) bit corrector gates, other types of photonic gates, or some combination thereof. The photonic super-gates are designed to include the compute for two or more photonic gates that cascade into each other. The bit corrector gates are designed to fix errors (e.g., bit errors) resulting from cascading two or more photonic gates. The message generation photonic circuit 215 may be an embodiment of the message generation photonic circuit 130. [0041] The photodetector array 230 may receive at least a portion of the output messages 216 from the message generation photonic circuit 215 via a second set of optical connections for, e.g., further processing and generation of at least one hash value 235. The photodetector array 230 may further transmit output messages 218 (e.g., digital values or bit sequence) to the keys update photonic circuit 220 via a third set of electrical connections. The photodetector array 230 may be an embodiment of the photodetector array 140. [0042] The keys update photonic circuit 220 may receive, during a plurality of operational cycles, the plurality of output messages 216 from the message generation photonic circuit 215 via a third set of optical connections. The keys update photonic circuit 220 may receive, during each operational cycle, a respective output message 216. In some embodiments, the plurality of output messages 216 may also include the plurality of input messages 212. For example, a total of 64 output messages 216 may be passed onto the keys update photonic circuit 220 during 64 operational cycles (e.g., during 64 iterations at the keys update photonic circuit 220). The keys update photonic circuit 220 may update, during each operational cycle (i.e., during each iteration), a plurality of key values 225, based on at least one output message 216, initial key values 214 and at least one output message 218. The at least one output message 218 may be a digital version (i.e., bit sequence) of the at least one photonic output message 216 passed onto the keys update photonic circuit 220 directly from the message generation photonic circuit 215. While updating the plurality of key values 225 at the keys update photonic circuit 220, the message generation photonic circuit may generate at least one new output message 216. The keys update photonic circuit 220 may update the plurality of key values 225 over a plurality of pipeline stages of the keys update photonic circuit 220 based at least in part on a corresponding subset of the output messages 216 received at each of the plurality of pipeline stages. [0043] During each iteration, the keys update photonic circuit 220 may perform rotation and shifting on a subset of keys (e.g., on the initial key values 214) to generate a rotated subset of keys. The keys update photonic circuit 220 may further perform logical operations on the rotated subset of keys to generate processed key values. The keys update photonic circuit 220 may generate at least one updated key 225 during each iteration by combining at least one of the processed keys and at least one output message 216 received at the keys update photonic circuit 220. The keys update photonic circuit 220 may further split at least one of the processed keys before the updated key 225 is generated. [0044] The keys update photonic circuit 220 may include: a plurality of photonic components, a plurality of passive or active (e.g., electro-optic) photonic logic super-gates, a plurality of passive or active (e.g., electro-optic) photonic regenerator stages, a plurality of photonic logic adder gates, a plurality of passive or active (e.g., electro-optic) bit corrector gates, a plurality of photonic majority logic gates, a plurality of photonic choose logic gates, at least one photonic splitter coupled to at least one of the plurality of the photonic logic adder gates, other type of photonic circuit, or some combination thereof. The plurality of photonic components of the keys update photonic circuit 220 may be implemented as: a plurality of three- dimensional layout components, a plurality of photonic crossing devices, a plurality of photonic logic gates, a plurality of photonic wire bonds, a plurality of optical fibers, other type of photonic component, or some combination thereof. The keys update photonic circuit 220 may be an embodiment of the keys update photonic circuit 134. [0045] After a defined number of iterations (which may correspond to the number of the output messages 216 provided to the keys update photonic circuit 220), the photodetector array 230 may receive final values of the updated keys 225 from the keys update photonic circuit 220 via a fourth set of optical connections. The photodetector array 230 may generate (i.e., detect) at least one hash value 235 based on the received final values of the updated keys 225. EXAMPLE PROCESS FLOWS [0046] FIG.3 is a flowchart illustrating an example method 300 for message generation at a photonic processor for digital currency transactions, in accordance with some embodiments. The operations of method 300 may be performed at, e.g., the processor 100 or the photonic processor 200. The photonic processor may be deployed in a computing system that can further include a non-transitory computer-readable storage medium (e.g., optical, electrical, or electro- optical memory) for storing computer executable instructions and data. The photonic processor may be implemented as a silicon photonics platform. [0047] The photonic processor receives 305 (e.g., via an input photonic circuit) input data of a first size (e.g., 512 bits). The input photonic circuit may comprise an array of photonic intensity modulators configured to receive the input data from an array of lasers. The array of photonic intensity modulators may comprise at least one of: an array of electro-optic effect modulators, an array of carrier-depletion effect modulators, and an array of thermo-optic effect modulators. The array of electro-optic effect modulators may comprise, e.g., an array of Mach- Zehnder modulators. The array of carrier-depletion effect modulators may comprise, e.g., at least one of: an array of micro-disk modulators, an array of nanobeam modulators, and an array of micro-ring modulators. [0048] The photonic processor splits 310 (e.g., by the input photonic circuit) the received input data into a plurality of input messages of a second size (e.g., 32 bits). A number of the plurality of input messages (e.g., 16 input messages) may be equal to a ratio of the first size to the second size. In some embodiments, the input photonic circuit further comprises an array of photonic splitters coupled to the array of photonic intensity modulators. The array of photonic splitters may be configured to receive the input data from the array of photonic intensity modulators, and split the received input data into the plurality of input messages. A first portion of the received input data may be associated with a first subset of the input messages that do not comprise parts of a nonce, and a second portion of the received input data may be associated with a second subset of the input messages comprising a plurality of increments of the nonce. The first subset of input messages may comprise an input message of the plurality of input messages received in a plurality of optical wavelengths or optical modes. Each input message in the second subset may comprise a respective increment of the nonce represented as a respective optical wavelength of the plurality of optical wavelengths. [0049] The photonic processor receives 315 the plurality of input messages at a message generation photonic circuit of the photonic processor coupled to the input photonic circuit via a set of optical connections. The photonic processor generates 320 (e.g., via the message generation photonic circuit) a plurality of output messages of the second size based at least in part on the plurality of input messages. The photonic processor may generate (e.g., via the message generation photonic circuit) an output message of the plurality of output messages by summing a corresponding pair of processed versions of the plurality of input messages and a corresponding pair of the plurality of input messages. [0050] The message generation photonic circuit may comprise a plurality of photonic components configured to generate a subset of the plurality of output messages by at least performing rotation and shifting of a subset of the plurality of input messages. The plurality of photonic components of the message generation photonic circuit may comprise at least one of: a plurality of three-dimensional layout components, a plurality of three-dimensional bit corrector gates, a plurality of photonic crossing devices, a plurality of photonic logic gates, a plurality of photonic wire bonds, a plurality of optical fibers, a plurality of photonic logic super-gates, and a plurality of photonic regenerator stages. The message generation photonic circuit may further comprise at least one of: a plurality of photonic logic adders, a plurality of bit corrector gates, a plurality of photonic logic super-gates, and a plurality of photonic regenerator stages. [0051] In some embodiments, the photonic processor further includes an array of photodetectors coupled to the message generation photonic circuit via a second set of optical connections. The array of photodetectors may be configured to receive the generated output messages via the second set of optical connections for further processing and generation of at least one hash value. [0052] FIG.4 is a flowchart illustrating an example method 400 for keys update and hash generation at a photonic processor for digital currency transactions, in accordance with some embodiments. The operations of method 400 may be performed at, e.g., the processor 100 or the photonic processor 200. The photonic processor may be deployed in a computing system that can further include a non-transitory computer-readable storage medium (e.g., optical, electrical, or electro-optical memory) for storing computer executable instructions and data. The photonic processor may be implemented as a silicon photonics platform. [0053] The photonic processor generates 405 (e.g., via a first photonic circuit or a message generation photonic circuit) a plurality of new messages based at least in part on a plurality of input messages. The photonic processor receives 410 (e.g., at a second photonic circuit or a keys update photonic circuit), during a plurality of operational cycles, the plurality of new messages from the first photonic circuit via a set of optical connections. The photonic processor updates 415 (e.g., via the second photonic circuit), during the plurality of operational cycles, a plurality of keys based at least in part on the received plurality of new messages. The photonic processor generates 420 (e.g., via the second photonic circuit), after the plurality of operational cycles, at least one hash value based on the plurality of keys obtained after the plurality of operational cycles. [0054] The second photonic circuit may receive, from the first photonic circuit via the set of optical connections during each iteration of a plurality of iterations, a subset of the plurality of new messages. The second photonic circuit may update the plurality of keys based at least in part on the received subset of new messages. The second photonic circuit may generate the at least one hash value based on the plurality of keys obtained after the plurality of iterations. The second photonic circuit may update the plurality of keys based at least in part on the received subset of new messages, while the first photonic circuit generates another subset of the plurality of new messages. The second photonic circuit may be further configured to update the plurality of keys over a plurality of pipeline stages of the second photonic circuit based at least in part on a corresponding subset of the plurality of new messages received at each of the plurality of pipeline stages. [0055] In some embodiments, the photonic processor further includes an array of photodetectors coupled to the second photonic circuit via another set of optical connections, and an interface circuit coupled to the array of photodetectors. The array of photodetectors may be configured to detect the at least one hash value received at the array of photodetectors via the other set of optical connections. The interface circuit may be configured to compare the at least one detected hash value with at least one target value. [0056] In some embodiments, the photonic processor further includes an array of photodetectors coupled to the first photonic circuit via a first set of optical connections and to the second photonic circuit via a first set of electrical connections. The array of photodetectors may be configured to receive at least a portion of the generated new messages from the first photonic circuit via the first set of optical connections, and transmit at least the portion of the received new messages to the second photonic circuit via the first set of electrical connections. [0057] In some embodiments, the photonic processor further includes an array of photonic intensity modulators coupled to the second photonic circuit via another set of optical connections. The array of photonic intensity modulators may be configured to receive at least a portion of initial key values for the plurality of keys, the portion of initial key values encoded in a plurality of optical wavelengths or optical modes, and transmit the received portion of initial key values to the second photonic circuit via the other set of optical connections. The array of photonic intensity modulators may comprise at least one of: an array of electro-optic effect modulators, an array of carrier-depletion effect modulators, and an array of thermo-optic effect modulators [0058] The second photonic circuit may be configured to update the plurality of keys by at least performing rotation and shifting of a subset of the plurality of keys to generate a rotated subset of the plurality of keys. The second photonic circuit may be further configured to perform logical operations on the rotated subset of keys to generate a processed subset of the plurality of keys. In some embodiments, the second photonic circuit is configured to generate at least a subset of the updated keys, each updated key in the subset generated by at least combining corresponding processed versions of the plurality of keys and at least one corresponding new message of the received subset of new messages. The second photonic circuit may be further configured to split at least one of the corresponding processed versions of the plurality of keys before the updated key is generated. [0059] The second photonic circuit may comprise at least one of: a plurality of photonic components, a plurality of photonic logic super-gates, a plurality of photonic regenerator stages, a plurality of photonic logic adder gates, a plurality of bit corrector gates, a plurality of photonic majority logic gates, a plurality of photonic choose logic gates, and at least one photonic splitter coupled to at least one of the plurality of the photonic logic adder gates. The plurality of photonic components of the second photonic circuit may comprise at least one of: a plurality of three-dimensional layout components, a plurality of photonic crossing devices, a plurality of photonic logic gates, a plurality of photonic wire bonds, and a plurality of optical fibers. [0060] The photonic processor presented herein provides an increase in energy efficiency while simultaneously increasing a hash rate and decreasing a die area. This is achieved by implementing a secure hash algorithm using photonic circuits on a silicon photonics platform. A high throughput is achieved by exploiting a low latency offered by optical interconnects, photonic devices, passive photonic logic gates, and wavelength-division multiplexing. A high compute density and low power consumption can be achieved by utilizing photonic crystals and waveguides for propagating photonic signals. The photonic processor presented herein does not require any memory to store data and thus overcomes the need of data convertors. ADDITIONAL CONSIDERATIONS [0061] The foregoing description of the embodiments of the disclosure has been presented for the purpose of illustration; it is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above disclosure. [0062] Some portions of this description describe the embodiments of the disclosure in terms of algorithms and symbolic representations of operations on information. These algorithmic descriptions and representations are commonly used by those skilled in the data processing arts to convey the substance of their work effectively to others skilled in the art. These operations, while described functionally, computationally, or logically, are understood to be implemented by computer programs or equivalent electrical circuits, microcode, or the like. Furthermore, it has also proven convenient at times, to refer to these arrangements of operations as modules, without loss of generality. The described operations and their associated modules can be embodied in software, firmware, hardware, or any combinations thereof. [0063] Any of the steps, operations, or processes described herein can be performed or implemented with one or more hardware or software modules, alone or in combination with other devices. In one embodiment, a software module is implemented with a computer program product comprising a computer-readable medium containing computer program code, which can be executed by a computer processor for performing any or all of the steps, operations, or processes described. [0064] Embodiments of the disclosure can also relate to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, and/or it can comprise a general-purpose computing device selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a non- transitory, tangible computer readable storage medium, or any type of media suitable for storing electronic instructions, which is coupled to a computer system bus. Furthermore, any computing systems referred to in the specification can include a single processor or can be architectures employing multiple processor designs for increased computing capability. [0065] Some embodiments of the present disclosure can further relate to a system comprising a processor, at least one computer processor, and a non-transitory computer-readable storage medium. The storage medium can store computer executable instructions, which when executed by the compiler operating on the at least one computer processor, cause the at least one computer processor to be operable for performing the operations and techniques described herein. [0066] Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it has not been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the disclosure be limited not by this detailed description, but rather by any claims that issue on an application based hereon. Accordingly, the disclosure of the embodiments is intended to be illustrative, but not limiting, of the scope of the disclosure, which is set forth in the following claims.