PHOTOVOLTAIC DEVICES WITH ENCAPSULATION LAYERS AND SYSTEMS AND METHODS FOR FORMING THE SAME

BACKGROUND

[0001] The present specification generally relates to photovoltaic devices with one or more encapsulation layers, and, more specifically, to devices and methods using organosilicon materials in coatings for photovoltaic devices.

[0002] A photovoltaic device generates electrical power by converting light into electricity using semiconductor materials that exhibit the photovoltaic effect. Photovoltaic devices include a number of layers divided into a plurality of photovoltaic cells. Each photovoltaic cell converts sunlight into electrical power and can be connected in series with one or more adjacent cells of a photovoltaic device. A plurality of photovoltaic devices or modules may be electrically connected into a larger array or system. Photovoltaic devices are often used in outdoor installations, in a wide range of environments, and intended to function reliably for many years. Photovoltaic devices generally include internal layers and components which may fail or function poorly if exposed to moisture, oxygen, or airborne contaminants.

[0003] Accordingly, a need exists for photovoltaic devices with effective and efficient encapsulation technology.

SUMMARY

[0004] The embodiments provided herein relate to photovoltaic devices with an organosilicon encapsulation layer and methods of forming an encapsulation layer on a partially-formed photovoltaic device. A partially-formed device may have a plurality of semiconductor layers forming a layer stack on a substrate. The method may include applying a coating over the layer stack, wherein the coating comprises an organosilicon material including at least a polysilsesquioxane (PSSQ) or a polysilazane (PSZ). The coating contacts and substantially covers a back surface of the layer stack. The coating also contacts and covers a side edge of the layer stack, whereby no portion of the side edge is exposed, and the coating contacts the substrate to substantially encapsulate the layer stack. The coating is cured to produce cross-linkage within the coating, thereby forming the encapsulation layer. These and additional features provided by the embodiments described herein will be more fully understood in view of the following detailed description, in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments set forth in the drawings are illustrative and exemplary in nature and not intended to limit the subject matter defined by the claims. The following detailed description of the illustrative embodiments can be understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals and in which:

[0006] FIG. 1 schematically depicts a photovoltaic device according to one or more embodiments shown and described herein;

[0007] FIG. 2 schematically depicts a cross-sectional view along 2-2 of the photovoltaic device of FIG. 1 according to one or more embodiments shown and described herein;

[0008] FIG. 3 schematically depicts a substrate according to one or more embodiments shown and described herein;

[0009] FIG. 4 schematically depicts a photovoltaic device according to one or more embodiments shown and described herein;

[0010] FIG. 5 schematically depicts a cross-sectional view along 5-5 of the photovoltaic device of FIG. 1 according to one or more embodiments shown and described herein;

[0011] FIGS. 6A to 6F schematically depict cross-sectional views of a photovoltaic device according to one or more embodiments shown and described herein.

[0012] FIG. 7 schematically depicts a cross-sectional view of a photovoltaic device according to one or more embodiments shown and described herein;

[0013] FIG. 8 depicts embodiments of the coating process according to one or more embodiments shown and described herein;

[0014] FIG. 9 depicts embodiments of the coating process according to one or more embodiments shown and described herein; and

[0015] FIGS 10A to 10D depict a photovoltaic device following masking and coating steps, as described in FIG 8.

DETAILED DESCRIPTION

[0016] Embodiments of photovoltaic devices having an environmentally robust coating or encapsulation layer are provided herein. Generally, the photovoltaic devices provided herein can include partly-formed of fully-formed photovoltaic modules with encapsulation to limit the intrusion of moisture and gasses onto internal, electrically active portions of the cells when exposed to environmental conditions. Various embodiments of the photovoltaic device, as well as systems and methods for forming the photovoltaic device, will be described in more detail herein.

[0017] The need for effective, stable, and durable barrier materials in photovoltaic (PV) modules that minimize water and oxygen incursion has increased as extended reliability becomes more important and as more efficient, but more environmentally sensitive, PV technologies are developed. While glass is impermeable through its thickness, it is heavy, brittle, and may be problematic with respect to edge sealing and interfacial sealing.

[0018] Ceramic coatings, such as amorphous aluminum phosphate layers, offer excellent physical, mechanical and chemical resistance properties once thermally cured. However, ceramic coatings generally require excessively high thermal cure temperatures, in excess of 400 degrees Celsius, and extended cure times to achieve the desired environmental barrier properties. At lower cure temperatures, ceramic coatings may be subject to delamination, degradation, and permeation of H ₂ O and O ₂ .

[0019] Flexible polymers, such as polyethylene terephthalate (PET), ethylene-vinyl acetate (EVA), and polyolefins, are lightweight and their properties are well characterized, however, these materials are subject to degradation and permeation of H ₂ O and O ₂ . Furthermore, degradation products, or adhesives used with flexible polymers, can react with some components of photovoltaic devices to produce discoloration and corrosion, leading to reduced device efficiency.

[0020] Described is a methodology to form an encapsulation layer using organo- silicon materials, including polysilsesquioxanes (PSSQs) and polysilazanes (PSZs). PSSQs are a class of organosilicon polymers with an inorganic silicon-oxygen backbone and attached side groups. PSSQs have a general formula of (RSiOi s) _» , where R can be hydrogen, methyl, phenyl, or higher molecular weight organic groups, and PSSQs may form chains and rings and may also be amorphous. Ladder- like forms of PSSQs can demonstrate high thermal stability, optical transparency, and mechanical stability. PSZs are polymers in which silicon and nitrogen atoms alternate to form the basic backbone. PSZs have the general formula (R ¹ R ² Si-NR ³ ) _n with each silicon atom bound to two separate nitrogen atoms and each nitrogen atom to two silicon atoms, and PSZs may form chains and rings and may also be amorphous in structure. [0021] Example materials used in formulating the coating may include T6, T8, T10, and T12 cages and open cage precursors. The material may include both polymeric materials and oligomers. During the curing process, -OH positions on the molecules react and bonds are formed between oxygen and silicon atoms to form cross-linkages and bonding between precursors, oligomers, and polymers. The coating may also include one or more solvents, catalysts, or additives.

[0022] PSSQ closed“cage structures” T6, T8, T10, and T12 are illustrated in the table below.

[0023] PSSQ open“cage precursors” T7a, and T7b are shown in the table below, as are exemplary ladder forms and random or PSSQ structures.

[0024] Use of the described compounds combines the favorable properties of an inorganic oxide, such as thermal stability, chemical stability, and hardness, with the favorable properties of an organic material, such as functionality and processability. [0025] A range of hydrocarbon R- groups are useful with a range of carrier solvents, which may be selected to control the wetting characteristics of the PSSQ or PSZ coating for use with particular metal, glass, and organic polymer materials used at, or adjacent to, a back metal contact of a thin film photovoltaic module. Exemplary R groups may be aliphatic, for example alkyl of 1-12 carbons in straight or branched chains, such as methyl, ethyl, isopropyl and the like. Exemplary R groups may be aryl or aralkyl, for example single or multiple or fused ring structures of 7 to 24 carbons, e.g. phenyl, tolyl, or naphthyl.

[0026] PSSQs and PSZs can take on characteristics of a ceramic coating following the thermal cure. PSSQs and PSZs are thermoset materials that can be hardened to a dense hybrid inorganic-organic glass with heating. Using selected materials in coating and curing, as described further herein, the resulting material may form an encapsulation layer for use with photovoltaic devices to protect them from environmental factors. The polymerization and deposition conditions may be altered to influence the film morphology to control adhesion, porosity, and permeation. In some embodiments, the strength and integrity provided by the encapsulation layer may eliminate the need for a side edge seal and a supporting back cover glass used on the back side, including omitting the associated elastomeric and adhesive layers used to secure the back cover glass. In some embodiments, use of an encapsulation layer may facilitate use of thinner or lighter materials for back side support.

[0027] PSSQ and PSZ coatings may be applied as a liquid suspension of selected oligomers and polymer precursors in an organic solvent. The liquid may be coated onto a formed or partly formed, in-process, photovoltaic device. The coating may be applied by an application method including, but not limited to: spray coating, meniscus coating, roll coating, dip coating, flow coating, curtain coating, slot die coating, spin coating, inkjet printing, gravure, and selective printing technologies. The coating may be applied in a single step or in multiple stages, or by more than one application method and may be applied without an intervening drying step.

[0028] After a coating is applied to one or more device surfaces, the coating may optionally be dried, removing excess solvent. Drying may be performed at ambient temperature and pressure. Drying may be performed using an air knife or other drying method. The coating may be applied in a single step or in multiple stages with or without intervening drying steps.

[0029] PSSQ and PSZ coatings may be cured to form an encapsulation layer. Thermal curing may be performed by applying heat using a resistive heating oven, photonic curing, or variable frequency microwave curing. Curing may include a hybrid method of two or more curing methods, for example, photonic or microwave curing methods may be combined with curing the device in a heated chamber. The curing step may include exposing the dried coating to a temperature between 220 C and 350 C for a period of 5 minutes to 60 minutes.

[0030] In some embodiments, the curing step is performed at a temperature in a range of 230 C to 300 C for a period of 20 minutes to 90 minutes. In some embodiments, the curing step is performed at a temperature in a range of 270 C to 330 C. In some embodiments, the curing step is performed at a temperature in a range of 290 C to 310 C. In some embodiments, the curing step is performed at a temperature in a range of 230 C to 300 C for a duration of 5 to 40 minutes. In some embodiments, the curing is performed by a variable frequency microwave (VFM) instrument and the heating duration is between 5 to 45 minutes, 5 to 30 minutes, or 10 to 25 minutes. In some embodiments, the curing is performed by VFM and no portion of the substrate or layer stack has a temperature of greater than 300 C at any time during the thermal cure. In some embodiments, the curing is performed by VFM in a heated chamber and no portion of the layer stack has a temperature greater than 270 C at any time during the thermal cure. Catalysts such as Zn (zinc 2-ethylhexanoate) and dibutyltin dilaurate may be used to accelerate the curing.

[0031] The encapsulation layer may provide a hermetic or semi-hermetic sealing layer. The encapsulation layer may be transparent, durable, non-porous, scratch resistant, and impervious to moisture. Following a curing step, the thickness of the encapsulation layer may be 5% to 30% of a thickness of the coating following the applying step. The cured encapsulation layer may range from about 0.1 pm to about 10 pm, for example from about 3 mhi to about 6 mhi. Changes in chemical structure of the encapsulation layer relative to the coating layer can be measured and assessed using an infrared absorption profile. The IR absorption for Si-O-Si (1130- 1000cm ¹ ) is different from Si-OH (3690, 3400-3200cm ¹ ). The IR absorbance for the Si-O-Si in a closed ring structure at about 1130-1120cm ¹ is differentiated from the Si-O-Si in a non-ring closed structure including a crosslinked matrix at about 1080- 1060cm ¹ . The ratio of the areas under the absorbance peaks for Si-O-Si (ring closed) / Si-O- Si (non-ring closed) before and after a thermal cure can be used to assess the degree of crosslinking in the cured PSSQ film. Reduction of the Si-OH signal may be used as a secondary indicator of the extent of the crosslinking reaction.

[0032] Referring now to FIG. 1, an embodiment of a photovoltaic device 100 is schematically depicted. The photovoltaic device 100 can be configured to receive light and transform light into electrical signals, e.g., photons can be absorbed from the light and transformed into electrical signals via the photovoltaic effect. Accordingly, the photovoltaic device 100 can define an energy side 102 configured to be exposed to a light source such as, for example, the sun. The photovoltaic device 100 can also define an opposing side 104 offset from the energy side 102 such as, for example, by a plurality of material layers. It is noted that the term“light” can refer to various wavelengths of the electromagnetic spectrum such as, but not limited to, wavelengths in the ultraviolet (UV), infrared (IR), and visible portions of the electromagnetic spectrum.“Sunlight,” as used herein, refers to light emitted by the sun.

[0033] The photovoltaic device 100 can include a plurality of layers disposed between the energy side 102 and the opposing side 104. As used herein, the term“layer” refers to a thickness of material provided upon a surface. Each layer can cover all or any portion of the surface. In some embodiments, the layers of the photovoltaic device 100 can be divided into an array of photovoltaic cells 200. For example, the photovoltaic device 100 can be scribed according to a plurality of serial scribes 202 and a plurality of parallel scribes 204. The serial scribes 202 can extend along a length Y of the photovoltaic device 100 and demarcate the photovoltaic cells 200 along the length Y of the photovoltaic device 100. The serial scribes 202 can be configured to connect neighboring cells of the photovoltaic cells 200 serially along a width X of the photovoltaic device 100. Serial scribes 202 can form a monolithic interconnect of the neighboring cells, i.e., adjacent to the serial scribe 202. The parallel scribes 204 can extend along the width X of the photovoltaic device 100 and demarcate the photovoltaic cells 200 along the width X of the photovoltaic device 100. Under operations, current 205 can predominantly flow along the width X through the photovoltaic cells 200 serially connected by the serial scribes 202. Under operations, parallel scribes 204 can limit the ability of current

205 to flow along the length Y. Parallel scribes 204 are optional and can be configured to separate the photovoltaic cells 200 that are connected serially into groups 206 arranged along length Y. Accordingly, the serial scribes 202 and the parallel scribes 204 can demarcate the array of the photovoltaic cells 200.

[0034] Referring still to FIG. 1, the parallel scribes 204 can electrically isolate the groups

206 of photovoltaic cells 200 that are connected serially. In some embodiments, the groups 206 of the photovoltaic cells 200 can be connected in parallel such as, for example, via electrical bussing. Optionally, the number of parallel scribes 204 can be configured to limit a maximum current generated by each group 206 of the photovoltaic cells 200. In some embodiments, the maximum current generated by each group 206 can be less than or equal to about 200 milliamps (mA) such as, for example, less than or equal to about 100 mA in one embodiment, less than or equal to about 75 mA in another embodiment, or less than or equal to about 50 mA in a further embodiment.

[0035] Referring collectively to FIGS. 1 and 2, the layers of the photovoltaic device 100 can include a substrate 110 configured to facilitate the transmission of light into the photovoltaic device 100. The substrate 110 can be disposed at the energy side 102 of the photovoltaic device 100. Referring now to FIGS. 2 and 3, the substrate 110 can have a first surface 112 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 114 substantially facing the opposing side 104 of the photovoltaic device 100. One or more layers of material can be disposed between the first surface 112 and the second surface 114 of the substrate 110.

[0036] The substrate 110 can include a transparent layer 120 having a first surface 122 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 124 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the second surface 124 of the transparent layer 120 can form the second surface 114 of the substrate 110. The transparent layer 120 can be formed from a substantially transparent material such as, for example, glass. Suitable glass can include soda-lime glass, or any glass with reduced iron content. The transparent layer 120 can have any suitable transmittance, including about 250 nm to about 1,300 nm in some embodiments, or about 250 nm to about 950 nm in other embodiments. The transparent layer 120 may also have any suitable transmission percentage, including, for example, more than about 50% in one embodiment, more than about 60% in another embodiment, more than about 70% in yet another embodiment, more than about 80% in a further embodiment, or more than about 85% in still a further embodiment. In one embodiment, transparent layer 120 can be formed from a glass with about 90% transmittance, or more. Optionally, the substrate 110 can include a performance coating 126 applied to the first surface 122 of the transparent layer 120. The performance coating 126 can be configured to interact with light or to improve durability of the substrate 110 such as, but not limited to, an antireflective coating, an antisoiling coating, or a combination thereof.

[0037] Referring again to FIG. 2, the photovoltaic device 100 can include a barrier layer 130 configured to mitigate diffusion of contaminants (e.g. sodium) from the substrate 110, which could result in degradation or delamination. The barrier layer 130 can have a first surface 132 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 134 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the barrier layer 130 can be provided adjacent to the substrate 110. For example, the first surface 132 of the barrier layer 130 can be provided upon the second surface 114 of the substrate 100. The phrase "adjacent to," as used herein, means that two layers are disposed contiguously and without any intervening materials between at least a portion of the layers.

[0038] Generally, the barrier layer 130 can be substantially transparent, thermally stable, with a reduced number of pin holes and having high sodium-blocking capability, and good adhesive properties. Alternatively or additionally, the barrier layer 130 can be configured to apply color suppression to light. The barrier layer 130 can include one or more layers of suitable material, including, but not limited to, tin oxide, silicon dioxide, aluminum-doped silicon oxide, silicon oxide, silicon nitride, or aluminum oxide. The barrier layer 130 can have any suitable thickness bounded by the first surface 132 and the second surface 134, including, for example, more than about 100 A in one embodiment, more than about 150 A in another embodiment, or less than about 200 A in a further embodiment.

[0039] Referring still to FIG. 2, the photovoltaic device 100 can include a transparent conductive oxide (TCO) layer 140 configured to provide electrical contact to transport charge carriers generated by the photovoltaic device 100. The TCO layer 140 can have a first surface 142 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 144 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the TCO layer 140 can be provided adjacent to the barrier layer 130. For example, the first surface 142 of the TCO layer 140 can be provided upon the second surface 134 of the barrier layer 130. Generally, the TCO layer 140 can be formed from one or more layers of n-type semiconductor material that is substantially transparent and has a wide band gap. Specifically, the wide band gap can have a larger energy value compared to the energy of the photons of the light, which can mitigate undesired absorption of light. The TCO layer 140 can include one or more layers of suitable material, including, but not limited to, tin dioxide, doped tin dioxide (e.g., F-Sn0 ₂ ), indium tin oxide, or cadmium stannate.

[0040] The photovoltaic device 100 can include a buffer layer 150 configured to provide an insulating layer between the TCO layer 140 and any adjacent semiconductor layers. The buffer layer 150 can have a first surface 152 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 154 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the buffer layer 150 can be provided adjacent to the TCO layer 140. For example, the first surface 152 of the buffer layer 150 can be provided upon the second surface 144 of the TCO layer 140. The buffer layer 150 may include material having higher resistivity than the TCO later 140, including, but not limited to, intrinsic tin dioxide, zinc magnesium oxide (e.g., Zm- _x Mg _x O), silicon dioxide (Sn0 ₂ ), aluminum oxide (AI2O3), aluminum nitride (AIN), zinc tin oxide, zinc oxide, tin silicon oxide, or any combination thereof. In some embodiments, the material of the buffer layer 150 can be configured to substantially match the band gap of an adjacent semiconductor layer (e.g., an absorber). The buffer layer 150 may have any suitable thickness between the first surface 152 and the second surface 154, including, for example, more than about 100 A in one embodiment, between about 100 A and about 800 A in another embodiment, or between about 150 A and about 600 A in a further embodiment.

[0041] Referring still to FIG. 2, the photovoltaic device 100 can include an absorber layer 160 configured to cooperate with another layer and form a p-n junction within the photovoltaic device 100. Accordingly, absorbed photons of the light can free electron-hole pairs and generate carrier flow, which can yield electrical power. The absorber layer 160 can have a first surface 162 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 164 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the absorber layer 160 can be defined between the first surface 162 and the second surface 164. The thickness of the absorber layer 160 can be between about 0.5 pm to about 10 pm such as, for example, between about 1 pm to about 7 pm in one embodiment, or between about 1.5 pm to about 4 pm in another embodiment.

[0042] According to the embodiments described herein, the absorber layer 160 can be formed from a p-type semiconductor material having an excess of positive charge carriers, i.e., holes or acceptors. The absorber layer 160 can include any suitable p-type semiconductor material such as group II- VI semiconductors. Specific examples include, but are not limited to, semiconductor materials comprising cadmium, tellurium, selenium, or any combination thereof. Suitable examples include, but are not limited to, ternaries of cadmium, selenium and tellurium (e.g., CdSe _x Tei- _x ), or a compound comprising cadmium, selenium, tellurium, and one or more additional element.

[0043] While specific examples of photovoltaic materials and semiconductors are provided, other suitable materials may be used in the described methods and devices. These may include, but are not limited to silicon and copper indium gallium selenide (CIGS) compounds. Photovoltaic devices may include a plurality of absorber materials. Devices may include one or more pn or pin junctions. [0044] In embodiments where the absorber layer 160 comprises tellurium and cadmium, the atomic percent of the tellurium can be greater than or equal to about 25 atomic percent and less than or equal to about 50 atomic percent such as, for example, greater than about 30 atomic percent and less than about 50 atomic percent in one embodiment, greater than about 40 atomic percent and less than about 50 atomic percent in a further embodiment, or greater than about 47 atomic percent and less than about 50 atomic percent in yet another embodiment. Alternatively or additionally, the atomic percent of the tellurium in the absorber layer 160 can be greater than about 45 atomic percent such as, for example, greater than about 49% in one embodiment. It is noted that the atomic percent described herein is representative of the entirety of the absorber layer 160, the atomic percentage of material at a particular location within the absorber layer 160 can vary with thickness compared to the overall composition of the absorber layer 160.

[0045] In embodiments where the absorber layer 160 comprises selenium and tellurium, the atomic percent of the selenium in the absorber layer 160 can be greater than about 0 atomic percent and less or equal to than about 25 atomic percent such as, for example, greater than about 1 atomic percent and less than about 20 atomic percent in one embodiment, greater than about 1 atomic percent and less than about 15 atomic percent in another embodiment, or greater than about 1 atomic percent and less than about 8 atomic percent in a further embodiment. It is noted that the concentration of tellurium, selenium, or both can vary through the thickness of the absorber layer 160. For example, when the absorber layer 160 comprises a compound including selenium at a mole fraction of x and tellurium at a mole fraction of 1-x (Se _x Tei- _x ), x can vary in the absorber layer 160 with distance from the first surface 162 of the absorber layer 160.

[0046] Referring still to FIG. 2, the absorber layer 160 can be doped with a dopant configured to manipulate the charge carrier concentration. In some embodiments, the absorber layer 160 can be doped with a group I or V dopant such as, for example, copper, arsenic, phosphorous, antimony, or a combination thereof. The total density of the dopant within the absorber layer 160 can be controlled. Alternatively or additionally, the amount of the dopant can vary with distance from the first surface 162 of the absorber layer 160.

[0047] According to the embodiments provided herein, the p-n junction can be formed by providing the absorber layer 160 sufficiently close to a portion of the photovoltaic device 100 having an excess of negative charge carriers, i.e., electrons or donors. In some embodiments, the absorber layer 160 can be provided adjacent to n-type semiconductor material. Alternatively, one or more intervening layers can be provided between the absorber layer 160 and n-type semiconductor material. In some embodiments, the absorber layer 160 can be provided adjacent to the buffer layer 150. For example, the first surface 162 of the absorber layer 160 can be provided upon the second surface 154 of the buffer layer 150.

[0048] Referring now to FIG. 4, in some embodiments, a photovoltaic device 210 can include a window layer 170 comprising n-type semiconductor material. The absorber layer 160 can be formed adjacent to the window layer 170. The window layer 170 can have a first surface 172 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 174 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the window layer 170 can be positioned between the absorber layer 160 and the TCO layer 20. In one embodiment, the window layer 170 can be positioned between the absorber layer 160 and the buffer layer 150. The window layer 170 can include any suitable material, including, for example, cadmium sulfide, zinc sulfide, cadmium zinc sulfide, zinc magnesium oxide, or any combination thereof.

[0049] Referring collectively to FIGS. 2 and 4, the photovoltaic device 100, 210 can include a back contact layer 180 configured to mitigate undesired alteration of the dopant and to provide electrical contact to the absorber layer 160. The back contact layer 180 can have a first surface 182 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 184 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the back contact layer 180 can be defined between the first surface 182 and the second surface 184. The thickness of the back contact layer 180 can be between about 5 nm to about 200 nm such as, for example, between about 10 nm to about 50 nm in one embodiment.

[0050] In some embodiments, the back contact layer 180 can be provided adjacent to the absorber layer 160. For example, the first surface 182 of the back contact layer 180 can be provided upon the second surface 164 of the absorber layer 160. In some embodiments, the back contact layer 180 can include binary or ternary combinations of materials from groups I, II, VI, such as for example, one or more layers containing zinc, copper, cadmium and tellurium in various compositions. Further exemplary materials include, but are not limited to, zinc telluride doped with copper telluride, or zinc telluride alloyed with copper telluride.

[0051] The photovoltaic device 100 can include a conducting layer 190 configured to provide electrical contact with the absorber layer 160. The conducting layer 190 can have a first surface 192 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 194 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the conducting layer 190 can be provided adjacent to the back contact layer 180. For example, the first surface 192 of the conducting layer 190 can be provided upon the second surface 184 of the back contact layer 180. The conducting layer 190 can include any suitable conducting material such as, for example, one or more layers of nitrogen- containing metal, silver, nickel, copper, aluminum, titanium, palladium, chrome, molybdenum, gold, or the like. Suitable examples of a nitrogen-containing metal layer can include aluminum nitride, nickel nitride, titanium nitride, tungsten nitride, selenium nitride, tantalum nitride, or vanadium nitride.

[0052] The photovoltaic device 100, 210 can include a back support 196 configured to cooperate with the substrate 110 to form a housing for the photovoltaic device 100. The back support 196 can be disposed at the opposing side 102 of the photovoltaic device 100. For example, the back support 196 can be formed adjacent to the conducting layer 190. The back support 196 can include any suitable material, including, for example, glass (e.g., soda-lime glass). In some embodiments, an encapsulation layer formed from an organosilicon material, as described further below, can also function as the back support 196.

[0053] Referring collectively to FIGS. 2, 4, and 5, manufacturing of a photovoltaic device 100, 210 generally includes sequentially disposing functional layers or layer precursors in a “stack” of layers through one or more thin film deposition processes, including, but not limited to, sputtering, spray, evaporation, molecular beam deposition, pyrolysis, closed space sublimation (CSS), pulse laser deposition (PLD), chemical vapor deposition (CVD), electrochemical deposition (ECD), atomic layer deposition (ALD), or vapor transport deposition (VTD). In some embodiments, VTD may be preferred for greater through put quality.

[0054] Manufacturing of photovoltaic devices 100, 210 can further include the selective removal of the certain layers of the stack of layers, i.e., scribing, to divide the photovoltaic device into 100, 210 a plurality of photovoltaic cells 200. For example, the serial scribes 202 can comprise a first isolation scribe 212 (also referred to as PI scribe), a series connecting scribe 214 (also referred to as P2 scribe), and a second isolation scribe 216 (also referred to as P3 scribe). The first isolation scribe 212 can be formed to ensure that the TCO layer 140 is electrically isolated between cells 210. Specifically, the first isolation scribe 212 can be formed though the TCO layer 140, the buffer layer 150, and the absorber layer 160 of photovoltaic device 100, or though the TCO layer 140, the buffer layer 150, the window layer 170, and the absorber layer 160 of photovoltaic device 200. The first isolation scribe 212 can be filled with a dielectric material 198.

[0055] Referring again to FIGS. 2 and 4, the series connecting scribe 214 can be formed to electrically connect photovoltaic cells 200 in series. For example, the series connecting scribe 214 can be utilized to provide a conductive path from the conductive layer 190 of one of the photovoltaic cells 200 to the TCO layer 140 of another of the photovoltaic cells 200. The series connecting scribe 214 can be formed though the absorber layer 160, and the back contact layer 180 of photovoltaic device 100, or through the window layer 170, the absorber layer 160, and the back contact layer 180 of photovoltaic device 200. Optionally, the series connecting scribe 214 can be formed though some or all of the buffer layer 150. Accordingly, the series connecting scribe 214 can be formed after the back contact layer 180 is deposited. The series connecting scribe 214 can then be filled with a conducting material such as, but not limited to, the material of the conducting layer 190.

[0056] The second isolation scribe 216 can be formed to isolate the back contact 190 into individual cells 210. The second isolation scribe 216 can be formed through the conductive layer 190, the back contact layer 180, and at least a portion of the absorber layer 160. The second isolation scribe 216 can be filled with a dielectric material 218.

[0057] Referring collectively to FIGS. 1 and 5, a parallel scribe 204 (also referred to as P4 scribe) can be formed to isolate groups 206 of cells 200 from one another. In some embodiments, each group 206 can comprise multiple photovoltaic cells 200 connected in series such as, for example, via the series connecting scribe 214. The parallel scribe 204 can be formed through the conductive layer 190, the back contact layer 180, the absorber layer 160, the buffer layer 150, the TCO layer 140, the barrier layer 130, and the window layer 170 (when present). According to the embodiments provided herein, each of the parallel scribe, 204, the first isolation scribe 212, the series connecting scribe 214, and the second isolation scribe 216 can be formed via laser cutting or laser scribing. In some embodiments, the parallel scribe 204 can be filled with a dielectric material.

[0058] Processing steps in manufacturing a device may be accomplished using a system with one or more processors. According to the embodiments described herein, a processor means any device capable of executing machine readable instructions. Accordingly, each of the one or more processors may be a controller, an integrated circuit, a microchip, a computer, or any other computing device. [0059] The one or more processors can be configured to execute logic or software and perform functions that control relative movement of a coating applicator and the layer stack, as well as the properties of the applicator, such as a coating flow rate or consistency. The one or more processors can be configured to execute logic or software and perform functions that control relative movement of a curing apparatus and the layer stack, as well as the properties of the curing apparatus, such as temperature or a photonic or a microwave intensity and duration. The one or more processors can be configured to execute logic or software and perform functions that control relative movement of a laser waveform and the layer stack, as well as the properties of the laser waveform. Additionally, the one or more processors can be communicatively coupled to one or more memory components that can store the logic and/or input received by the one or more processors. The memory components described herein may be RAM, ROM, a flash memory, a hard drive, or any device capable of storing machine readable instructions.

[0060] As used herein, the term“communicatively coupled” means that the components are capable of exchanging data signals with one another such as, for example, electrical signals via conductive medium, electromagnetic signals via air, optical signals via optical waveguides, and the like.

[0061] Embodiments of the present disclosure comprise logic that includes machine readable instructions or an algorithm written in any programming language of any generation (e.g., 1GL, 2GL, 3GL, 4GL, or 5GL) such as, e.g., machine language that may be directly executed by the processor, or assembly language, object-oriented programming (OOP), scripting languages, microcode, etc., that may be compiled or assembled into machine readable instructions and stored on a machine readable medium. Alternatively, the logic or algorithm may be written in a hardware description language (HDL), such as logic implemented via either a field-programmable gate array (FPGA) configuration or an application-specific integrated circuit (ASIC), and their equivalents. Accordingly, the logic may be implemented in any conventional computer programming language, as pre-programmed hardware elements, or as a combination of hardware and software components. The logic can be configured such that, when executed by the one or more processors, the system operates to automatically control relative movement of a curing apparatus and the layer stack, as well as the properties of the curing apparatus, such as a photonic or microwave intensity and duration. The logic can be configured such that, when executed by the one or more processors, the system operates to automatically synchronize relative movement between the laser waveform and the layer stack with modulation of parameters of the laser waveform.

[0062] Referring now to FIGS. 6A-F, embodiments are schematically depicted in cross section for a partly-formed photovoltaic device 600.

[0063] In FIG. 6A, the partly-formed photovoltaic device 600 comprises a layer stack 632 having a plurality of photovoltaic layers configured to produce current, as previously described for FIGS. 1-5. The layer stack 632, is disposed on a substrate 610. A suitable substrate 610 may include glass or other translucent materials. FIG. 6A shows an embodiment in which an encapsulation layer 601 covers top and side edges of the layer stack 632, contacting the layer stack back surface 634 and the layer stack side edge 635. In FIG 6A, the encapsulation layer 601 also contacts the front substrate 610 covering at least a portion of a substrate side edge 615.

[0064] FIG. 6B shows an embodiment in which an encapsulation layer 601 covers the top and side edges of the layer stack 632, contacting the layer stack back surface 634 and the layer stack side edge 635. In the embodiment depicted in FIG. 6B, the layer stack side edge 635 is inset from a substrate side edge 615 and the encapsulation layer 601 contacts an outer edge portion of a substrate back surface 614.

[0065] FIG. 6C shows an embodiment in which an encapsulation layer 601 covers the layer stack 632, contacting the layer stack back surface 634 and the layer stack side edge 635. In FIG 6C, the encapsulation layer 601 also contacts the front substrate 610 covering a substrate side edge 615 and a substrate front surface 612.

[0066] FIG. 6D shows an embodiment in which an encapsulation layer 601 covers the layer stack back surface 634 and other means, such as polymeric tape, are used as a side seal 637 to seal the side edge 635 of the layer stack 632.

[0067] FIG. 6E shows an embodiment in which an encapsulation layer 601 covers the top and side edges of the layer stack 632, contacting the layer stack back surface 634 and the layer stack side edge 635. In the embodiment depicted in FIG. 6E, the layer stack side edge 635 is inset from a substrate side edge 615 and the encapsulation layer 601 contacts an outer edge portion of a back surface 614 of the front substrate 610.

[0068] FIG. 6F shows an embodiment in which an encapsulation layer 601 covers the top and side edges of the layer stack 632, contacting the layer stack back surface 634, the layer stack side edge 635, and contacts the front substrate 610 covering a substrate side edge 615. In the embodiment depicted in FIG. 6F, the encapsulation layer 601 does not cover any portion of a front surface 612 of the front substrate 610.

[0069] FIGS. 6A-F are simplified for clarity. The substrate 610, as previously discussed, may include more than one layer and may include functional coatings such as a performance coating for ultraviolet or antireflective features. Thus, for example, the encapsulation layer may entirely cover, but not contact, a glass surface of a glass substrate, instead contacting a functional coating of the glass substrate along that surface.

[0070] In some embodiments, the encapsulation layer 601 covers and contacts the entirety of the side edge 635 of the layer stack 632 and also contacts 75-95% of the back contact layer 634. In some embodiments, the encapsulation layer 601 covers the entirety of the side edge 635 of the layer stack 632, but does not contact the entirety of the side edge 635. In some embodiments a side edge interlayer is between at least a portion of the side edge and a portion of the encapsulation layer, and the side edge interlayer contacts at least a portion of the side edge 635 of the layer stack 632 and also contacts the encapsulation layer 601.

[0071] In some embodiments, the encapsulation layer 601 contacts the entirety of the layer stack side edge and also contacts 75-95% of the back contact layer.

[0072] In some embodiments, the encapsulation layer 601 covers the layer stack 632, contacting a conducting layer of the layer stack back surface 634. In some embodiments, the encapsulation layer 601 contacts the conducting layer across an entire layer stack back surface 634. In some embodiments, the encapsulation layer 601 contacts the conducting layer across a portion of a layer stack back surface 634. In some embodiments, the encapsulation layer 601 contacts the conducting layer across a 50-95% of a layer stack back surface 634. In some embodiments, the encapsulation layer 601 contacts the conducting layer across a 70-90%, 80- 99%, or 85-95% of a layer stack back surface 634. In some embodiments, the encapsulation layer 601 covers and electrically insulates an adjoining surface region of the conducting layer along the layer stack back surface 634, while an exposed surface region of the layer stack back surface is not covered by the encapsulation, and the exposed region may electrically connect with or contact an electrical connector and the exposed region may be covered in whole or in part by an insulating material. In some embodiments, the encapsulation layer 601 contacts a back support across a portion of a layer stack back surface 634. In some embodiments, the encapsulation layer 601 forms a back support across a layer stack back surface 634. In some embodiments, the encapsulation layer 601 forms an electrically insulating layer across a layer stack back surface 634.

[0073] Referring now to FIG. 7, in some embodiments, a photovoltaic device may be formed with one or more leads or busbars that exit the side of a device. As also shown in Fig 7, an elastomer layer 780 and supporting back cover glass 790 may optionally be added on the encapsulation layer 601 of any of the described devices for additional strength and support. In the embodiment shown in FIG. 7, a simplified diagram shows the layer stack 632 formed on the substrate 610 and a bus bar 740 having an electrical connection exiting the side of the device, with the encapsulation layer 601 formed over the bus bar. An elastomer layer 780 is between and in direct contact with the encapsulation layer 601 and a back support 790. The back support 790 may be glass. The strengthening provided by the encapsulation layer can facilitate use of a thinner or lighter support. In other embodiments, the back cover glass and its associated elastomeric adhesive layer may be omitted.

[0074] Referring now to FIGS. 8-9 and 10A-D and the Examples below, methods of applying and curing an encapsulation material are described and illustrated. “Substrate” in these process steps include the entire PV device, not just the front glass onto which semiconductor layers are applied. Substrate preparation may involve cleaning the substrate and, optionally, a surface activation step that enhances binding to the surface. An oxygen plasma is an exemplary activation. Referring to FIGS. 8 and 10A-D, a substrate is prepared 810, areas are masked 825, and a coating is applied 830. A mask is placed over the back contact or conductive layer before the coating is applied. The coating is dried 840, the mask is removed 855, and the coating is cured 860 to form the encapsulation layer. Drying entails the evaporation of solvent such that the coating becomes solid or semi-solid. Drying speed may be modified by altering the drying conditions, such as decreasing drying time by using an air knife. Curing entails changes in chemical bonding structure of the encapsulation material. After curing, the device is cooled 875 and electrical connectors are applied 885. Prior to curing, the mask is removed, so that busbars or other electrical connections can be made through the masked region to the conductive layer. In some embodiments, the device is cooled to a temperature in a range of 20-60 C, or below 50 C before applying electrical connectors. The process of FIG. 8 is amenable to either a spray or roll coating process for applying the coating.

[0075] Referring to FIG 9, an alternate process is depicted that is amenable to spray coating or dip coating, but the height of the attached busbar prior to coating limits applicability with roll coating processes. A substrate is prepared 910, a busbar is applied 915, and the coating is applied 930. In this process, the busbar extends past the side edge of the device and remains uncoated so that conductive foils or other electrical connections can be made to the busbar near the edge of the device. The coating is dried 940 and cured 960. After curing, the device is cooled 975 and one or more lead foils or other electrical connectors may be applied 985.

[0076] Referring to FIGS. 10A-D, with reference to FIGS. 1-6, in an example process, a substrate 1000 including a layer stack 632 has been prepared with a region, 1010 on either end of the device masked off, using a polyimide tape. In the example shown, each region 1010a, 1010b has an area corresponding to a portion of conductive layer of a cell 200 on the back surface 1004 of the device. The coating is applied and then the masking is removed to expose the two exposed regions or openings through the coating to the conductive layer at the back surface of the layer stack. After the masking is removed, the coating is cured, forming a contiguous encapsulation layer 601 on the back surface 1004 of the device with gaps only in the selected exposed regions 1010a, 1010b. Double sided tape (DST) 1020 is applied along a center area of the device 1000 and over a portion of each region. A lead foil 1030 is applied to the DST for making electrical connection to the device. Busbars 1040a 1040b are applied over a portion of the lead foil and in electrical connection with the conductive layer of the respective exposed regions 1010a, 1010b.

[0077] Coating materials may include combinations of PSSQ or PSZ resins along with additives designed to enhance crosslinking. The resins may include cage structures (both open and closed) as described above as well as ladder structures and PSSQ or PSZ precursors having reactive silanols that may be assembled into oligomers or polymers of cage-like organo-silcon structures linked together. For example, coating formulations may include 50-95% of HardSil™- type AR or AP resins. Additives containing reactive groups such as alkoxy carboxyl, or amine groups may be present in the formulations at 1-50% (preferably 10-35% or 15-30%). Some specific additives may include Gelest types SST-3M01 (100% methyl R groups), SST-3P01 (100% phenyl R groups), or SST-MnPm (n% methyl and m% phenyl R substituents, with m and n varying from 10% to 90%).

[0078] In some embodiments, methods of curing include thermal curing in which heat is applied to the coating layer. In some embodiments the entire device is placed into a heated chamber. In some embodiments heat is directed to the coating layer using photonic curing or variable frequency microwave curing. Temperatures may be controlled to avoid damage to components of the device, in particular, if the encapsulation layer is applied over one or more busbars or lead foils, the maximum temperature and duration of curing may be adjusted. In some embodiments, the cure temperature does not exceed 380C and 90 minutes duration. In some embodiments, the cure temperature does not exceed 350C and 60 minutes duration. In some embodiments, the cure temperature does not exceed 330C and 75 minutes duration. In some embodiments, the cure temperature is maintained between 220-350C for a duration of

30-90 minutes. In some embodiments, the cure temperature is maintained between 220-350C for a period of 5-60 minutes. In some embodiments, the cure temperature is maintained between 270-330C for a duration of 5-90 minutes. In some embodiments, the cure temperature is maintained between 290-3 IOC for a duration of 15-90 minutes, or for a duration of 15-60 minutes.

Example: Roll coating and curing

[0079] Coating solution preparation:

[0080] In an appropriate container were assembled lOOg of HardSil™ AP (Gelest Inc.) polysilsesquioxane resin solution in propylene glycol monomethyl ether (PGME). The HardSil™ AP solution has a nominal concentration of 20 weight % solid resin. 300g of PGME (Sigma Aldrich >99.5% purity) was added to the container to dilute the resin concentration to 5 weight % and the resulting solution was filtered through a Fluoropore 0.5micron PTFE membrane filter (Merck Millipore, Germany) into a 500mL low particle amber bottle (Eagle Pitcher Inc.). The solution was stored at ambient temperature under a nitrogen atmosphere.

[0081] Substrate preparation:

[0082] A 100mm x 100mm square PV substrate (1) immersing the coupon in a bath of isopropyl alcohol (IP A) at ambient temperature and cleaning by ultrasonication (Branson 0.5 gallon Ultrasonic bath) for 30 seconds to remove surface contamination· (2) Residual IPA is removed by rinsing the coupon with deionized water in an OEMgroup PSC-108 spin rinse drier (SRD) and then dried by spinning at 1800rpm for 220 seconds. The coupons are then placed in a forced air oven (OF-02, JeloTech, Republic of Korea) at 105°C for up to 18 hours to remove adventitious moisture on the substrate surface.

[0083] The coupons are removed from the oven and cooled to ambient temperature. The surface to be coated is treated with an ambient pressure oxygen plasma (Enercon Dyne-A-Mite IT) to improve surface wetting of the coating solution. The water contact angle of the substrate decreases from 35°-45° to <10° (Easy Drop FM402Mk2, Kriiss, Germany). [0084] Kapton Polyimide tape was applied to two individual cells to create a nine (9) cell PV device with a nominal Voc of 5 V. The Kapton tape creates a masking element that excludes the PSSQ coating from the surface of two cells.

[0085] Coating:

[0086] The coating solution was applied to the glass substrate using a Biirkle CE Laboratory roll coater with a polyurethane rubber roller. The belt speed was 5 meters/minute, the roller gap over the substrate was 0.2mm, roller compression was 0.3mm and the roller rotational speed was 2 meters per minute. The doctor blade nip was 0.2mm. The wet film thickness was estimated at 1.5 microns.

[0087] Excess coating solution was removed by passing the coupon under an ambient temperature air knife (Leister) at a rate of lOmm/min. The coupons were then placed on a flat surface to dry for 60 minutes under ambient conditions. After 1 hours the Kapton tape was removed from the substrate to provide openings in the coating to provide electrical contact with bussing elements.

[0088] Thermal Cure:

[0089] The final thermal cure was performed in a Hengli belt furnace set at 330°C under ambient atmosphere. The belt speed of the oven was 75mm/minute. Coupons have a residence time in the furnace of 41 minutes.

Example: Spray coating and cure

[0090] Coating solution preparation:

[0091] Same as roll coating example

[0092] Substrate preparation:

[0093] A 100mm x 100mm square PV substrate (1) immersing the coupon in a bath of isopropyl alcohol (IP A) at ambient temperature and cleaning by ultrasonication (Branson 0.5 gallon Ultrasonic bath) for 30 seconds to remove surface contamination· (2) Residual IPA is removed by rinsing the coupon with deionized water in an OEMgroup PSC-108 spin rinse drier (SRD) and then dried by spinning at 1800rpm for 220 seconds. The coupons are then placed in a forced air oven (OF-02, JeloTech, Republic of Korea) at 105°C for up to 18 hours to remove adventitious moisture on the substrate surface. [0094] The coupons are removed from the oven and cooled to ambient temperature. The surface to be coated is treated with an ambient pressure oxygen plasma (Enercon Dyne-A-Mite IT) to improve surface wetting of the coating solution. The water contact angle of the substrate decreases from 35°-45° to <10° (Easy Drop FM402Mk2, Kriiss, Germany).

[0095] A 5mm busbar tape (Adhesives Research Inc. USA) was applied to two individual cells to create a nine (9) cell PV device with a nominal Voc of 5V. The busbar tape creates a masking element that excludes the PSSQ coating from the surface of two cells.

[0096] Coating:

[0097] The coating solution was applied to the substrate using a Devilbiss Finishline 4 spray gun. The spray conditions were 13cubic feet per minute (cfm) at 23psi using a 1.3mm fluid tip atomizer. The coating was applied in two passes, the coupon was rotated by 90 degrees between individual passes to improve the coating uniformity.

[0098] Excess coating solution was removed by passing the coupon under an ambient temperature Air knife (Leister) at a rate of lOmm/min. The coupons were then placed on a flat surface to dry for 60 minutes under ambient conditions.

[0099] Thermal Cure:

[00100] The final thermal cure was performed in a forced air oven (OF-02, JeloTech, Republic of Korea) at 220°C for 20 minutes. The samples were removed from the oven when the temperature had cooled to 100°C.

[00101] Lamination of back cover glass:

[00102] A 100mm x 100mm film of polyolefin elastomer interlayer (XUR-20, First Applied Materials, China) was deposed over the substrate such that the lead foil ribbon is exposed. A 100mm x 100mm piece of 3.2mm glass was placed on top of the XUR-2- film. On entry into the SLM laminator (NPC Incorporated , Japan), a vacuum of 105HPA is applied for 150 seconds to removed trapped air and then the device was heated to 160°C for 8 minutes under 500Hpa pressure.

[00103] Thermal Cure by Variable Frequency Microwave:

[00104] A coating comprising PSSQ was applied to a substrate. Curing was performed by applying heat by a MicroCure® variable frequency microwave instrument to heat the coating from room temperature, about 22°C, to 140°C and maintaining 140°C for 300 seconds. The temperature was then increased to 250°C and held at 250°C for 600 seconds. The variable frequency microwave instrument used microwave energy sweeps from 5.85 GHz to 6.65 GHz in 100 millisecond sweeps.

[00105] It should now be understood that the embodiments provided herein, relate to improved coating and encapsulation technology. This coating and encapsulation technology is a significant step towards replacing glass and polymer encapsulants, and enabling higher efficiency thin film cell technologies that are currently constrained by moisture degradation, O2 permeation, delamination, and other degradation mechanisms. The use of the described methods and structures for sealing and encapsulation provides options to reduce or replace the use of glass in photovoltaic modules. This may reduce the weight of modules, decrease transportation costs, and facilitate module installation·

[00106] According to embodiments provided herein, methods of manufacturing a photovoltaic device with an encapsulation layer are provided. Described methods provide for forming a moisture seal or barrier for a photovoltaic device and adhering a moisture barrier to a photovoltaic layer stack by applying a coating to at least a portion of a substrate layer stack of a photovoltaic device and curing the coating. In some embodiments, described methods provide for curing a film comprising PSSQ on a photovoltaic module. In some embodiments, described methods provide for adhering a moisture barrier to a photovoltaic device. In some embodiments, described methods provide for forming an encapsulation layer on a partially- formed photovoltaic device.

[00107] According to the embodiments provided herein, methods of forming an encapsulation layer on a partially-formed photovoltaic device are provided. In embodiments, the device may have a plurality of semiconductor layers forming a layer stack on a substrate. The method may include applying a coating over the layer stack and curing the coating, producing cross-linkage within the coating, thereby forming the encapsulation layer. In embodiments, the coating comprises a polysilsesquioxane (PSSQ) or a polysilazane (PSZ). In embodiments, the coating contacts and substantially covers a back surface of the layer stack, the coating contacts and covers a side edge of the layer stack, and no portion of the side edge is exposed, and the coating contacts the substrate to substantially encapsulate the layer stack.

[00108] According to the embodiments provided herein, an encapsulation layer on a partially formed photovoltaic device may include a plurality of semiconductor layers forming a layer stack on a substrate; and a coating over the layer stack. The coating may comprise a polysilsesquioxane (PSSQ) or a polysilazane (PSZ). The coating contacts and substantially covers a back surface of the layer stack. The coating contacts and covers a side edge of the layer stack, such that no portion of the side edge is exposed. The coating contacts the substrate to substantially encapsulate the layer stack. And the coating is cured to produce cross-linkage within the coating, and forming the encapsulation layer. In some embodiments the cure is a thermal cure.

[00109] According to the embodiments provided herein, methods of manufacturing a photovoltaic device with an encapsulation layer are provided. Described methods provide for forming a moisture seal or barrier for a photovoltaic device and adhering a moisture barrier to a photovoltaic layer stack by applying a coating to at least a portion of a substrate layer stack of a photovoltaic device, and thermally curing the coating.

[00110] In some embodiments, the method includes: drying the coating on the layer stack before the curing step.

[00111] In some embodiments, the method includes: masking a region of a back surface of the layer stack before applying the coating; and unmasking the region after applying the coating and before the curing step, wherein the region includes at least one electrical connection of the layer stack, and wherein the region defines an area on the back surface having a size in a range of 1% to 10% of the back surface.

[00112] In some embodiments, applying the coating is performed by an application method including: spray coating, meniscus coating, roll coating, dip coating, flow coating, curtain coating, slot die coating, or spin coating. In some embodiments, applying the coating comprises applying a single layer in one step.

[00113] In some embodiments, the curing step comprises at least one of: applying heat using a resistive heating oven, photonic curing, or variable frequency microwave curing. In some embodiments, the curing step comprises: exposing the coating to a curing heat temperature in a range between 220 C and 350 C for a period of 5 minutes to 90 minutes. In some embodiments, the curing step includes curing heat exposure for a period of 5 minutes to 90 minutes. In some embodiments the period is 5-45 minutes, 5-30 minutes, 5-25 minutes, 10-45 minutes, 10-30 minutes, 10-25 minutes, 15-60 minutes, 15-45 minutes, or 15-30 minutes. In some embodiments, the curing step is performed at a temperature in a range of 220 C to 330 C. In some embodiments, the curing step is performed at a temperature in a range of 270 C to 330 C, in a range of 290 C to 310 C, in a range of 220 C to 270 C, or in a range of 220 C to 300 C. [00114] In some embodiments, a thickness of the encapsulation layer following the curing step is 5% to 30% of a thickness of the coating following the applying step.

[00115] In some embodiments, at least a portion of the side edge of the layer stack forms a contiguous side edge with a side edge surface of the substrate, and the encapsulation layer covers 90-100% of the contiguous side edge of the layer stack and substrate.

[00116] In some embodiments, at least a portion of the side edge of the layer stack is inset from a side edge surface of the substrate, and the encapsulation layer covers 0-10% of the side edge surface of the substrate.

[00117] In some embodiments, the encapsulation layer covers 50-100% of a side edge surface of the substrate.

[00118] In some embodiments, the encapsulation layer covers 90-100% of a back surface of a photovoltaic module. In some embodiments, the encapsulation layer covers 90-99% of a back surface of a photovoltaic module. In some embodiments, the encapsulation layer does not cover a region of a back surface of the layer stack, wherein: the exposed region comprises an area of 1-10% of the back surface, and a busbar is located over or adjacent to the exposed region. The busbar may be in direct electrical and physical contact with at least a portion of the exposed region. In some embodiments a busbar makes electrical contact to a conductive layer of at least one cell of the layer stack at the exposed region. A junction box may electrically connect to a lead foil and a busbar. In some embodiments, a junction box covers a portion of the exposed region.

[00119] In some embodiments, the encapsulation layer comprises 5%-100%, by weight, PSSQ. In some embodiments, the encapsulation layer comprises 5%-100%, by weight, PSZ. In some embodiments, the encapsulation layer comprises 5%-100%, by weight, PSSQ and 5%- 100%, by weight, PSZ. In some embodiments, the encapsulation layer comprises 30%-70%, by weight, PSSQ and 30%-70%, by weight, PSZ. In some embodiments, the encapsulation layer comprises 40%-60%, by weight, PSSQ and 40%-60%, by weight, PSZ. In some embodiments, the encapsulation layer comprises a greater amount, by weight, of PSSQ than PSZ. In some embodiments, the encapsulation layer comprises 45%-75%, by weight, PSSQ.

[00120] In some embodiments, the coating layer comprises: PSSQ cage structures, PSSQ ladder structures, PSSQ precursors, and at least one of polymethylsilsesquioxane oligomer or polyphenylsilsesquioxane oligomer, in an amount of l%-50% by weight in the coating layer. [00121] In some embodiments, the curing step comprises forming cross-linkages within the coating by applying heat to promote condensation of silanols, whereby a percentage of closed cage structures in the encapsulation layer is between 10-70 percent. In some embodiments, following the curing step, an infrared spectroscopy absorption profile of the encapsulation layer produces absorption peaks at 1040 to 1070cm ¹ and 1120- 1160cm ¹ .

[00122] In some embodiments, an elastomeric interlayer is applied over the encapsulation layer and a back glass cover is applied over the elastomeric interlayer.

[00123] In some embodiments, the encapsulation layer protects the layer stack from significant damage due to environmental factors. In some embodiments, environmental factors include at least one of: moisture, dust, salt, chemicals, temperature changes, or mechanical abrasion.

[00124] In some embodiments the coating is applied over one or more busbars. In some embodiments the coating is applied over one or more lead foils. In some embodiments the cure is a thermal cure with curing temperature at a level that does not cause significant damage to underlying layers including any busbars or lead foils. In some embodiments, significant damage may be defined as a decrease in efficiency of greater than 15%.

[00125] In some embodiments, use of the described methods produces a device with no edge tape contacting a side edge of the layer stack. In some embodiments, no adhesive is in contact with the layer stack side edge. In some embodiments, no adhesive is in contact with the conductive layer of the layer stack. In some embodiments, the encapsulation layer is disposed between the conductive layer of the layer stack and a back support structure.

[00126] It is noted that the terms "substantially" and "about" may be utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation. These terms are also utilized herein to represent the degree by which a quantitative representation may vary from a stated reference without resulting in a change in the basic function of the subject matter at issue.

[00127] While particular embodiments have been illustrated and described herein, it should be understood that various other changes and modifications may be made without departing from the spirit and scope of the claimed subject matter. Moreover, although various aspects of the claimed subject matter have been described herein, such aspects need not be utilized in combination. It is therefore intended that the appended claims cover all such changes and modifications that are within the scope of the claimed subject matter.