Title:
PLL CIRCUIT, DEMODULATOR CIRCUIT, IC CARD, AND IC CARD PROCESSING APPARATUS
Document Type and Number:
WIPO Patent Application WO/2005/079032
Kind Code:
A1
Abstract:
A demodulator circuit for reproducing data sequence included in an input signal received via a desired transmission system, wherein an exclusive-OR (EX-OR) circuit (254Q,254I) phase compare a first oscillation output signal and a second oscillation output signal that is different in phase by 90 degrees [&pgr /2] from the first oscillation output signal, both of which are produced by an oscillator (252) and a variable frequency divider (253); a control direction deciding circuit (257) decides, based on the positive and negative of that phase comparison result, a control direction; an integrator circuit (258) integrates that control direction decision result for one period of the input signal; and a corrector circuit (259) performs, based on the phase comparison result, a correction for that integration result in such a manner that when the phase difference is [± &pgr /2], a predetermined control amount is given, whereby the corrected control signal outputted once a period is used to control the operation of the variable frequency divider (253).
Inventors:
ARISAWA SHIGERU (JP)
ZHANG CHENG (JP)
ZHANG CHENG (JP)
Application Number:
PCT/JP2005/002161
Publication Date:
August 25, 2005
Filing Date:
February 14, 2005
Export Citation:
Assignee:
SONY CORP (JP)
ARISAWA SHIGERU (JP)
ZHANG CHENG (JP)
ARISAWA SHIGERU (JP)
ZHANG CHENG (JP)
International Classes:
H03D3/24; H03L7/08; H03L7/087; H04L25/49; H04L27/22; (IPC1-7): H04L27/22; H03L7/08; H03L7/087
Foreign References:
| JPH11274919A | 1999-10-08 | |||
| JP2003319003A | 2003-11-07 | |||
| JP2001333055A | 2001-11-30 |
Attorney, Agent or Firm:
Koike, Akira (Yamato Seimei Bldg. 1-7, Uchisaiwai-cho 1-chom, Chiyoda-ku Tokyo 11, JP)
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