Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2000/000975
Kind Code:
A1
Abstract:
An A/D converter (30) samples an analog signal synchronously with a sampling clock from a VCO (70) to obtained sampled values. These sampled values are stored in a shift register (410). A code judging section (420) detects the positive/negative sign pattern (time-series code pattern) of the sampled values held in storage elements (S0 to S5) of the shift register (410) and stores the sampled values in predetermined register (431 to 434) according to the detected sign pattern. According to this, an arithmetic section (430) determines the phase difference between the analog signal and the sampling clock. The phase difference is fed to a VCO (70) through a D/A converter (50) and a loop filter (60).
Inventors:
AOKI HIROSHI (JP)
SUZUKI SHIRO (JP)
HORIGOME JUNICHI (JP)
CHIBA TAKAYOSHI (JP)
YAMAGUCHI SHIGEO (JP)
SUZUKI SHIRO (JP)
HORIGOME JUNICHI (JP)
CHIBA TAKAYOSHI (JP)
YAMAGUCHI SHIGEO (JP)
Application Number:
PCT/JP1999/003526
Publication Date:
January 06, 2000
Filing Date:
June 30, 1999
Export Citation:
Assignee:
ASAHI CHEMICAL IND (JP)
ASAHI CHEMICAL MICRO SYST (JP)
SONY CORP (JP)
AOKI HIROSHI (JP)
SUZUKI SHIRO (JP)
HORIGOME JUNICHI (JP)
CHIBA TAKAYOSHI (JP)
YAMAGUCHI SHIGEO (JP)
ASAHI CHEMICAL MICRO SYST (JP)
SONY CORP (JP)
AOKI HIROSHI (JP)
SUZUKI SHIRO (JP)
HORIGOME JUNICHI (JP)
CHIBA TAKAYOSHI (JP)
YAMAGUCHI SHIGEO (JP)
International Classes:
G11B20/14; H03L7/06; (IPC1-7): G11B20/14
Foreign References:
| JPH01296733A | 1989-11-30 | |||
| JPH0326113A | 1991-02-04 | |||
| JPH0765508A | 1995-03-10 |
Attorney, Agent or Firm:
Mori, Tetsuya (8th floor 7, Kanda-Kajicho 3-chome Chiyoda-ku Tokyo, JP)
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