Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2001/080426
Kind Code:
A1
Abstract:
A PLL circuit comprises means (3) for generating a plurality of reference signals (fR1-fR8) of different phases, a primary divider (30) for dividing the output signal (fVCO) from a voltage-controlled oscillator (29) by a factor N1, a secondary divider (31) for dividing the output (fV') from the primary divider by a factor N2, a separator circuit (32) for separating the output (Q1a, Q2a, Q3a) from the secondary divider into a plurality of feedback signals (fV1-fV8), and a phase comparator (12-19) for comparing the feedback signals with the reference signals to produce error signals (ER1-ER8). Since the PLL circuit performs phase comparison multiple times during one cycle of a reference signal, lock-up time decreases. An output signal is divided by only two dividers, i.e., the primary and secondary, rather than four or more used in the prior art.
Inventors:
SUMI YASUAKI (JP)
Application Number:
PCT/JP2001/001884
Publication Date:
October 25, 2001
Filing Date:
March 09, 2001
Export Citation:
Assignee:
SANYO ELECTRIC CO (JP)
TOKYO SANYO ELECTRIC CO (JP)
SUMI YASUAKI (JP)
TOKYO SANYO ELECTRIC CO (JP)
SUMI YASUAKI (JP)
International Classes:
H03K23/66; H03L7/087; H03L7/091; H03L7/191; H03L7/23; H03L7/089; (IPC1-7): H03L7/087
Foreign References:
| JPH07154252A | 1995-06-16 | |||
| JPH1022824A | 1998-01-23 | |||
| JPH08186488A | 1996-07-16 | |||
| JPH10135822A | 1998-05-22 |
Attorney, Agent or Firm:
Maeda, Minoru (Yoyogi 2-chome Shibuya-ku, Tokyo, JP)
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