Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2011/108186
Kind Code:
A1
Abstract:
Disclosed is a PLL circuit which is provided with: a frequency dividing means (11), which divides the frequency of the output of the PLL circuit; a phase detector (12), which detects the phase difference between a reference clock signal and the output signal of the frequency dividing means (11); a loop filter (13), which filters the output signals of the phase detector, and outputs the filtering results as digital values; a selector (15), which selects either a digital value or a fixed value; a digitally controlled oscillator (16), which performs oscillation at a frequency that corresponds to the value selected by the selector (15); and a control means (17), which instructs the selector (15) to select the fixed value until a start signal is received, and which, after receiving the start signal, instructs the selector (15) to select the digital value in edge timing of the reference clock signal, and instructs the frequency dividing means (11) to start outputting the signals.
Inventors:
YAMADA YUJI
KINOSHITA MASAYOSHI
SOGAWA KAZUAKI
KINOSHITA MASAYOSHI
SOGAWA KAZUAKI
Application Number:
PCT/JP2011/000339
Publication Date:
September 09, 2011
Filing Date:
January 24, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
YAMADA YUJI
KINOSHITA MASAYOSHI
SOGAWA KAZUAKI
YAMADA YUJI
KINOSHITA MASAYOSHI
SOGAWA KAZUAKI
International Classes:
H03L7/10; H03L1/02; H03L7/093
Foreign References:
| JP2007214790A | 2007-08-23 | |||
| JPH05129948A | 1993-05-25 | |||
| JPH0884074A | 1996-03-26 | |||
| JP2004080624A | 2004-03-11 | |||
| JPH02100518A | 1990-04-12 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims:
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