Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/241268
Kind Code:
A1
Abstract:
A PLL circuit (4) comprises: an oscillation circuit (5) that operates using a power source (VDD) of a semiconductor chip (2) making up a solid-state imaging device (3); a PLL (7) that provides control according to a parameter (FCW); a monitoring unit (8) that includes, in the monitoring target thereof, at least the voltage of the power source (VDD); and a correction unit (9) that corrects the parameter (FCW) on the basis of the monitoring result from the monitoring unit (8). The PLL (7) generates a PLL clock signal (PLLCLK), which is determined on the basis of the parameter (FCW) that was corrected by the correction unit (9) and a reference clock signal (REFCLK) that is obtained from an oscillation clock signal (OSCLK) of the oscillation circuit (5).
Inventors:
MATSUMOTO TOMOHIRO (JP)
MARUKO KENICHI (JP)
MARUKO KENICHI (JP)
Application Number:
PCT/JP2021/018361
Publication Date:
December 02, 2021
Filing Date:
May 14, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03L1/02
Domestic Patent References:
| WO2012101774A1 | 2012-08-02 |
Foreign References:
| JP2014052969A | 2014-03-20 | |||
| JP2014017804A | 2014-01-30 | |||
| JPH0575445A | 1993-03-26 |
Attorney, Agent or Firm:
SAKAI INTERNATIONAL PATENT OFFICE (JP)
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