PLL DEVICE - NIHON DEMPA KOGYO CO

Title:

PLL DEVICE

Document Type and Number:

WIPO Patent Application WO/2007/114501

Kind Code:

A1

Abstract:

In a PLL device for outputting a frequency signal from a voltage control oscillation unit in synchronization with a reference frequency signal from outside, it is possible to suppress frequency fluctuation even if a trouble is caused in the reference signal from outside. More specifically, a signal level of the reference frequency signal from outside is monitored. When the signal level is within a set range, PLL control is performed by using data on a phase difference formed by the phase difference data creation means. When the signal level is out of the set range, it is recognized that the signal supply has stopped or an error has occurred and PLL control is performed by switching to the data on the phase difference stored in the storage unit such as the latest data accumulated or a pre-generated data.

Inventors:

ONISHI NAOKI (JP)
WAKAMATSU SHUNICHI (JP)
SHIOBARA TSUYOSHI (JP)

Application Number:

PCT/JP2007/057693

Publication Date:

October 11, 2007

Filing Date:

March 30, 2007

Export Citation:

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Assignee:

NIHON DEMPA KOGYO CO (JP)
ONISHI NAOKI (JP)
WAKAMATSU SHUNICHI (JP)
SHIOBARA TSUYOSHI (JP)

International Classes:

H03L7/06; H03L7/14; H03L7/091; H03L7/093

Foreign References:

JPH10173642A	1998-06-26
JP2005109551A	2005-04-21
JP2004235858A	2004-08-19
JP2002505827A	2002-02-19
JP2002353807A	2002-12-06
US6282500B1	2001-08-28
US4672447A	1987-06-09

Other References: