Title:
PLL DUAL EDGE LOCK DETECTOR
Document Type and Number:
WIPO Patent Application WO/2012/058010
Kind Code:
A3
Abstract:
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.
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Inventors:
WANG XIAOYUE (US)
JAMAL SHAFIQ M (US)
JAMAL SHAFIQ M (US)
Application Number:
PCT/US2011/056097
Publication Date:
April 03, 2014
Filing Date:
October 13, 2011
Export Citation:
Assignee:
MARVELL WORLD TRADE LTD (BB)
WANG XIAOYUE (US)
JAMAL SHAFIQ M (US)
WANG XIAOYUE (US)
JAMAL SHAFIQ M (US)
International Classes:
H03K23/42
Foreign References:
| US7456661B2 | 2008-11-25 | |||
| US20080129352A1 | 2008-06-05 | |||
| US6130566A | 2000-10-10 | |||
| US7394322B2 | 2008-07-01 |
Other References:
See also references of EP 2633620A4
Attorney, Agent or Firm:
INGERMAN, Jeffrey et al. (1211 Avenue of the AmericasNew York, NY, US)
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