CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to the following co-pending applications, all of which are incorporated herein by reference in their entirety:

U.S. Application No. 13/840,478, filed March 15, 2013, entitled POLAR RECEIVER ARCHITECTURE AND SIGNAL PROCESSING METHODS; U.S. Application No. 13/839,462, filed March 15, 2013, entitled LNA WITH LINEARIZED GAIN OVER EXTENDED DYNAMIC RANGE; U.S. Application No. 13/840,379, filed March 15, 2013, entitled DIGITALLY CONTROLLED INJECTION LOCKED OSCILLATOR; and, U.S. Application No. 13/842,470, filed March 15, 2013, entitled SINGLE-BIT DIRECT MODULATION TRANSMITTER.

BACKGROUND OF THE INVENTION

[0002] Communications transceivers may utilize numerous architectures to recover data from a modulated carrier signal. These architectures include coherent demodulation, using either intermediate frequency conversion or direct-conversion receivers. Such receivers typically recover or regenerate the communications carrier signal using a phase-locked loop (PLL) and coherent demodulation. Recently, polar receiver architectures have been proposed that extract the modulation phase components from a received modulation signal without using a carrier recovery circuitry. However, the proposed polar receiver architectures and associated signal processing have deficiencies that result in poor performance and high bit error rates (BER). Accordingly, there is a need for improved polar receiver signal processing and architectures.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0003] The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed invention, and explain various principles and advantages of those embodiments.

[0004] FIG. 1 is a block diagram of a polar receiver in accordance with some embodiments.

[0005] FIG. 2 is a signal diagram of amplitude and phase information generated by a polar receiver in accordance with some embodiments.

[0006] FIG. 3 is a signal diagram of input and output signals associated with a polar receiver in accordance with some embodiments.

[0007] FIG. 4 is a circuit diagram of one embodiment of an injection locking oscillator in accordance with some embodiments.

[0008] FIG. 5 is a signal plot showing ILO signal relationships.

[0009] FIG. 6 is a block diagram of a portion of a polar demodulator circuit in accordance with some embodiments.

[0010] FIG. 7 is a flow chart of a method of calibrating a polar demodulator circuit in accordance with some embodiments.

[0011] FIG. 8 is a signal plot of a QPSK signal output recovered using a polar demodulator circuit in accordance with some embodiments.

[0012] FIG. 9 is a flow chart depicting a method of signal demodulation in accordance with some embodiments.

[0013] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

[0014] The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

DETAILED DESCRIPTION OF THE INVENTION

[0015] With reference to FIG. 1, a block diagram of a polar receiver 100 will be described in accordance with some embodiments. The injection signal Si _n j(t) 102, which is a received modulated signal having a variable phase component, is applied to an input node 103 of the second harmonic injection locked oscillator (ILO) 104 (also referred to herein as a harmonic ILO). The output signal of the harmonic ILO S _ou t,i(t) 106 at node 105 has a compressed variable phase component, as will be described below. The compressed variable phase signal 106 is applied to input node 109 of the fundamental injection locked oscillator ILO 110 (also referred to herein as a fundamental ILO), and undergoes a delay to generate the output signal S _ou t _,2 (t) 1 12 at output node 1 11. That is, S _ou t,i(t) 106 and S _ou t, ₂ (t) 1 12 are related by a time delay imposed by fundamental ILO 1 10. S _ou t,i(t) 106, which is the phase compressed signal, and S _o ut _,2 (t) which is the delayed phase compressed signal, are applied to mixer 1 14 to generate an output signal m ₂ (t) 1 16. The mixer output signal 116 is low pass filtered to remove the double frequency components present at the output of the mixer 114, to obtain an estimated phase derivative signal Ω(ί) 120. The injection signal Si _n j(t) 102 is also applied to the envelope detector 108 to generate and amplitude waveform A(t) 118.

[0016] With reference to FIG. 2, the output of the polar receiver is depicted as an amplitude signal A(t) 1 18, 202 and phase information 204 generated by integrating the estimated phase derivative signal Ω(ί) 120 from the polar receiver in accordance with some embodiments.

[0017] With reference to FIG. 3, the variable phase component 302 of a received modulated signal is compared against the estimated phase derivative signal 304 (or equivalently, the instantaneous frequency signal), and the recovered phase signal 306 obtained by integrating the instantaneous input frequency signal 304, in accordance with some embodiments. [0018] With reference to FIG. 4, an example of an injection locking oscillator 400 will be described. In one embodiment, the ILO 400 may be configured with a harmonic injection node at the common mode node 434 using FET 436. In an alternative embodiment the common mode node 421 may also be used for harmonic injection. In yet a further alternative embodiment both nodes 421 and 434 may be used to inject a harmonic locking signal. The tank circuit together with the cross- coupled transistor pair 426, 428, will oscillate and lock to a frequency associated with a harmonic of the injection signal. In one embodiment the harmonic is a 2nd harmonic, such that the output frequency at nodes 423, 425 will be one half the frequency of the injected signal. In the harmonic ILO embodiment the transconductance gain stage 409 is not necessary - is either switched off by a control circuit, or is not present. The resonance circuit 41 1 may include a tank circuit having variable capacitors 420, 422, and inductors 416, 418. In an alternative embodiment the tank circuit may take the form of an RC tank circuit, and include variable capacitors and resistors.

[0019] Alternatively the ILO 400 may be configured with a fundamental injection signal applied at nodes 402, 404, in a differential manner. Together with the transistor pair 410, 412, stage 409 provides a transconductance of the voltage input signal to a current signal to be injected at nodes 423, 425. The tank circuit together with the cross-coupled transistor pair 426, 428, will oscillate and lock to a frequency associated with the fundamental injection signal.

[0020] Variations and further details of ILOs are described more fully in co-pending application Attorney Docket 71604.US.01 filed March 15, 2013, entitled

DIGITALLY CONTROLLED INJECTION LOCKED OSCILLATOR.

[0021] In one embodiment, the polar receiver apparatus comprises a first ILO using harmonic injection to receive a modulated signal on the input having phase variations of a first range. The harmonic injection ILO may be similar to that shown in FIG. 4, but configured to use one or more of the common mode injection points 434, 421, while not having an injection signal on fundamental injection points 402, 404. The harmonic ILO generates an output signal at differential output nodes 414, 424 that restricts the range of phase variations to a range that may by one-half the first range. [0022] In an embodiment, the ILO 104 is a second-harmonic injection locking oscillator having an input node 103 that receives the modulated signal. The modulated signal may be provided by an analog front-end (AFE) signal processing circuit. The AFE may include a tuning function, or channel selection function.

Tuning or channel selection refers to the isolation of a desired signal at a desired frequency, also commonly referred to as a channel. Tuning or channel selection may also include isolating a signal of a predetermined bandwidth, where a first desired signal may be of a first bandwidth, and a second desired signal may have a different bandwidth.

[0023] The second harmonic ILO provides a phase-compressed signal at a compressed signal output node 105. That is, the second harmonic ILO is configured to receive at harmonic ILO input node 103 a modulated signal having a variable phase component with phase variations in a first phase range, and responsively generate, at the compressed output node 105, a phase-compressed signal having a compressed variable phase component in a compressed phase range being substantially one half the first phase range.

[0024] This relationship between phase changes associated with the input signal and corresponding phase changes in the output harmonic signal may be better understood with respect to FIG. 5. The effect of a π/2 change of phase in the input signal results in a π/4 change of phase in the output. In particular, input signal 506 (shown in dashed line) has twice the frequency of the output signal 508. As shown in plot (A), the input 506 and output 508 have a steady state alignment as can be seen generally with respect to the signal alignment at point 504, where both signals are initiating a downward swing from a DC or average value. Note that this particular alignment is depicted only for convenience of explanation, and the specific steady relationship between input and output signals may take a different value.

[0025] In intermediate plot (B) the input signal 516 is delayed by 90°, or π/2 radians, while ILO output signal 514 has not yet changed. The net phase relationship between input and output signals has therefore changed, as may be conveniently observed with reference to the signal alignment at point 518, where the signals align at the negative peaks, as compared to the alignment that previously occurred on the downward slope at 504. The change in phase of input signal 516 can be seen with reference to points 502 and 510, which is seen to be equal to π/2 as shown by 520. The phase change of input 516 may be the result of modulation of the input signal. While FIG. 5 depicts a discrete phase change, such as may occur in PSK signals, the properties of phase compression described herein apply as well to any other type of modulation where there is a varying phase component, including OFDM.

[0026] Plot (C) depicts the condition where the output signal 528 has relocked and has achieved its initial phase relationship with respect to input signal 526 as may be seen with reference to the signal alignment at point 524 (i.e., the signals are back in alignment as shown at initial point 504 in plot (A). A comparison of points 512 and 522, which are the peaks of the output signal before and after relocking, shows a change 530 of only π/4 radians in the output signal as a result of the input phase change 520 of π/2 radians.

[0027] Again with respect to FIG. 5, plots (D), (E) and (F) 550 depict initial, intermediate, and final signals plots, respectively, depicting a -π/2 radian phase change 558 of the input signal which can be seen by a comparison of the input signal peak points 552 and 554 before and after the phase change, respectively. The corresponding -π/4 radians output phase change 562 may be seen by comparing the peaks of the output signal at 556 before the ILO relocking and at 560 after the output has regained its steady state phase relationship to the input signal.

[0028] The second harmonic ILO of the polar receiver is therefore configured to receive a modulated signal having phase variations in a first range ±<p radians, and provide an output signal having a second range of phase variations equal to ± φ/2 radians. The apparatus may be configured to receive a modulated signal in the form of either a phase shift keying signal, a quadrature amplitude modulated signal, a single carrier signal, or an orthogonal frequency division multiplexed signal.

[0029] Again with respect to FIG. 1, the fundamental ILO has an input node connected to the compressed output node of the harmonic ILO. The fundamental ILO also has a delayed-output node, and is configured to generate, at the delayed output node, a phase-compressed signal having a delayed compressed variable phase component that is delayed relative to the compressed variable phase component. A mixer may then use the input and output of the fundamental ILO to generate an estimate of the derivative of the phase changes of the phase-compressed signal (and hence, an estimate of the original phase variations in the received modulated signal, as described more fully below).

[0030] One aspect of injection locking oscillators is referred to as a metastable state. The metastable state may result in the phenomena that when a phase change of the input signal occurs, the ILO may regain its locked condition by adjusting the phase of its output in a direction opposite to the input phase change until the steady state condition is achieved. For example, the output signal 514 may move to its final phase relationship shown by output signal 528 by momentarily increasing its frequency to advance its phase by π/4 radians, or, alternatively, by momentarily decreasing its frequency to retard its phase by -7π/4 radians. Thus, in some cases, a phase change in an input signal caused by a momentary increase in the input signal frequency may actually result in a momentary decrease in the output frequency to delay the phase of the output signal until the ILO is again locked. Such a phenomenon imparts an erroneous change in the frequency/phase characteristic of the ILO output signal that may cause errors when using an input and output of a fundamental ILO to generate an estimate of the derivative of the phase variations.

[0031] Note that the errors may occur when the phase change of the input is large enough so that the input-output ILO phase difference is greater than a phase difference associated with the metastable state. Because the metastable state is more likely to impart erroneous frequency or phase changes in the ILO output when the input phase change is larger, the phase compression obtained from the use of a second harmonic ILO as an initial stage in the polar receiver significantly reduces errors and improves performance of the receiver.

[0032] In a further embodiment, the second harmonic ILO and the fundamental ILO may be adjustable to obtain the desired characteristics or performance of the polar receiver. In an embodiment, the second harmonic ILO may be adjusted to select a desired signal having a predetermined carrier frequency. The adjustment to the ILO may be to change the free-running frequency f _r of the second harmonic ILO, such as by altering a capacitance of the ILO tank circuit. The polar receiver may include an ILO control circuit configured to measure a free running frequency f _r of the ILO after removing the injection input signal, such as by controlling a switch. The ILO control circuit may adjust a capacitance of the tank circuit until the free running frequency f _r has a desired relationship to the carrier signal f _c (or channel center frequency). The desired relationship may be that f _r is offset from f _c /2. The ILO control circuit may also adjust one or more parameters of the second harmonic ILO including an ILO injection coefficient a, a quality factor Q, and a capacitance of a tank circuit to adjust the free running frequency f _r .

[0033] The ILO control circuit may also be configured to adjust one or more parameters of the fundamental ILO to adjust an amount of delay associated with the delayed phase-compressed signal. The delay may be adjusted by adjusting one or more parameters including an injection coefficient a, a quality factor Q, and a free running frequency f _r . The injection coefficient may be adjusted by altering a transconductance stage at the ILO input, or by adding or removing parallel-configured signal injection node devices, or by altering bias signals within the ILO. The quality factor may be adjusted by altering a resistance value within the tank circuit. The free running frequency may be adjusted by altering a capacitance of the ILO tank circuit such as by a capacitor bank or varactor. In a further embodiment, the fundamental ILO may be configured to operate in a strong injection mode, as opposed to weak injection mode. Weak injection may be characterized by a low injection ratio, such as .1 (i.e., 10%). Strong injection may therefore include a range of injection coefficients a >.1. In a further embodiment, the strong injection mode may include a range of injection coefficients a >.5.

[0034] The characteristics of both the second harmonic ILO and fundamental ILO, including Q, f _r , and a may be adjusted according to the structures and methods described in co-pending application Attorney Docket 71604.US.01 filed March 15, 2013, entitled DIGITALLY CONTROLLED INJECTION LOCKED OSCILLATOR.

[0035] The mixer has a first input node connected to the compressed output node and a second input node connected to the delayed-output node. The mixer may be, for example, a Gilbert Cell, or other suitable signal frequency mixer. The mixer is configured to combine the phase-compressed signal and the delayed phase- compressed signal, and to output, at the mixer output node, a signal containing an estimated derivative of the variable phase component. Generally, a mixer will provide at its output a signal having a frequency equal to the sum of the input signal frequencies and a signal at a frequency equal to the difference of the input signal frequencies.

[0036] In the polar receiver architecture described herein, the sum frequencies are not of interest, so the receiver includes a filter configured to remove the higher- frequency components and to thus generate an estimated variable phase component signal from the estimated derivative of the variable phase component. To improve the characteristics of the estimated variable phase component from the mixer, the phase relationship between the two mixer inputs may be adjusted as described above by altering parameters of the fundamental ILO. The low-pass filtered output of the mixer may be monitored while the fundamental ILO is adjusted to determine a satisfactory operating point. In one embodiment, the ILO is injected with a steady-state signal (i.e., a carrier signal having no phase changes) and is adjusted until the mixer output has a reduced or otherwise acceptable DC offset.

[0037] In the polar receiver architecture, some embodiments are configured to receive modulated signals having amplitude, or signal envelope variations. Note that the second-harmonic ILO may be configured to generate a phase-compressed signal having substantially reduced amplitude variations relative to the received modulated signal. The envelope being of more constant magnitude will result in less amplitude- induce phase distortion in the output of the fundamental ILO.

[0038] In some embodiments, the polar received may include an amplitude detector configured to process the received modulated signal and to output a magnitude signal representative of the magnitude of the received modulated signal. In this way, the envelop of the signal may be preserved, and later re-combined with the estimated phase signal.

[0039] The polar receiver may also include a polar demodulation circuit configured to recover data information from the estimated variable phase component signal. In an embodiment, the demodulation circuit may be configured to first convert the polar information (amplitude and phase signals) into more conventional inphase and quadrature signal components, commonly referred to as I and Q signals. These conventional IQ signals may then be processed using well-developed signal processing techniques and architectures, which need not be reiterated herein.

[0040] With reference to FIG. 6 is a block diagram of a portion of a polar

demodulator circuit in accordance with some embodiments. In particular, FIG. 6 shows a block diagram of an example receiver 600. An input signal 601 is capture by the example receiver 600 and passed through a low noise amplifier (LNA) 602 and a polar receiver 604. One such suitable LNA is described in copending application Attorney Docket 71603.US.01 filed March 15, 2013, entitled LNA With Linearized Gain Over Extended Dynamic Range. Such an LNA provides appropriate adjacent channel rejection as well as amplification, as described more fully in the referenced application.

[0041] The output signal of the polar receiver 604 is provided as an input signal to a DC offset circuit 606 and as an input signal to the phase and amplitude alignment circuit 612. Further, the output of the DC offset circuit 606 is provided to a phase integral circuit 608. In addition, the output signal of the phase integral circuit 608 is provided as an input signal to the phase scaling circuit 610. Moreover, the output signal of the phase scaling circuit 610 is provided to the phase and amplitude alignment circuit 612. The phase and amplitude alignment circuit 612 provides an inphase (I) signal 614 and a quadrature (Q) signal 616.

[0042] The example receiver 600 further includes a timing circuit 618 that is provided the I and Q signals (614 and 616). The output signal of the timing circuit 618 is provided to the correlator circuit 620 that detects the maximum of the signal with respect to a Barker code correlation. Further, the output signal of the correlator circuit 620 is fed back to both the phase scaling circuit 610 and the phase and amplitude alignment circuit 612. The feedback may be used to adjust the scaling and/or the phase and amplitude alignment. In addition, the output signal of circuit 620 is provided to a frame synchronization circuit 622. Moreover, the output signals of the frame synchronization circuit 622 are provided to a demodulator/channel estimation circuit 624 to provide a receiver output signal 626.

[0043] In a further embodiment, an apparatus may comprise a phase derivative integration circuit configured to receive a phase derivative estimate signal; a phase mapping circuit configured to map the phase derivative estimate signal to angular values; an amplitude and phase alignment circuit configured to align the angular values and an envelope magnitude signal; and, an inphase signal and quadrature signal generator connected to the amplitude and phase alignment circuit. The apparatus may further comprise a correlation circuit configured to identify the presence of a Barker code within the inphase and quadrature signals.

[0044] FIG. 7 is a block diagram of an example method 700. The example method 700 includes phase scaling that may evaluate some number of discrete scaling values of the phase signal, as shown in block 702. In one embodiment 19 different values are used, but other numbers may be used. The scaling factors may be linearly spaced, or may have a nonlinear spacing. Because the phase information is presented as a signal amplitude such as a voltage signal, and yet must be converted to an I and Q channel, using for example a sine-cosine lookup table (LUT), the mapping between the voltage signal and the angular values must be established. In one embodiment, the phase variations may be analyzed for step transitions characteristic of most digital PSK signals, and then scaled appropriately by mapping the voltage transitions to those expected phase steps. In alternative embodiments, the scaling may be adjusted incrementally, using a binary tree search, or exhaustive search, and measuring the performance of the receiver accordingly. The iterative method may be evaluated based on the performance of the barker correlation circuit in embodiment where the received modulated signal includes barker coding (or other spreading codes that may provide a coding gain).

[0045] Because an incorrect scale (mapping of voltage to phase angle) may result in rotations of the desired signal points, a further embodiment may include a Barker correlation circuit configured with a plurality of correlators, each correlator testing for the presence of a sequentially rotated Barker sequence in the IQ signals. [0046] In a further embodiment, various combinations of phase scaling and amplitude and phase synchronization may be evaluated using the Barker correlator, and the scaling and synchronization offsets may be selected that provide a maximum barker correlation value. In yet another embodiment, the MMSE (minimum mean square error) of a phase difference between training data and estimated received data to search for a suitable phase scaling and synchronization between the amplitude and phase signals.

[0047] The example method 700 further includes synchronizing (i.e., shifting in time) of the amplitude and phase (A&P) of the signal, as shown in block 704, to evaluate the performance of the receiver using different alignments of these signals. In one embodiment, various time offsets are set in an iterative or exhaustive fashion, and the performance of the Barker correlation circuit is used to evaluate a best-performing time offset. In a further embodiment, a correlation may be run against the phase signal to identify the presence of a predetermined phase characteristic of a

synchronization sequence, and a second correlation may be performed on the envelope/amplitude signal, with the results being used to align the signals accordingly. In a further embodiment, a coarse alignment may be performed using separate amplitude and phase correlations followed by a finer alignment using an iterative procedure.

[0048] In one embodiment, the example method 700 includes eight 1 1 -Mbps data streams, as shown in block 706, which may 8 samples per symbol (or chip) period. A separate Barker correlation may performed on each of the eight 11 -Mbps data streams, as shown block 708. In some embodiments, the Barker correlation may be fed back to the phase scaling module, amplitude and phase synchronization module, and the eight 1 1-Mbps data streams.

[0049] With reference to FIG. 8, a signal plot of a QPSK signal output recovered using a polar demodulator circuit as described herein is shown.

[0050] Now, with reference to the flow chart of FIG. 9, an embodiment of a method 900 of signal demodulation will be described. In an embodiment the method 900 comprises: receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit. The method of generating the estimated phase signal may comprise integrating the estimated phase derivative signal. The method of mapping the estimated phase signal to an angular value may be based on identifying discrete levels within the estimated phase signal. The discrete levels may be determined by a modulation type. The method of converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value includes using a sine/cosine look up table. The method may further comprise receiving an envelope magnitude signal, and wherein converting the estimated phase signal to an inphase signal and a quadrature signal is further based on the envelope magnitude signal. In an embodiment, the results from the LUT for the sine and cosine values may be fed to multipliers to multiply the values by the envelope magnitude. The method of mapping the estimated phase signal to an angular value may be done iteratively and a demodulator performance may be evaluated at each iteration. The method of demodulator performance evaluation may be based on a IQ correlator processing the inphase signal and quadrature signal. The IQ correlator may be a Barker sequence correlator.

[0051] The method may further comprise aligning the envelope magnitude signal and the estimated phase signal.The method of aligning the envelope magnitude signal and the estimated phase signal may comprise iteratively adjusting an alignment and measuring the demodulator performance. The method of evaluating the demodulator performance may be based on a IQ correlator processing the inphase signal and quadrature signal. The method of aligning the envelope magnitude signal and the estimated phase signal may comprise performing a correlation on the estimated phase signal to identify a predetermined phase signal, and performing a correlation on the envelope magnitude signal to identify a predetermined magnitude signal, and aligning the envelope magnitude signal and the estimated phase signal based on the correlations.

[0052] The method may further comprise removing a DC offset from the estimated phase signal, or from the estimated phase derivative signal. The method may include providing the DC offset value to an ILO control circuit. The method may further comprise determining a sampling instant using a set of parallel correlators operating on different phases of a time-decimated sample stream. The method may include sampling the estimated phase derivative signal is sampled or the estimated phase signal.

[0053] In the foregoing specification, specific embodiments have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings.

[0054] The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

[0055] Moreover in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," "has", "having," "includes", "including," "contains", "containing" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises ...a", "has ...a", "includes ...a", "contains ...a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms "a" and "an" are defined as one or more unless explicitly stated otherwise herein. The terms "substantially", "essentially", "approximately", "about" or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non-limiting embodiment the term is defined to be within 10%, in another embodiment within 5%, in another embodiment within 1% and in another embodiment within 0.5%. The term "coupled" as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is "configured" in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

[0056] It will be appreciated that some embodiments may be comprised of one or more generic or specialized processors (or "processing devices") such as

microprocessors, digital signal processors, customized processors and field programmable gate arrays (FPGAs) and unique stored program instructions (including both software and firmware) that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of the method and/or apparatus described herein. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used.

[0057] Accordingly, some embodiments of the present disclosure, or portions thereof, may combine one or more processing devices with one or more software components (e.g., program code, firmware, resident software, micro-code, etc.) stored in a tangible computer-readable memory device, which in combination form a specifically configured apparatus that performs the functions as described herein. These combinations that form specially programmed devices may be generally referred to herein "modules". The software component portions of the modules may be written in any computer language and may be a portion of a monolithic code base, or may be developed in more discrete code portions such as is typical in object-oriented computer languages. In addition, the modules may be distributed across a plurality of computer platforms, servers, terminals, and the like. A given module may even be implemented such that separate processor devices and/or computing hardware platforms perform the described functions. [0058] Moreover, an embodiment can be implemented as a computer-readable storage medium having computer readable code stored thereon for programming a computer (e.g., comprising a processor) to perform a method as described and claimed herein. Examples of such computer-readable storage mediums include, but are not limited to, a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory) and a Flash memory. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.

[0059] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.