Title:
POWER AMPLIFICATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/100518
Kind Code:
A1
Abstract:
This power amplification circuit (10) comprises a power amplifier (11 and/or 12) configured so as to amplify a high-frequency signal, a power supply voltage terminal (112) connected to the power amplifier (11 and/or 12), and a bypass capacitor (C1) connected between the ground and a power supply voltage path (P1) for linking the power supply voltage terminal (112) and the power amplifier (11 and/or 12). A power supply voltage (VDET) that can be varied to a plurality of discrete voltage levels within one frame of the high-frequency signal is supplied to the power amplifier (11 and/or 12) via the power supply voltage terminal (112). The capacitance of the bypass capacitor (C1) is 1.4 nanofarads or greater.
Inventors:
NOGUCHI YUUMA (JP)
TAKENAKA KIICHIRO (JP)
ARAMATA TOMOHIDE (JP)
KOGURE TAKESHI (JP)
WADA TAKAYA (JP)
TAKENAKA KIICHIRO (JP)
ARAMATA TOMOHIDE (JP)
KOGURE TAKESHI (JP)
WADA TAKAYA (JP)
Application Number:
PCT/JP2022/039129
Publication Date:
June 08, 2023
Filing Date:
October 20, 2022
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H04B1/04; H03F1/02; H03F3/24
Domestic Patent References:
| WO2009072251A1 | 2009-06-11 |
Foreign References:
| US20210211107A1 | 2021-07-08 | |||
| US20120269240A1 | 2012-10-25 | |||
| JP2015507452A | 2015-03-05 | |||
| JP2012175286A | 2012-09-10 | |||
| JP2016201787A | 2016-12-01 |
Attorney, Agent or Firm:
YOSHIKAWA, Shuichi et al. (JP)
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