[0001] This description relates generally to test systems and methods, and more particularly to testing power converter circuits.

BACKGROUND

[0002] Automatic testing equipment (ATE) has been developed to test a wide range of electronic devices including integrated circuits (ICs), System-on-Chip (SoC) and printed circuit boards. In some examples, design for testability (DFT) can also be incorporated into electronic devices to add testability features to such devices. The DFT features facilitate designing and implementing tests, which can be driven by ATE, to ensure that the product contains no production defects. In some types of ICs and SoCs, such as those configured to implement power supplies, some ATE testing methods can increase the risks of electrical overshoot and/or undershoot. In other testing paradigms, which might reduce the risk of electrical overshoot and/or undershoot, test time can increase and/or testing might not evaluate the circuitry in a holistic manner.

SUMMARY

[0003] One example includes automatic test equipment (ATE) circuitry having a test input and a test output. The test input is adapted to be coupled to a digital output of a power converter integrated circuit (IC). The test output is adapted to be coupled to a voltage output of the power converter IC. The ATE circuitry also includes a level shifter, a buffer, pull-up circuitry and a filter. The level shifter has a shifter input and a shifter output, in which the shifter input is coupled to the test input. The buffer has a buffer input coupled to the shifter output. The pull-up circuitry is coupled to the buffer input, and the pull-up circuitry is configured to supply a voltage sufficient to enable operation of circuitry in the power converter IC. The filter has an input coupled to the buffer output and a filter output coupled to the test output.

[0004] Another example described herein provides a method that includes connecting a circuit path of automatic test equipment (ATE) circuitry between a digital output terminal and a voltage output terminal of a power converter integrated circuit (IC). The circuit path includes a level shifter, a buffer and a filter network coupled in series between the digital output terminal and the voltage output terminal. The method also includes providing a pull-up supply voltage to an input of the buffer of the ATE circuitry to enable operation of the power converter IC. The method also includes controlling the power converter IC to route a pulse width modulation control signal to the digital output terminal. The PWM control signal is provided by a control loop circuit of the power converter IC responsive to the signal provided by the ATE circuitry at the voltage output terminal. [0005] Another example described herein provides a test system that includes a boost power converter integrated circuit (IC) and automatic test equipment (ATE). The power converter integrated circuit (IC) has a digital output and a voltage output, and the ATE has a test input coupled to the digital output and a test output coupled to the voltage output. The power converter IC includes an output stage coupled to the voltage output. The power converter IC also includes a control loop configured to provide a pulse width modulation (PWM) control signal to control the output stage responsive to a voltage at the voltage output. The power converter IC can also include a multiplexer configured to route the PWM control signal to the digital output responsive to a test mode control signal representative of a test mode. The ATE includes a level shifter, a buffer and a resistor-capacitor (RC) network coupled in series between the test input and the test output. The buffer is configured to drive the voltage output of the power converter IC through the RC network. The AT also includes pull-up circuitry coupled to an input of the buffer and configured to supply a voltage sufficient to enable operation of circuitry in the power converter IC during the test mode. BRIEF DESCRIPTION OF THE DRAWINGS [0006] FIG. 1 depicts an example of a testing system.

[0007] FIG. 2 depicts another testing system showing examples of an integrated circuit and automatic testing equipment.

[0008] FIG. 3 depicts another testing system showing another example of automatic testing equipment.

[0009] FIG. 4 is a graph showing examples of a power converter output and an output of test circuitry implemented in automatic testing equipment.

[0010] FIG. 5 is a flow diagram showing an example of a method for testing a power converter circuit.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0011] This description relates generally to test systems and methods, and more particularly to testing power converter circuits, such as switching regulators. As described herein, automatic testing equipment (ATE) is adapted to be coupled to a power converter circuit, such as implemented on an integrated circuit (IC). The ATE is configured to test internal control loop circuitry of the power converter circuit, such as to detect production defects. The testing can be considered a pseudo-closed loop approach because it encompasses features from both open loop and closed loop testing methods. For example, the pseudo-closed loop approach described herein implements testing in a closed loop manner that bypasses the power stage of the power converter circuit. In this way, the control loop circuitry is tested similar to an application without high current and without fast transitions on the output terminal (e.g., a switching node).

[0012] As an example, the ATE has a test input and test output adapted to be coupled to a digital output and a voltage output, respectively, of the power converter circuit (e.g., an IC). The ATE includes test circuitry coupled between the test input and test output that, when coupled to the power converter circuit, is configured to emulate a power stage of the converter. For example, the ATE test circuitry includes a level shifter, a buffer and a resistor-capacitor (RC) filter network coupled in series between the test input and test output. The buffer is configured to drive the voltage output of the power converter circuit through the RC filter network, which improves loop stability. The ATE test circuitry also includes pull-up circuitry configured to supply a voltage to an input of the buffer sufficient to enable (e.g., kick-start) operation of circuitry in the power converter circuit during testing. The ATE test circuitry is designed to allow testing of the power converter circuits at operating frequency. Additionally, the test circuitry can be implemented without using an inductor, which reduces the risk of overshoot and undershoot. Thus, the testing systems and methods described herein can help reduce overall testing time and improve accuracy over many existing testing approaches.

[0013] FIG. 1 depicts an example of a testing system 100, shown as including a power converter IC 102 and an ATE 104. In the example of FIG. 1, the ATE 104 has a test input 106 and a test output 108, in which the test input 106 is coupled to a digital output 110 and the test output 108 is coupled to a voltage output 112 of the power converter IC 102. In other examples, the ATE 104 can be coupled to a number of instances of the power converter IC for testing in parallel. The ATE 104 can be coupled to the IC 102 through an interface circuit, such as a handler interface board. [0014] The ATE 104 includes test circuitry 114 coupled between the test input 106 and the test output 108, which is configured to emulate the power stage of the power converter IC 102. For example, the ATE test circuitry 114 includes a level shifter 116, a buffer 118 and a filter 120 coupled in series between the test input 106 and the test output 108. The level shifter 116 has an input coupled to the test input to receive a digital signal from the digital output 110. The level shifter is configured to shift the level of the digital signal and provide a level-shifted signal to an input of the buffer 118.

[0015] A pull-up circuit 122 is also coupled to the buffer input. The pull-up circuit 122 is configured to supply a voltage at the buffer input so the buffer 118 drive a voltage through the filter 120 to the test output 108 (coupled to the output 112 of the converter IC). In an example, the level shifter 116 or other circuitry in test circuitry 114 is configured to generate a DC voltage at the buffer input, which is pulled up by pull-up circuit 122. When a test mode is entered (e.g., automatically or responsive to a user input), the level shifter 116 does not yet provide a voltage and the voltage at the buffer input is sufficient to power circuitry of the IC 102 for testing purposes. Thus, the buffer 118 is configured to drive the voltage output 112 based on the voltage supplied by the circuit 122 to enable operation of circuitry in the power converter IC 102 during testing. The filter 120 can be implemented as an RC network such as configured as a low-pass filter to stabilize the test signal supplied to the test output 108. Responsive to the buffer driving the voltage output 112, as described herein, the circuitry in the power converter IC 102 is configured in a test mode and supplies a digital PWM signal at the digital output 110, which is received at the test input 106. The level shifter 116 is configured to amplify the digital PWM signal, and an amplified version of the PWM signal is supplied to the buffer input.

[0016] In the example of FIG. 1, the power converter IC 102 is shown as including an output stage 124 and a control loop 126. For example, the output stage 124 can include an arrangement of power switches (e.g., field effect transistors (FETs)) and drive circuitry configured to supply a regulated output voltage VOUT at 112 responsive to a PWM control signal generated by the control loop 126. The control loop 126 can include an arrangement of comparators, logic and other circuitry configured to generate the PWM control signal responsive to a reference voltage and the output voltage VOUT. The control loop 126 can implement additional voltage mode control and/or current mode control depending on application requirements and the converter topology.

[0017] As a further example, the power converter IC 102 includes DFT control 128. The ATE 104 can include measurement and control circuitry 130 configured to program the DFT control 128 to enter the test mode. The DFT control 128 can implement respective controls of the power converter IC 102 to enable testing of the control loop 126, as described herein. For example, the DFT control 128 is configured to disable switching of the output stage 124 during the test mode, such as by forcing output switches of the output stage to known fixed states during testing to configure the voltage output 112 to a high impedance state so that it can be driven by the test circuitry 114 . The DFT control circuitry 128 can also be configured to route the internally generated PWM control signal to the digital output 110 during the test mode. The measurement and control circuitry 130 can also be coupled to test output 108 to measure the output voltage VOUT and coupled to test input 106 to measure characteristics of the PWM signal during the test mode. The ATE 104 can also be configured to perform a variety of other testing, evaluating and detecting defects in the IC 102. For example, by measuring the output voltage VOUT at 112 and ensuring it is stable during testing, the systems and methods implemented by the ATE 104 can also indirectly confirm the operation of the control loop.

[0018] FIG. 2 depicts another testing system 200 that includes a power converter IC 202 and an ATE 204. In the example of FIG. 2, the power converter IC 202 is implemented as a boost regulator that includes an output stage 206 and control loop circuitry 208. In other examples, the IC 202 to be tested configured to implement one or more other types of power converter circuit topologies (e.g., buck, buck boost, etc.). During normal operation of the IC 202, the output stage 206 thus is configured to provide a regulated output voltage VOUT at an output 210 in response to a PWM control signal provided by the control loop circuitry 208.

[0019] The ATE 204 includes test circuitry 212 coupled between test input and output terminals 214 and 216. The test output terminal is adapted to be coupled to the output 210 and the test input 214 is adapted to be coupled to a digital output 218 of the power converter IC 202. The test circuitry 212 can be implemented according to the examples described herein (see, e.g., FIGS. 1, 3 and 5). The test circuitry 212 of the ATE 204 is configured to emulate a boost power stage, including the output stage 206 of the boost regulator 202, by providing a voltage at test output 216 responsive to a digital PWM signal received at the test input 214. In other examples, the ATE 204 can be configured to emulate other types of output stage circuits.

[0020] The control loop circuitry 208 is configured to generate the PWM control signal at an output 220 responsive to the voltage at 210. For example, the control loop circuitry 208 includes a voltage divider 222 (e.g., a resistor divider) coupled to the output terminal 210. An output of the voltage divider 222 is coupled to an inverting input of an error amplifier 224. The voltage divider 222 is configured to supply a feedback signal representative of the output voltage VOUT at 210. A reference voltage (VREF) is supplied (e.g., a DC voltage from a reference signal generator) to a non-inverting input of the error amplifier 224. The error amplifier 224 is configured to amplify a difference between the output voltage VOUT and the reference voltage VREF to produce an ERROR signal, shown as VERR, for commanding a change in the output voltage VOUT toward the desired reference voltage VREF. An RC filter can be coupled to the output of the error amplifier 224, such as configured to perform low-pass filtering on the error signal VERR. The output of the error amplifier 224 is coupled to a first input of a summing block 226.

[0021] A ramp voltage generator 230 has an output coupled to a second input of the summing block 226. The ramp voltage generator 230 is configured to provide a ramp voltage signal VRAMP. The summing block 226 has an output coupled to a non-inverting input of a comparator 228. The summing block 226 is configured to provide respective summing signal VCTRL to the input of a comparator 228 based on VERR and VRAMP. A current sensor 232 is configured to measure current at a switching voltage supply terminal 244 (e.g., switching node SW). For example, the current sensor 232 has an output coupled to the inverting input of the comparator 228. The current sensor 232 is configured to provide a control voltage signal VISNS to the inverting input that is representative of the current at the SW node. The comparator 228 is configured to provide a PWM signal (e.g., an analog PWM signal) at a comparator based on the sensed current signal VISNS and summing signal VCTRL. The control loop 208 can also include logic 234 coupled to receive the PWM signal at the comparator output. The logic is configured to generate the digital PWM control signal at 220 based on the comparator output signal and a clock signal (CLK). The output 220 is coupled to an input of multiplexer 236 and to drive logic 238 of the output stage 206.

[0022] The drive logic 238 is configured to provide drive signals to control output FETs 240 and 242. In the example of FIG. 2, the FET 240 is a high-side FET coupled between the switching voltage supply terminal 244 and the output terminal 210. The FET 242 is coupled between the switching supply terminal 244 and a ground terminal of the IC 202, shown as PGND. For example the FET 240 is a p-channel FET and the FET 242 is an n-channel FET. Other types of switch devices can be used in other examples. The drive logic 238 is configured to provide the low-side drive signals to a buffer 248, which is coupled between the drive logic and the gate of the FET 242. The drive logic 238 is configured to provide the high-side drive signals to an inverter 250, which is coupled between the drive logic and the gate of the FET 240. [0023] The power converter IC 202 also includes a DFT control register 252 having one or more programmable register entry. For example, the DFT control register 252 has an input coupled to a DFT program terminal 254 of the IC 202. The ATE 204 (or other device) can be coupled to the terminal 254 to program one or more entries of the DFT control register 252. For example, the DFT control register 252 can be programmed by the ATE (or other hardware) through a communication bus (e.g., inter-integrated circuit (I2C) or serial peripheral interface (SPI) or other common communication bus). As an example, the DFT control register 252 is configured to enter a test mode and implement respective control function for the power converter IC 202 responsive to a testing program signal at 254. For example, the DFT control register 252 has an output coupled to a control input of the drive logic 238 and another output coupled to a control input of the multiplexer 236. Responsive to entering the testing program signal, the DFT control register 252 controls the state of the power converter device, such as by configuring the drive logic 238 to disable switching of the output stage 124 so no switching occurs at the SW node 244 during the test mode. For example, the drive logic 238 can force the high-side FET 240 to an on state and force the low-side FET 242 to an off state. The DFT control register 252 can also configure the multiplexer 236 to route the PWM control signal provided at 220 to the digital output 218 responsive to the control signal during the test mode. Thus, during testing, the test circuitry 212 of the ATE, which is configured to emulate the (now disabled) output stage 206, processes the digital PWM signal at 218 to provide a respective output signal VOUT at 216, 210. The control loop 208 is configured to adjust the PWM control signal responsive to the output signal VOUT at 216, 210 and thereby regulate the output signal VOUT at 216, 210 based on the reference voltage VREF. Because the output voltage VOUT is measured in a closed loop manner, the settling time is small compared to the test time for a typical open loop test.

[0024] In examples where the boost regulator IC 202 is configured to implement multiple output voltages, the ATE 204 and/or DFT control circuitry on the IC can step through register settings for generating and regulating to each of the respective output voltage settings. Measurement circuitry on the ATE 204 can further be configured to measure and record the voltages on the output 210 over the range of respective output voltage settings. If a device has many settings to be tested these can be tested in a single mixed signal pattern by writing register values to step through the output voltages while simultaneously capturing the measurements at VOUT. Advantageously, the entire closed loop signal chain of the power converter IC 202 can be exercised and tested at operating frequency in a pseudo-closed loop approach described herein while the output stage is disabled. In some examples, because the power stage is bypassed for the pseudo-closed loop measurement, the ATE 204 (or other testing equipment) can be configured to test the power output stage 206 separately, such as in a separate open-loop test. In an example open loop test, the DFT control register 252 can change the test mode so that traditional open loop tests, such as drain- source on resistance (RDSon) and input current limit (ILIM) can be performed (e.g., through SW to VOUT and VOUT to GND connections).

[0025] FIG. 3 depicts another testing system 300 that includes a power converter IC 302 and an ATE 304. The power converter IC 302 can be implemented according to the examples described herein (see, e.g., FIGS. 1, 2 and 5).

[0026] The ATE 304 includes test circuitry 306 coupled between a test input 308 and the test output 310. As described herein, the test circuitry 306 is configured to emulate a power stage of the power converter IC 302, such as stage 124 or 206. For example, the ATE test circuitry 306 includes a level shifter implemented as a common source amplifier. The common source amplifier includes a FET 312 having a gate coupled to the test input, source coupled to ground, and a drain coupled to a voltage VS through a resistor R1. The drain provides an output 314 of the common source amplifier configured to provide a switching signal SW. In the example of FIG. 3, a filter 316 is coupled between the output 314 and an input of a buffer 320. The filter 316 can include a resistor-capacitor network configured to filter the switching signal SW to provide filtered voltage VC at the buffer input. The filter 316 can be configured to provide the filtered voltage VC as a DC voltage at the buffer input.

[0027] A pull-up circuit 322 is also coupled to the buffer input. The pull-up circuit 322 includes a diode D1 coupled between the buffer input and a control voltage of the IC 302, shown as VCCA. The pull-up circuit 322 is configured to supply a voltage at the buffer input at level sufficient to enable initial operation of the power converter IC (e.g., to kick-start regulation) responsive to entering the test mode. A clamping circuit 324 is also coupled to the buffer input. For example, the clamping circuit 324 includes a Zener diode Z1 coupled between the buffer input and ground. The clamping circuit 324 is configured to limit a maximum voltage VC at the buffer input, such as a maximum voltage that is greater than regulated voltage of the power converter IC 302.

[0028] The buffer 320 can include an operational amplifier having a non-inverting input configured to receive the filtered signal VC and an inverting input coupled to an output of the buffer so the buffer provides a buffer output signal VB. A filter 326 is coupled between the output of the buffer 320 and the test output 310. For example, the filter 326 includes a resistor R3 in series between the output of the buffer 320 and the test output 310 and a capacitor coupled between the test output and ground. The filter 326 is thus configured to filter the buffer output signal VB to increase stability of the voltage VOUT at the test output 310 during the test mode. The test output 310 is coupled to an output terminal 328 of the power converter IC 302. As described herein, during testing, the main control loop of the power converter IC 302 is configured to regulate the output voltage to a reference voltage based on the voltage at 328.

[0029] The ATE 304 also includes measurement and control circuitry 330, which can include hardware and/or software configured to implement testing functionality. The control circuitry 330 can include one or more measurement inputs adapted to be coupled to respective terminals of the IC 302 for measuring voltage, current or other electrical characteristics of the IC 302 during testing. The control circuitry 330 also is coupled to a test control output 332 that is adapted to be coupled to a DFT program terminal 334 of the IC 302. The control circuitry 330 can provide control instructions, such as to enter a test mode and/or set test parameters for the IC 302 during testing.

[0030] As an example, ATE 304 can enter the test mode automatically or responsive to a user input. In the test mode, the ATE 304 is configured to supply the control voltage VCCA through diode D1 to the buffer input. As described herein, the VCCA enables the buffer 320 to drive the voltage output 310 and thereby provide sufficient power to enable (e.g., kick-start) operation of circuitry in the power converter IC 302 during testing. Concurrently, the control circuitry 330 can write instructions to the test control output 332 to command the DFT circuitry of the power converter IC 302 to enter the test mode. In the test mode responsive to the instructions at 332, DFT circuitry can be configured to disable switching by the output stage of the IC and to route the digital PWM signal to a digital output 336 of the IC. The digital output 336 is coupled to the test input 308. The measurement and control circuitry 330 can measure voltage, current and/or other electrical characteristics of the power converter IC 302 during such testing. Because, as shown in the example of FIG. 3, the test circuitry 306 is implemented without including an inductor, the risk of overshoot and undershoot during testing is reduced. Additionally, the ATE 304 is configured to test the closed loop signal chain of the power converter IC 302 at true operating frequency. Thus, the testing system 300 can help reduce overall testing time and improve accuracy over many existing testing approaches.

[0031] FIG. 4 is a graph 400 showing examples of a power converter output 402 and an output 404 of test circuitry implemented in automatic testing equipment. The graph shows the voltage outputs 402 and 404 regulated to 5 V. The comparison of outputs 402 and 404 shows a small DC voltage difference between the outputs of less than about 0.5 mV. The graph 400 thus demonstrates that the test circuitry (e.g., circuitry 114, 212, 306) described herein provides a good approximation to emulate the power train of the boost converter to enable increased testing coverage with reduced risk of voltage spikes.

[0032] In view of the foregoing structural and functional features described above, a methodology in accordance with various aspects of the present invention will be better appreciated with reference to FIG. 5. While, for purposes of simplicity of explanation, the method of FIG. 5 is shown and described as executing serially, systems and methods described herein are not limited by the illustrated order, as some aspects could occur in different orders, multiple times and/or concurrently from that described herein.

[0033] FIG. 5 is a flow diagram illustrating an example method 500 of testing a power converter circuit. The method 500 can be performed, for example, by an ATE (e.g., 104, 204 or 204), such as for testing one or more instances of a power converter IC (e.g., IC 102, 202 or 302). The description of FIG. 5 also refers to the systems of FIGS. 1, 2 and 3, which show example systems that can be configured to implement the method of FIG. 5.

[0034] At 502, the method include connecting a circuit path (e.g., 114, 212, 306) of ATE circuitry (e.g., 104, 204, 304) between a digital output terminal and a voltage output terminal of a power converter IC (e.g., IC 102, 202, 302). As described herein, the circuit path is configured to emulate a power stage (e.g., a boost power stage) of power converter IC to which the ATE circuitry is connected during testing. For example, the circuit path can include a level shifter, a buffer and filter network coupled in series between the digital output terminal and the voltage output terminal. [0035] At 504, a pull-up supply voltage is provided to an input of the buffer of the ATE circuitry to enable operation of the power converter IC. The pull-up supply voltage can be provided at a level sufficient to kick-start operation of power converter IC during testing. For example, the pull- up voltage can be provided by connecting a control voltage terminal to an input of the buffer, such as through a diode (e.g., VCCA coupled to buffer input through diode Dl).

[0036] At 506, switching of the output stage (e.g., output stage 124, 206) of the power converter IC is disabled responsive to a test mode control signal. For example, the power converter IC include DFT circuitry (e.g., DFT circuitry 128, 253, 238) configured, during testing, to force a high-side switch of the output stage to be on and to force a low-side switch of the output stage to be off.

[0037] At 508, the power converter IC is controlled to route a pulse width modulation control signal to the digital output terminal of the IC. The PWM control signal is provided by a control loop circuit (e.g., circuit 126, 208) of the power converter IC responsive to the signal provided by the ATE circuitry at the voltage output terminal. For example, the power converter IC includes a DFT control register (e.g., 128, 252) configured, during testing, responsive to provide a test mode control signal to configure a multiplexer 236 to route the PWM control signal to the digital output terminal. During testing, with the output stage switching being disabled and the PWM signal being routed to the ATE, at 510 the method can also include measuring (e.g., by the ATE 104, 204, 304) one or more signals from the power converter IC. For example, measurement circuitry (e.g., circuitry 130, 330) can measure and record the voltage (e.g., the output voltage VOUT) over a range of operating parameters (e.g., register settings). The measurement circuitry (e.g., circuitry 130, 330) can also measure current and/or other signal characteristics representative of operating characteristics of the IC over a number of operating conditions. In a further example, the method 500 can also include clamping the voltage at the input of the buffer (e.g., by Zener diode Z1 or another claiming circuit coupled to input of the buffer 320).

[0038] As described herein, the method 500 thus can take advantage can exercise the entire closed loop signal chain can be exercised and tested at operating frequency. By omitting an inductor from the test circuit path, there is no switching inductor current, which reduces overshoot and/or undershoot. ATE measurement and application measurement can perform production defect testing over a full range of settings to ensure that the power converter IC meets or exceeds desired operating parameters. The systems and methods described herein also enable the overall testing time to be reduced compared to existing testing solutions, which only cover testing process corners. Also, because the output power stage is disabled during pseudo-closed loop testing, the power stage can be tested separately, such as in open-loop manner.

[0039] In this description, numerical designations “first”, “second”, etc. are not necessarily consistent with same designations in the claims herein. Additionally, the term "couple" may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is directly coupled to device B; or (b) in a second example, device A is indirectly coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal generated by device A.

[0040] Also, in this description, a device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, a circuit or device described herein as including certain components may instead be configured to couple to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor wafer and/or integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and/or the sources to form the described structure, either at a time of manufacture or after a time of manufacture, such as by an end user and/or a third party.

[0041] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.