Related Applications

[0001] This application claims the benefit of provisional patent application serial number 63/121 ,622, filed December 4, 2020, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The present disclosure is related to a power management integrated circuit (PMIC).

Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience requires higher data rates offered by such advanced wireless communication technologies as fifth-generation new- radio (5G-NR). To achieve higher data rates, a mobile communication device may employ a power amplifier(s) to amplify a radio frequency (RF) signal(s) (e.g., maintaining sufficient energy per bit) before transmission. Given that the power amplifier(s) requires a supply voltage(s) for operation, a power management integrated circuit (PMIC) is thus required to generate and provide the supply voltage(s) to the power amplifier(s).

[0005] Given that the PMIC often needs to concurrently generate multiple supply voltages for multiple power amplifiers, the PMIC typically includes multiple direct-current to direct-current (DC-DC) power inductors. As a result, the PMIC can claim a larger portion of precious real estate in the mobile communication device. Hence, it is desirable to reduce the number of DC-DC power inductors in the PMIC to help reduce footprint of the PMIC.

[0006] Embodiments of the disclosure relate to a power management integrated circuit (PMIC). The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.

[0007] In one aspect, a PMIC is provided. The PMIC includes a voltage generation circuit configured to generate and maintain a number of voltages during at least one voltage generation period based on a reference voltage. The PMIC also includes a voltage modulation circuit configured to modulate the reference voltage during the at least one voltage generation period. The PMIC also includes a control circuit. The control circuit is configured to divide the at least one voltage generation period into a number of voltage generation intervals for generating the number of voltages, respectively. The control circuit is also configured to cause the voltage modulation circuit to modulate the reference voltage to a respective level during each of the number of voltage generation intervals. The control circuit is also configured to cause the voltage generation circuit to generate and maintain each of the number of voltages in a respective one of the number of voltage generation intervals based on the respective level of the reference voltage modulated during the respective one of the number of voltage generation intervals.

[0008] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0009] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0010] Figure 1 is a schematic diagram of an exemplary power management integrated circuit (PMIC) configured according to embodiments of the present disclosure to concurrently generate multiple voltages without requiring multiple direct-current to direct-current (DC-DC) power inductors;

[0011] Figure 2 is a schematic diagram providing an exemplary illustration of a voltage generation period during which the PMIC of Figure 1 can be configured to concurrently generate the voltages;

[0012] Figure 3 is a schematic diagram providing an exemplary illustration of a voltage modulation circuit provided in the PMIC of Figure 1 and configured according to an embodiment of the present disclosure to include a single DC-DC power inductor;

[0013] Figure 4 is a schematic diagram providing exemplary illustration of a voltage generation circuit provided in the PMIC of Figure 1 and configured according to an embodiment of the present disclosure to generate and maintain the voltages;

[0014] Figures 5A and 5B are signal diagrams illustrating exemplary operations of the PMIC of Figure 1 in accordance with embodiments of the present disclosure; and [0015] Figure 6 is a schematic diagram providing an exemplary illustration of a voltage generation circuit provided in the PMIC of Figure 1 and configured according to an alternative embodiment of the present disclosure.

Detailed Description

[0016] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0017] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0018] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0019] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] Embodiments are described herein with reference to a power management integrated circuit (PMIC). The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.

[0023] In this regard, Figure 1 is a schematic diagram of an exemplary PMIC 10 configured according to embodiments of the present disclosure to generate multiple voltages VCCI-VCCN without requiring multiple DC-DC power inductors. In an embodiment, the PMIC 10 is configured to generate and maintain the voltages VCCI-VCCN during at least one voltage generation period (T) as illustrated in Figure 2. Figure 2 is a schematic diagram providing an exemplary illustration of the voltage generation period (T) during which the PMIC 10 of Figure 1 can be configured to concurrently generate the voltages VCCI-VCCN.

[0024] In a non-limiting example, the voltage generation period (T) can be equally divided into multiple time slots (At). Accordingly, multiple voltage generation intervals dTi-dTN can be further defined to each include a respective one or more of the time slots (At). Each of the voltage generation intervals dTi- dTN can be longer if a respective one of the voltages VCCI-VCCN is higher or be shorter if a respective one of the voltages VCCI-VCCN is lower. For example, the voltage generation interval dTi can be configured to include two time slots (2At) for generating a higher voltage Vcci. In contrast, the voltage generation intervals dT2 and dTN are configured to each include one time slot (At) for generating lower voltages Vcc2 and VCCN. Accordingly, the PMIC 10 can be configured to generate and maintain each of the voltages VCCI-VCCN during a respective one of the voltage generation intervals dTi-dTN.

[0025] In this regard, the voltage generation intervals dTi-dTN appear to be analogous to a time-division schedule for generating the voltages VCCI-VCCN. However, as discussed in detail below, the PMIC 10 can be further configured to maintain each of the voltages VCCI-VCCN at a respective constant level during each of the voltage generation intervals dTi-dTN. As such, despite that the voltages VCCI-VCCN are each generated in a time-division fashion, the PMIC 10 can nevertheless make the voltages VCCI-VCCN concurrently available during the voltage generation period (T). Accordingly, the voltage generation period (T) should be determined by taking into consideration as to how long the PMIC 10 can maintain the voltages VCCI-VCCN and to what degree a ripple can be tolerated in each of the voltages Vcci-Vcc.

[0026] With reference back to Figure 1 , the PMIC 10 includes a voltage generation circuit 12 and a voltage modulation circuit 14. The voltage generation circuit 12 is configured to generate and maintain a respective one of the voltages VCCI-VCCN during a respective one of voltage generation intervals dTi-dTN based on a reference voltage VREF modulated for the respective one of the voltage generation intervals dTi-dTN. The voltage modulation circuit 14 is configured to modulate the reference voltage V EF in each of the voltage generation intervals dTi-dT _N .

[0027] The PMIC 10 further includes a control circuit 16, which can be a field programmable gate array (FPGA), as an example. The control circuit 16 is configured to divide the voltage generation period (T) into the voltage generation intervals dTi-dTN. Accordingly, the control circuit 16 can provide a target signal 18 to cause the voltage modulation circuit 14 to modulate the reference voltage VREF to a respective level during each of the voltage generation intervals dTi-dTN. In addition, the control circuit 16 can assert multiple control voltages CTRLi- CTRN to thereby cause the voltage generation circuit 12 to generate and maintain each of the voltages VCCI-VCCN in a respective one of the voltage generation intervals dTi-dTN based on the respective level of the reference voltage VREF modulated during the respective one of the voltage generation intervals dTi-dTN. Herein, asserting the control voltages CTRLI-CTRN means increasing the control voltages CTRLI-CTRN above respective threshold voltages. In contrast, de-asserting the control voltages CTRLI-CTRN means decreasing the control voltages CTRLI-CTRN below the respective threshold voltages.

[0028] Given that the voltages VCCI-VCCN are each generated in a timedivision fashion, the voltage modulation circuit 14 can also modulate the reference voltage VREF in the time-division fashion. As such, it is not necessary for the voltage modulation circuit 14 to concurrently modulate the reference voltage V EF in the voltage generation intervals dTi-dTN, thus making it possible for the voltage modulation circuit 14 to operate based on a single DC-DC power inductor to help reduce footprint of the PMIC 10.

[0029] In this regard, Figure 3 is a schematic diagram providing an exemplary illustration of the voltage modulation circuit 14 in the PMIC 10 of Figure 1 configured according to an embodiment of the present disclosure to modulate the reference voltage VREF based on a single DC-DC power inductor LDC-DC. Common elements between Figures 1 and 3 are shown therein with common element numbers and will not be re-described herein.

[0030] In a non-limiting example, the voltage modulation circuit 14 includes a voltage amplifier 20 (denoted as “VA”), an offset capacitor COFF, a multi-level charge pump (MCP) 22, the DC-DC power inductor LDC-DC, and a switch SOFF. The voltage amplifier 20 is configured to generate an initial reference voltage VAMP based on a target voltage VTGT, which is received as part of the target signal 18. The offset capacitor COFF is configured to raise the initial reference voltage VAMP by an offset voltage VOFF to thereby generate the reference voltage VREF (VREF = VAMP + VOFF) at a reference node 24. In this regard, the voltage amplifier 20 and the offset capacitor COFF are collectively responsible for modulating the reference voltage VREF in each of the voltage generation intervals dTi-dTN. Notably, by using the offset capacitor COFF to raise the initial reference voltage VAMP, the initial reference voltage VAMP will be lower than the reference voltage VREF, thus helping to improve efficiency of the voltage amplifier 20.

[0031] The MCP 22 is configured to generate a DC voltage VDC as a function of a battery voltage VBAT and in accordance with a defined duty cycle. In a nonlimiting example, the defined duty cycle can also be configured via the target signal 18. The DC-DC power inductor LDC-DC is configured to induce a reference current IREF based on the DC voltage VDC to thereby charge the offset capacitor COFF to the offset voltage VOFF. The switch SOFF may be closed when the offset capacitor COFF is charged towards the offset voltage VOFF and opened when the offset capacitor COFF is charged to the offset voltage VOFF. In this regard, the offset voltage VOFF is said to be modulated by the reference current I EF.

[0032] By modulating the reference voltage VREF and/or the reference current IREF, the voltage modulation circuit 14 further modulates a reference power PREF (PREF = VREF * IREF) at the reference node 24. In this regard, the voltage modulation circuit 14 may also be referred to as a power modulation circuit. In one embodiment, the reference current IREF can be so generated as a constant current during the voltage generation period (T). As such, the voltage modulation circuit 14 can modulate the reference power PREF by modulating the reference voltage VREF.

[0033] With reference back to Figure 1 , the PMIC 10 can include multiple voltage outputs 26(1)-26(N), each coupled to a respective one of multiple load circuits LOADI-LOADN (e.g., power amplifier circuits). The voltage generation circuit 12 is coupled to the voltage outputs 26(1 )-26(N) and configured to concurrently provide the voltages VCCI-VCCN to the voltage outputs 26(1 )-26(N), respectively, during the voltage generation period (T). Notably, the load circuits LOADI-LOADN can each act as a current source. As such, the load circuits LOADI-LOADN can each induce a respective one of multiple load currents ILOAD-I- ILOAD-N in response to receiving a respective one of the voltages VCCI-VCCN.

Accordingly, the load circuits LOADI-LOADN will each consume a respective one of multiple load powers PLOAD-I-PLOAD-N (PLOAD-I = Vcci * ILOAD-I, 1 i N).

[0034] The voltage generation circuit 12 may be configured according to an embodiment illustrated in Figure 4. Figure 4 is a schematic diagram providing an exemplary illustration of the voltage generation circuit 12 in the PMIC 10 of Figure 1 configured according to an embodiment of the present disclosure. Common elements between Figures 1 and 4 are shown therein with common element numbers and will not be re-described herein. [0035] In a non-limiting example, the voltage generation circuit 12 includes multiple holding capacitors CHOLD-I-CHOLD-N each coupled between a respective one of the voltage outputs 26(1)-26(N) and a ground (GND). The voltage generation circuit 12 also includes multiple switched capacitor-based voltage converters 28(1 )-28(N) each configured to generate a respective one of multiple charging voltages VCHARGE-I-VCHARGE-N in a respective one of the voltage generation intervals dTi-dTN based on the reference voltage VREF modulated during the respective one of the voltage generation intervals dTi-dTN. Each of the charging voltages VCHARGE-I-VCHARGE-N can cause a respective one of multiple charge currents ICHARGE-I-ICHARGE-N to thereby charge a respective one of the holding capacitors CHOLD-I-CHOLD-N to a respective one of the voltages VCCI-VCCN during a respective one of the voltage generation intervals dTi-dTN.

[0036] In this regard, the holding capacitors CHOLD-I-CHOLD-N are still being charged sequentially to the voltages VCCI-VCCN during the voltage generation intervals dTi-dTN. However, each of the holding capacitors CHOLD-I-CHOLD-N is so chosen to have a respective capacitance that can maintain a respective one of the voltages VCCI-VCCN for up to the voltage generation period (T). As a result, the voltages VCCI-VCCN can be simultaneously available at the voltage outputs 26(1 )-26(N) during the voltage generation period (T). Hence, each of the voltage generation intervals dTi-dTN must be long enough and each of the charge currents ICHARGE-I-ICHARGE-N must be large enough to ensure that a respective one of the holding capacitors CHOLD-I-CHOLD-N can be charged to a respective one of the voltages VCCI-VCCN during a respective one of the voltage generation intervals dTi-dTN.

[0037] The switched capacitor-based voltage converters 28(1 )-28(N) can be implemented based on any known switched capacitor-based voltage converter that does not include a DC-DC power inductor. In one embodiment, each of the switched capacitor-based voltage converters 28(1 )-28(N) can be a switched capacitor-based buck voltage converter. In this regard, each of the switched capacitor-based voltage converters 28(1 )-28(N) can operate based on a respective one of multiple conversion ratios XI-XN that is less than or equal to 1 (XI-XN 1 ). Accordingly, each of the switched capacitor-based voltage converters 28(1 )-28(N) is configured to reduce or pass the reference voltage VREF modulated in a respective one of the voltage generation intervals dTi-dTN to thereby generate a respective one of the charge voltages VCHARGE-I -VCHARGE-N that is lower than or equal to the reference voltage V EF.

[0038] In another embodiment, each of the switched capacitor-based voltage converters 28(1 )-28(N) can be a switched capacitor-based boost voltage converter. In this regard, each of the switched capacitor-based voltage converters 28(1 )-28(N) can operate based on a respective one of the conversion ratios XI-XN that is greater than 1 (XI-XN > 1 ). Accordingly, each of the switched capacitor-based voltage converters 28(1 )-28(N) is configured to boost the reference voltage VREF modulated in a respective one of the voltage generation intervals dTi-dTN to thereby generate a respective one of the charge voltages VCHARGE-I -VCHARGE-N that is higher than the reference voltage VREF. Notably, by boosting the reference VREF to generate the charge voltages VCHARGE-I -VCHARGE-N, the voltage modulation circuit 14 can be configured to reduce the reference voltage VREF during each of the voltage generation intervals dTi-dTN, thus helping to improve efficiency of the voltage modulation circuit 14. In addition, the voltage modulation circuit 14 may also reduce the reference current IREF during each of the voltage generation intervals dTi-dTN, thus making it possible to reduce the size of the DC-DC power inductor LDC-DC.

[0039] In one embodiment, the conversion ratios XI-XN can be so determined to be different from one another. Accordingly, the switched capacitor-based voltage converters 28(1 )-28(N) will each operate based on a different one of the conversion ratios XI-XN. In another embodiment, the conversion ratios XI-XN can be so determined to be identical. Accordingly, the switched capacitor-based voltage converters 28(1 )-28(N) will each operate based on a common conversion ratio. The conversion ratios XI-XN can be determined by the control circuit 16 or preconfigured in the switched capacitor-based voltage converters 28(1 )-28(N). [0040] Figures 5A and 5B are signal diagrams illustrating exemplary operations of the PMIC of Figure 1 in accordance with embodiments of the present disclosure. The illustrations discussed in Figures 5A and 5B are based on a set of assumptions. It should be appreciated that the assumptions are merely made for the convenience of illustration and shall not be considered as limiting by any means. Elements in Figures 1 and 4 are referenced in Figures 5A and 5B by respective element numbers and will not be re-described herein.

[0041] Herein, the voltage generation circuit 12 is assumed to generate the three voltages Vcm, Vcc2, and Vcca for the three load circuits LOADi, LOAD2, and LOAD3, respectively. In this regard, it is assumed that there will be three load currents ILOAD-I , ILOAD-2, and ILOAD-3 flowing through the load circuits LOADi, LOAD2, and LOAD3, respectively.

[0042] The voltage generation circuit 12 is also assumed to include the three switched capacitor-based voltage converters 28(1 ), 28(2), and 28(3) (represented by 28(N)) and the three holding capacitors CHOLD-I , CHOLD-2, and CHOLD-3. The holding capacitors CHOLD-I , CHOLD-2, and CHOLD-3 are assumed to be coupled to the three voltage outputs 26(1 ), 26(2), and 26(3), respectively. The voltage outputs 26(1 ), 26(2), and 26(3) are assumed to be coupled to three load circuits LOADi, LOAD2, and LOAD3, respectively.

[0043] Accordingly, the voltage generation period (T) is assumed to be divided into three voltage generation intervals dTi, dT2, and dTs (T = dTi + dT2 + dTs) for generating the voltages Vcm, Vcc2, and Vcc3, respectively. In this example, the voltage generation period (T) is assumed to include four time slots (T = 4At), which are divided unevenly among the voltage generation intervals dTi, dT2, and dTs. The voltage generation interval dTi is assumed to include 2 time slots (dTi = 2At = ¹ /2T), while the voltage generation intervals dT2 and dTs are assumed to each include 1 time slot (dT2 = dTs = At = ! T).

[0044] The switched capacitor-based voltage converters 28(1 ), 28(2), and 28(3) are assumed to operate based on three conversion ratios xi, X2, and X3 to convert the reference voltage VREF modulated during the voltage generation intervals dTi, dT2, and dTs into three charging voltages VCHARGE-I , VCHARGE-2, and VCHARGE-3, respectively. The charging voltages VCHARGE-I , VCHARGE-2, and VCHARGE- 3, in turn, are assumed to cause three charging currents ICHARGE-I , ICHARGE-2, and ICHARGE-3 for charging the holding capacitors CHOLD-I , CHOLD-2, and CHOLD-3 during the voltage generation intervals dTi, dT2, and dTs, respectively.

[0045] With reference to Figure 5A, in a non-limiting example, the switched capacitor-based voltage converters 28(1 ), 28(2), and 28(3) are each configured to operate as a switched capacitor-based boost voltage converter based on a common conversion ratio x (x = xi = X2 = X3). The load currents ILOAD-I , ILOAD-2, and ILOAD-3 as well as the voltages Vcm, Vcc2, and Vcc3 are prestored in the PMIC 10 and thus considered known to the control circuit 16. In this example, it is further assumed that Vcm = 1 Volt (V), Vcc2 = 2 V, Vcc3 = 3 V, ILOAD-I = 2 Amp (A), ILOAD-2 = 1 A, ILOAD-3 = 1 A, and x = 4.

[0046] The control circuit 16 may determine each of the charge currents ICHARGE-I , ICHARGE-2, and ICHARGE-3 as a function of a respective one of the load currents ILOAD-I , ILOAD-2, and ILOAD-3, as expressed in the equations below, for charging the holding capacitors CHOLD-I , CHOLD-2, and CHOLD-3 during the voltage generation intervals dTi, dT2, and dTs, respectively.

ICHARGE-1 = I LOAD-1 * (T / dTi) = 4 A

ICHARGE-2 = ILOAD-2 * (T / dT2) = 4 A

ICHARGE-3 = ILOAD-3 * (T / dTs) = 4 A

[0047] The control circuit 16 can further determine the reference current IREF during the voltage generation intervals dTi, dT2, and dTs in accordance with the equations below.

IREF during dTi (IREFI ) = ICHARGE-I / X = 4 A / 4 = 1 A

IREF during dT2 (IREF2) = ICHARGE-2 /x = 4 A /4 = 1 A

IREF during dTs (IREFS) = ICHARGE-3 /x = 4 A /4 = 1 A

[0048] In this regard, the reference current IREF is a constant current across the voltage generation intervals dTi, dT2, and dTs. The control circuit 16 can further determine the reference voltage VREF during the voltage generation intervals dTi, dT2, and dTs in accordance with the equations below.

V EF during dTi (VREFI) = x * Vcci = 4 * 1 V = 4 V VREF during dT2 (VREF2) = x * Vcc2 = 4 * 2 V = 8 V VREF during dTs (VREFS) = x * Vcc3 = 4 * 4 V = 12 V

[0049] Accordingly, an average of the reference power PREF as modulated by the voltage modulation circuit 14 during the voltage generation period (T) can be expressed in the equation below.

AVG(PREF) = (dTl*VREF1 *lREF1 + dT2*VREF2*lREF2 + dT3*VREF3*lREF3) I T = ( ¹ / ₂ T*4V*1 A + !4T*8V*1 A + ¹ / ₄ T*12V*1 A) / T = 7 Watt (W)

[0050] Similarly, an average load power AVG(PLOAD) consumed by the load circuits LOADi, LOAD2, and LOAD3 during the voltage generation period (T) can be expressed in the equation below.

AVG(PLOAD) = (Vcci * I LOAD-1 + VcC2* I LOAD-2 + VcC3*lLOAD3)

= 1 V*2A + 2V*1A + 3V*1 A = 7 W

[0051] With reference to Figure 5B, the control circuit 16 may control each of the switched capacitor-based voltage converters 28(1 ), 28(2), and 28(3) via a respective one of three control voltages CTRL1, CTRL2, and CTR3. The control circuit 16 may assert the control voltage CTRL1 prior to or at time T1 to cause the switched capacitor-based voltage converter 28(1 ) to charge the holding capacitor CHOLD-I , assert the control voltage CTRL2 prior to or at time T2 to cause the switched capacitor-based voltage converter 28(2) to charge the holding capacitor CHOLD-2, and assert the control voltage CTRL3 prior to or at time T3 to cause the switched capacitor-based voltage converter 28(3) to charge the holding capacitor CHOLD-3. The control circuit 16 may be further configured to de-assert the control voltage CTRLi at or after time T2, de-assert the control voltage CTRL2 at or after time T3, and de-assert the control voltage CTRL3 at or after time T4.

[0052] With reference back to Figure 1 , the PMIC 10 may be configured to include a memory circuit 30, which can be a random-access memory (RAM) circuit, a flash storage circuit, or a register bank, as an example. The memory circuit 30 may be programmed to store the voltages VCCI-VCCN and the load currents ILOAD-I-ILOADN. The memory circuit 30 may be further programmed to store the conversion ratios XI-XN of the switched capacitor-based voltage converters 28(1 )-28(N), as shown in Figure 4. In a non-limiting example, the memory circuit 30 can be programmed via a control bus 32, such as a radio frequency front-end (RFFE) bus or a single-wire serial bus, as an example. Accordingly, the control circuit 16 may retrieve the voltages VCCI-VCCN, the load currents ILOAD-I-ILOADN, and/or the conversion ratios XI-XN from the memory circuit 30.

[0053] The PMIC may also include multiple feedback circuits FBI-FBN, each configured to provide a respective one of a plurality of voltage feedbacks VCCI-FB- VCCN-FB to the control circuit 16. Notably, each of the voltage feedbacks VCCI-FB- VCCN-FB can be proportionally related to a respective one of the voltages Vcm- VCCN. Accordingly, the control circuit 16 may control the voltage modulation circuit 14 to adjust the reference voltage VREF during any of the voltage generation intervals dTi-dTN based on a respective one of the voltage feedbacks VCC1 -FB-VCCN-FB.

[0054] Alternative to the voltage generation circuit 12 of Figure 4, it is also possible to implement the voltage generation circuit 12 based on alternative configurations. In this regard, Figure 6 is a schematic diagram of an exemplary voltage generation circuit 34 configured according to another embodiment of the present disclosure. Common elements between Figures 1 , 4, and 6 are shown therein with common element numbers and will not be re-described herein. [0055] The voltage generation circuit 34 includes multiple hybrid switch circuits 36(1 )-36(N) (denoted as “SW/LDO”). Each of the hybrid switch circuits 36(1 )-36(N) is coupled to a respective one of the holding capacitors CHOLD-I- CHOLD-N and can operate either as a switch or a low dropout (LDO) regulator. Specifically, each the hybrid switch circuits 36(1 )-36(N) can provide the reference voltage VREF as a respective one of the charging voltages VCHARGE-I-VCHARGE-N directly to a respective one of the holding capacitors CHOLD-I -CHOLD-N when operating as the switch. In contrast, when operating as the LDO regulator, each of the hybrid switch circuits 36(1 )-36(N) regulates the reference voltage VREF before providing to a respective one of the holding capacitors CHOLD-I -CHOLD-N as a respective one of the charging voltages VCHARGE-I-VCHARGE-N.

[0056] In one embodiment, the control circuit 16 may cause the voltage modulation circuit 14 to modulate the reference voltage VREF in each of the voltage generation intervals dTi-dTN to be equal to a respective one of the voltages VCCI-VCCN. In this regard, the control circuit 16 may cause each of the hybrid switch circuits 36(1 )-36(N) to operate as the switch.

[0057] In another embodiment, the control circuit 16 may cause the voltage modulation circuit to modulate the reference voltage in each of the voltage generation intervals dTi-dTN to be higher than a respective one of the voltages VCCI-VCCN. In this regard, the control circuit 16 may cause each of the hybrid switch circuits 36(1 )-36(N) to operate as the LDO regulator.

[0058] The voltage generation circuit 34 may also include a maximum voltage control circuit 38. The maximum voltage control circuit 38 may be configured to ensure that the reference voltage VREF is always greater than or equal to a respective one of the voltages VCCI-VCCN during a respective one of the voltage generation intervals dTi-dTN such that none of charging currents ICHARGE-I- ICHARGE-N can flow back toward the voltage modulation circuit 14.

[0059] With reference back to Figure 1 , the PMIC 10 may also include an auxiliary voltage generation circuit 40 coupled to the voltage generation circuit 12. The auxiliary voltage generation circuit 40 may be configured generate multiple auxiliary voltages VASSI-VASSN to assist in charging the holding capacitors CHOLD-I -CHOLD-N during the voltage generation intervals dTi-dTN, respectively.

Notably, the auxiliary voltages VASSI-VASSN may each cause a respective one of the charging currents ICHARGE-I-ICHARGE-N to increase, thus helping to speed up charging of a respective one of the holding capacitors CHOLD-I-CHOLD-N during a respective one of the voltage generation intervals dTi-dTN. In a non-limiting example, the auxiliary voltage generation circuit 40 may generate each of the auxiliary voltages VASSI-VASSN during a respective one of the voltage generation intervals dTi-dTN as a function of the reference voltage VREF modulated during the respective one of the voltage generation intervals dTi-dTN.

[0060] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.