TECHNICAL FIELD

The present disclosure relates to a power module, and more particularly, to a power module with improved current distribution.

BACKGROUND

Semiconductor power modules are widely used in industry. For example, such a power module may be used for the controlled switching of high currents and can be used in power converters (such as inverters) to convert DC to AC or vice versa, or for converting between different voltages or frequencies of AC. Such inverters are used in motor controllers or interfaces between power generation or storage, or a power distribution grid. For example, a power module may be used in a "grid tie" inverter of a battery storage system. In such a battery storage system, current is supplied to a power supply grid either to stabilize the grid or to provide electrical power during times where the grid electric energy is expensive, ie. in the morning and in the afternoon. The batteries are recharged during nighttime when grid energy cost is lower, or they can be recharged using solar power. Overall, the system helps the customer to reduce expenses for electrical energy. The "grid tie" inverter connects the battery storage system to the grid and has the task to convert the DC voltage of the battery to AC voltage for the grid and vice versa.

SUMMARY

It is an object of the present disclosure to provide a power module with enhanced efficiency.

In a first aspect, a power module is provided, comprising at least one substrate on which at least two semiconductor switches are mounted, wherein the at least two semiconductor switches are configured to operate in parallel, and wherein at least one of a control circuit and a load circuit for the semiconductor switches is designed to minimize a difference between electrical parameters of the at least one circuit for respective semiconductor switches. The term "load circuit" used herein refers to a set of circuits whose current (load current) is routed from the positive or negative DC inputs to the load output via the semiconductor switches, and the term "control circuit" used herein refers to a set of circuits whose signals (control signals) are routed from external pins to the gate or sensing contacts of the semiconductor switches and are used to control the switching of the semiconductor switches.

In an embodiment, the electrical parameter is signal propagation time. The signal propagation time used herein refers to the time for a signal passing from external pin(s) to the gate contact(s) of the semiconductor switches.

In an embodiment, the electrical parameter is a stray inductance value. The stray inductance value used herein refers to the value of stray inductances generated on the path of the load current.

In an embodiment, the at least one of the control circuit and the load circuit is designed by adjusting length of each of respective signal paths for respective semiconductor switches. Such adjustment is possible today by modelling at the design stage, and is particularly advantageous if the adjustments are made to the layout of the conducting tracks on which semiconductor and other components mounted, or the length and positioning of wirebonds which connect sections of conducting tracks and/or semiconductor and other components electrically together. In an embodiment, the at least one of the control circuit and the load circuit has signal paths of equal length for respective semiconductor switches.

In an embodiment, the control circuit exhibits a difference between signal propagation times for a control signal passing through respective signal paths of less than 10ns.

In an embodiment, the control circuit exhibits a difference of signal propagation times for a control signal passing through respective signal paths of between 1 ns and 20ns. In an embodiment, the length of each of the respective signal paths for the control circuit is adjusted by positioning a foot on the substrate for a bond wire from an external pin to the substrate. In an embodiment, the length of each of the respective signal paths is adjusted by adjusting lengths of bond wires involved in the respective signal paths.

In an embodiment, the length of each of the respective signal paths is adjusted by adjusting loop height of bond wires involved in the respective signal paths.

In an embodiment, the at least two semiconductor switches comprise wide- bandgap semiconductors.

In an embodiment, the wide-bandgap semiconductors comprise Silicon Carbide (SiC) semiconductors.

In an embodiment, the SiC semiconductors comprise SiC Metal-Oxide- Semiconductor Field Effect Transistors (MOSFETs). In an embodiment, the power module comprises a Neutral-Point-Clamped-2

(NPC2) topology. The NPC2 topology is a known topology for three-level inverter circuits and comprises two switches in series between the positive and negative DC power lines, and the load connection comprising the connection between these switches. In addition, two further switches, connected as a bi-directional switch, lie between the load connection and the neutral power line. It is also further described below.

In an embodiment, the at least one substrate comprises a DBC substrate. Such a substrate is formed by a copper/ceramic/copper sandwich, where a circuit structure may be created in the upper copper layer and which may be populated with semiconductor switches, capacitors and/or resistors as required to form a functioning circuit.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages will be more apparent from the following description of embodiments with reference to the figures, in which: Fig. 1 shows a cross section view of a power module according to an

embodiment of the present disclosure;

Fig. 2 shows a perspective view of the power module according to the

embodiment of the present disclosure;

Fig. 3 shows a view of a power module with lid placed according to an

embodiment of the present disclosure;

Fig. 4 shows a schematic diagram of a power module with IGBT/Diode combination in an NPC2 three-level topology;

Fig. 5 shows a schematic diagram of a power module with SiC-MOSFETs in an NPC2 three-level topology; Fig. 6 shows a top view of an exemplary power module according to an embodiment of the present disclosure;

Fig. 7 shows in more detail a top view of the exemplary power module according to the embodiment of the present disclosure;

Fig. 8 shows an example of positioning a foot of a bond wire on the substrate to enable symmetry according to an embodiment of the present disclosure;

Fig. 9 is a simplified schematic diagram of DBC1 with T1 and T4 in the power module shown in Fig. 7, where (a) shows the conductor of the control circuits for T1 and T4, (b) shows the signal path of the control circuit, and (c) shows the load current path of the load circuit;

Fig. 10 is a simplified schematic diagram of DBC2 with T2 and T3 in the power module shown in Fig. 7; and Fig. 11 shows a way of increasing loop height of a bond wire in a power module according to an embodiment of the present disclosure. DETAILED DESCRIPTION

The embodiments of the disclosure will be detailed below with reference to the drawings. It should be noted that the following embodiments are illustrative only, rather than limiting the scope of the disclosure. References in the specification to "one embodiment," "an embodiment," etc.

indicate that the embodiment described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. It shall be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed terms.

The terminology used herein is for the purpose of describing particular

embodiments only and is not intended to be liming of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "has", "having", "includes" and/or "including", when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/ or

combinations thereof.

In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.

Fig. 1 shows a cross section view of a power module 100 according to an embodiment of the present disclosure, and Fig. 2 shows a perspective view of the power module according to the embodiment of the present disclosure. As shown, the power module 100 according to an embodiment of the present disclosure comprises a copper baseplate 110 with two substrates 120 soldered on top of it. Direct Bonding Copper (DBC) substrates are used in the power module 100. The DBC substrates are formed by a sandwich of Cu 122 (for example, of 300μηπ), Ceramics 124 (for example, AIN of 320μηπ) and Cu 126 (for example, of 300μηπ) where in the upper Cu layer 122 a circuit structure can be found that holds semiconductor switches 130, capacitors 150 and gate resistors 140. Aluminum bond wires 1 60 are used for the top-side connection of the die and for

interconnection with pins 210, including signal pins and power pins of the power module 100. The two DBC substrates are connected via bond wires 220. The power module 100 is encapsulated with a molded plastic frame 170 (holding the press-fit contact pins). It is filled with Silicone-gel 180. The frame is fixed by metal bushings 230. The power module 100 is closed by a plastic lid 300. Fig. 3 shows a view of the power module 100 with lid 300 in place.

During assembly of the power module, first the semiconductor switches, resistors and capacitors are soldered to the DBC substrate. Afterwards the substrate is pre-tested. The tested DBC is then soldered to a 3mm thick copper baseplate covered with nickel plating. Afterwards the plastic frame is mounted; this is done by bonding the frame to the baseplate using silicone glue. In addition, the frame and the base plate are fixed by metal bushings. Afterwards the pins and the substrates are connected in a second bonding step with bond wires. In the final step the module is filled with silicone-gel, the lid is mounted and the module is tested in regards to secure the electrical function. The soldering steps may be combined into a single soldering step in order to save process complexity and hence cost.

The power module is designed to fulfill two major characteristics: High power conversion efficiency and high power density. Factors as lifetime, cost and quality are also taken into account.

In order to achieve high power conversion efficiency, a three-level topology is used. By using a three-level topology, fewer external components (i.e. filters) are needed because the sine-waveform is reproduced better. At the same time, the overall system efficiency increases.

Fig. 4 shows a schematic diagram of a power module with conventional Silicon technology (mainly IGBT/Diode combination) in a Neutral Point Clamped (NPC)-2 three-level topology. The numerals in the figure denote number of pins of the power module. As shown, there are additional free-wheeling diodes D1 , D4, D5 and D6. The configurations require the discrete components. In an embodiment, high performance wide-bandgap semiconductors, such as Silicon Carbide (SiC) semiconductor switches may be used, as they generally outperform standard silicon based components, i.e. Insulated Gate Bipolar Transistors (IGBT). The wide-bandgap semiconductors (e.g., SiC semiconductor switches) have the characteristic to switch very fast, and therefore have less switching losses than IGBTs. The wide-bandgap semiconductors, for example SiC Metal-Oxide- Semiconductor Field Effect Transistors (MOSFETs), have higher efficiency, and so less cooling is needed compared with IGBTs.

The three-level topology may make use of the MOSFET intrinsic body diode, and thus no additional Si or SiC freewheeling diode is needed as it is the case in IGBT based three-level power module. Moreover, the SiC MOSFET needs less space on the substrate compared to equal rated IGBT. Therefore, higher power densities are possible. Fig. 5 shows a schematic diagram of a power module 500 with Sic-MOSFETs in an NPC2 three-level topology. As shown, no additional freewheeling diodes are required in the power module. It is also shown that there are four semiconductors, T1 -T4, and two substrates DBC1 and DBC2 inside the power module 500. DBC1 holds T1 and T4, and DBC2 holds T2 and T3. The numerals 1 -24 in the figure denote pin reference numbers of the power module.The line ringed denotes the connection between the two DBC substrates. The wide-bandgap semiconductors put high demands on the design of the power module from thermal and electrical standpoint. The wide-bandgap

semiconductors (e.g., SiC semiconductor switches) have the characteristic to switch very fast, meaning that the transition from conduction to blocking mode takes only a few nanoseconds. As current gradients during switching are high, the parasitic inductance of the whole assembly needs to be as small as possible.

The wide-bandgap semiconductors (e.g., SiC semiconductor switches) are used in applications where highest efficiency in small building volume is required by the application. SiC MOSFET show fast switching speeds and low on-state

resistance (Rds,on) at the same time. As SiC wafers are expensive to

manufacture, and with current manufacturing processes, it is hard to fabricate components with an acceptably low crystal failure amount, the die are typically very small (for example, 15-25mm ² ). This keeps yield losses low, but restricts the total current that a component can pass. In order to achieve high output powers, several of these small components (for example MOSFETs) need to be operated in parallel.

Having two or more semiconductor switches in parallel practically leads to an asymmetric current distribution, as different effects come into play:

- Layout asymmetries (the current is not distributed equally in the copper layer of the substrate due to differences in the impedance of the current path)

Electromagnetic effects (stray inductance and mutual couplings affect the current distribution)

Device variations due to manufacturing (semiconductor properties) Due to these effects, each semiconductor switch has to be chosen to be able to carry worst case current that can occur with unbalanced current symmetry. The practical approach to handle this is to derate the current of the power module, so that even in worst-case conditions no semiconductor switch will be overloaded. The term "derating" refers to the operation of a device at less than its rated maximum capability in order to prolong its life.

In an example, for a 200A power Module, 2x100A chip are selected to operate in parallel. As a current imbalance of 20% is expected, the power module is designed for 80A per die (="derated", so the 2x100A Chips form a 1 60A power module, sacrificing 20% of the theoretical power module performance).

This principle leads to non-ideal utilization of the semiconductor switches. The problems become even more delicate when fast switching semiconductor switches, i.e. SiC MOSFETs, are used. When turn-on and turn-off processes only take 10-50ns, a high dynamic symmetry is required, as otherwise the device that is "faster" due to the position on the substrate from a layout perspective will have to handle high peak currents.

In an embodiment, the load circuit and/or control circuit of paralleled

semiconductor switches are designed to have identical substrate structure, to enable symmetric current share and thereby avoiding the need for current derating.

Fig. 6 shows a top view of an exemplary power module 600 according to an embodiment of the present disclosure, and Fig. 7 shows a top view of the exemplary power module 600 in more detail. As shown, there are four

semiconductor switches, where T1-T4 are doubled compared with those shown in Fig. 5. DBC1 holds T1 and T4, and DBC2 holds T2 and T3. In other words, each transistor in Fig. 5 is realized by two transistors in parallel in Figs. 6 and 7. Similar as Fig. 5, the bond wires ringed shown in Fig. 7denote the connection between the two DBC substrates. The load circuit for the bidirectional semiconductor switches in DBC 2 (T2, T3) is designed to have a geometrically symmetric layout with two-axis symmetry. At the same time the control circuit of DBC2 (T2, T3) is absolutely geometrically symmetric regarding upper and lower section. On the other hand, the control circuit of DBC1 (T1 , T4) is designed to have equal control signal propagation times for both semiconductor switches.

High symmetry is required to guarantee symmetric switching behavior of paralleled semiconductor switches. In an embodiment, the control circuit is designed to minimize a difference between electrical parameters of the control circuit for respective semiconductor switches, and/or the load circuit is designed to minimize a difference between electrical parameters of the load circuit for respective semiconductor switches. In an embodiment, the electrical parameter is signal propagation time. In another embodiment, the electrical parameter is a stray inductance value.

The signal propagation time is proportional to the length of the signal path of the load circuit/control circuit. Therefore, the control circuit and/or the load circuit for paralleled semiconductor switches may be designed to have signal paths of equal length, to minimize the different between the signal propagation times. The signal path is formed partly by the bond wire involved in the signal path and partly by the substrate metallization. If the substrate layouts of the control circuit for paralleled semiconductor switches are different, the length of each of the signal paths for respective semiconductor switches may be adjusted by positioning a foot on the substrate for a bond wire from an external pin to the substrate.

Fig. 8 shows an example of positioning a foot of a bond wire on the substrate to enable symmetry according to an embodiment of the present disclosure. The Cu layers 810 of the DBC substrates 840 hold semiconductor switches 820. The DBC substrates 840 are connected via bond wires. The power module is encapsulated with a frame 850, on which external pins 830 are mounted. In Fig. 8, the short dashed line shows the conventional foot selection, and the long dashed line shows a different foot selection which may enable symmetry. In the conventional foot selection, the position of the foot of the bond wire on the substrate is generally selected from process optimization point of view, which will result a shorter wire. It is noted that the position of the foot of the bond wire as shown by the long dashed line may be located in a greater distance seen from the pin, to allow for similar gate signal propagation times for the paralleled semiconductor switches. The position of the foot of the bond wire may be appropriately selected to match the substrate layout to allow for equal signal propagation times at the gates of the paralleled semiconductor switches.

Fig. 9 is a simplified schematic diagram of DBC1 with T1 and T4 in the power module shown in Fig. 7, where (a) shows the conductor of the control circuits 1130 for T1 and T4, (b) shows the signal path of the control circuit 1130, and (c) shows the load current path of the load circuit 1120. By positioning the foot of the bond wire from the external pin 1110 to the substrate as shown, the signal propagation times of the control circuit for T1 and T4 may be equal. With the conventional foot selection, propagation time mismatches of between 20 and 50 ns or more are widely expected. With the appropriate selection of the foot position, it is possible to reduce the different between the signal propagation times to below 10 ns. In an embodiment, the difference between the signal propagation times is reduced to be between 1 ns to 20ns. Fig. 10 is a simplified schematic diagram of DBC2 (denoted by 1230 in the figure) with T2 and T3 in the power module shown in Fig. 7, where X1 and X2 denote the axes of symmetry, and the short dashed line shows the load current path. As shown, the Cu layer 1220 of the DBC 1230 hold semiconductor switches T2 and T3. The power module is encapsulated with a frame 1210, on which external pins 1240 are mounted. The DBC 1230 is symmetrical from electrical and geometrical standpoint. This specific chip arrangement is needed to form a bidirectional switch. The short dashed line shows only one option for the load current - it can also be vice versa. It can also be stated that this design enables thermal optimization since the symmetry in design helps to keep all chips at equal temperatures - no "hot spot" will occur. The load current path is symmetrical from electrical standpoint, even if it looks asymmetric from geometrical point of view.

For symmetry in the design, it is required that the load circuit of the power module is electrically symmetric. Due to space limitations on the substrate, the paralleled semiconductor switches T3.1 /T3.2 and T2.1/T2.2 cannot be placed directly next to each other to form a symmetric load current through the layout. It appears that the load current path length from IN through T3.1 to the central island is shorter than the corresponding path length through T3.2. Therefore, to enforce symmetry, intentionally longer bond wires W1 and W4 are used for T3.1 and T2.2 in comparison with the standard shorter bond wires used for W2 and W3. By adjusting the lengths of bond wires involved in the respective signal paths, the difference between the signal paths in terms of signal propagation times or in terms of stray inductance can be minimized. In an embodiment, the symmetry may be achieved by increasing the loop height of the bond wire in a power module as shown in Fig 11 . The DBC substrates are formed by a sandwich of Cu 1320, Ceramics 1330 and Cu 1340, where the upper Cu layer 1340 holds semiconductor switches 1310. The DBC substrates are connected via bond wires. As shown in Fig. 11 , the bond wire WB has an increased loop height compared to the bond wire WA. The standard bond wire WA may be used as W2 and W3 of Fig. 10, while the increased bond wire WB may be used as W1 and W4 of Fig. 10.

Alternatively, if there is sufficient space available in the module, the start and end positions of the bond wires may be placed further apart or closer together in order to respectively increase or decrease the length of the bond wires. In such an embodiment, the loop height of the bond wire may be increased, decreased, or left at an optimum height for ease of production. In Fig. 10, the distance between start at the end positions of bond wires W1 and W4 is increased relative to that used for bond wires W3 and W2. The final electrical symmetry of the completed system is a combination of the electrical characteristics of the copper layer 1220, the start and end points of the wirebonds, and the loop height of the wirebonds. Such characteristics can be modelled at the design stage and/or measured and corrected by the building of prototypes.

It can be appreciated that the measures for achieving symmetry described in the load circuit embodiments are also applicable to the control circuit embodiment. Similarly, the measures for achieving symmetry described in the control circuit embodiments are applicable to the load circuit embodiments. By designing the load circuit structure for each paralleled semiconductor switches and the control circuit as identical as possible, it is not necessary to derate the current of the power module. Therefore, higher output current can be achieved at unchanged costs. Each semiconductor switch having the same load current means each semiconductor switch facing the same thermal stress, which leads to improved reliability.

The disclosure has been described above with reference to embodiments thereof. It should be understood that various modifications, alternations and additions can be made by those skilled in the art without departing from the spirits and scope of the disclosure. Therefore, the scope of the disclosure is not limited to the above particular embodiments but only defined by the claims as attached.