Title:
POWER SEMICONDUCTOR MODULE
Document Type and Number:
WIPO Patent Application WO/2021/014692
Kind Code:
A1
Abstract:
Provided is a highly reliable power semiconductor module in which a plurality of semiconductor chips are arranged in parallel on an insulated substrate. The power semiconductor module makes it possible to densely package the semiconductor chips, and there is little difference in operating characteristics between the semiconductor chips. The present invention is characterized by comprising an insulated substrate, a first conductive pattern that is arranged on the insulated substrate, a plurality of power semiconductor chips that are arranged on the first conductive pattern, bridge-shaped first wiring that directly connects gate electrodes of the plurality of power semiconductor chips, and bridge-shaped second wiring that directly connects source electrodes of the plurality of power semiconductor chips. The present invention is also characterized in that the first wiring is arranged along the second wiring such that the angle formed between the first wiring and the second wiring is no more than 30 degrees.
Inventors:
MASUDA TORU (JP)
HAYAKAWA SEIICHI (JP)
TAKAYANAGI YUJI (JP)
HAYAKAWA SEIICHI (JP)
TAKAYANAGI YUJI (JP)
Application Number:
PCT/JP2020/015565
Publication Date:
January 28, 2021
Filing Date:
April 06, 2020
Export Citation:
Assignee:
HITACHI POWER SEMICONDUCTOR DEVICE LTD (JP)
International Classes:
H01L25/07; H01L25/18
Domestic Patent References:
| WO2019044748A1 | 2019-03-07 |
Foreign References:
| JP2007234690A | 2007-09-13 | |||
| JP2010087400A | 2010-04-15 | |||
| JP2019068035A | 2019-04-25 |
Attorney, Agent or Firm:
POLAIRE I.P.C. (JP)
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