TECHNICAL FIELD

The disclosure relates to the field of chip embedding technology for manufacturing power electronic packages and assemblies. In particular, the disclosure relates to a prepackage module for embedding into a multilayer printed circuit board (PCB), a method for its production and a multilayer PCB. Specifically, a prepackage with integrated isolation is disclosed.

BACKGROUND

Due to the numerous advantages chip embedding has been successfully used for power packaging for several years. However, chip embedding is used only in low voltage and low power applications. Further development of chip embedding technology is desired for high power and high voltage applications. For that, high voltage compatibility, current carrying capability and thermal performance seem the main challenges or limitations. With known CE (chip embedding or component embedding technology) it seems difficult to meet the high power and high voltage requirements. Especially the current carrying capability is limited due to limited Cu volume and poorer thermal performance compared to currently used modules.

SUMMARY

This disclosure provides a solution for overcoming limitations of the used chip embedding technologies as described above.

The foregoing and other objectives are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

This disclosure provides a solution for conducting generated heat away from embedded power components to a heat sink (or case) and providing at the same time good isolation between the heat sink (or case) and module.

In particular, a prepackage module is disclosed that effectively transfers generated heat from at least one component to a heat sink. The prepackage module provides short, direct and effective heat path(s) between the at least one component and heat sink, and at the same time a good electrical isolation. As described in this disclosure, manufacturing of a prepackage including integrated highly thermally conductive isolation is disclosed. This prepackage contains one or several power dies, Cu posts and optionally passives that are bonded on a compact ceramic substrate. This prepackage can be embedded inside a multilayer PCB and can be connected to the PCB with laser pvias or blind mechanical vias (mechanically drilled holes that do not penetrate through the complete PCB). Substrate materials that can be used, are for example, direct plated copper (DPC) substrates, direct bonded copper (DBC) substrates or IMS (Isolated Metal Substrate) type substrates. In IMS substrates, isolation is polymer-based (not ceramic). Optionally, IMS substrates can be used in a similar way as ceramic substrates.

As disclosed herein, manufacturing of a prepackage module with integrated thermally conductive isolation and embedding the module inside the printed circuit board is feasible. The printed circuit board can also be a “power module” or a smart power module or intelligent power module. In other words, the achievements are: 1) compact prepackage with integrated isolation; 2) combination of prepackage with integrated isolation and embedding. Package options and process flow are explained in embodiments 1-4 listed below. Structure and process flow are explained in embodiments 5 and 6 described below.

The procedure described in this disclosure can be applied for “Double Side Cooled (DSC) Embedded Component Package (ECP) module for next or future generation” modules. The same applies for HV (e.g., up to 1200V, 500A) applications and higher power classes, i.e., higher than 1200V, 500A.

Embodiments presented in this invention disclosure are:

1. Single die prepackage with integrated ceramic isolation, as described below with respect to Figure 1 ;

2. Multi-die prepackage with integrated ceramic isolation, as described below with respect to Figure 2;

3. Prepackage for single or multi-die with integrated organic isolation, as described below with respect to Figure 1 ;

4. Prepackage manufacturing (example), as described below with respect to Figure 3;

5. Process flow and final structure of the product where the isolated prepackages are embedded inside a multilayer PCB, as described below with respect to Figures 4a and 4b;

6. Structure for a multilayer PCB with embedded isolated prepackages, as described below with respect to Figure 5. In order to describe the disclosure in detail, the following terms, abbreviations and notations will be used:

PCB printed circuit board

DPC Direct Plated Copper

DBC Direct Bonded Copper

AMB Active Metal Brazing

PTH Plated Through Hole

HDI PCB High Density Interconnect Printed Circuit Board

PPG Prepreg pvia Microvia

IMS Insulated metal substrate

CE Chip Embedding

ECP Embedded Component Package or Packaging

L/S Line/Space

DSC Double Side Cooled

LTCC Low Temperature Co-fired Ceramics

Build up: Laminated printed circuit board layer on both sides (symmetrical structure) of the 2 layer FR4 (or other printed circuit board material)

Prepreg: Non cured FR4 resin sheet with glass fiber reinforcement that is used in PCB manufacturing to laminate different printed circuit board core layers together or to manufacture build up layers (prepreg + Cu foils) pvia: Laser drilled small size via (60-200pm) between printed circuit board build up layers that connects Cu layers electrically together

DPC: Direct plated copper. Ceramic substrate where copper (typically 10um to

140um) is plated to one or both sides of the ceramic material. Top side (or both sides) of the substrate can be structured and used for wiring

DBC: Direct bonded copper. Ceramic substrate where copper sheet or sheets

(typically 140um-350um) are bonded to one or both sides of the ceramic material by using high-temperature oxidation process. Top side (or both sides) of the substrate can be structured and used for wiring

IMS: Insulated metal substrate (Al, Cu) that consist from 2 different metal layers that are isolated from each other’s with polymer based dielectric layer (epoxy, PI)

AMB: AMB means active metal brazing and is the latest development in ceramic substrates. The copper is joined/brazed directly to the ceramic substrate in vacuum and in high temperature. The brazing also allows to use very thick Cu thicknesses (up to 800pm). CE/ECP: Chip embedding or embedded component packaging. Packaging technology where bare dies typically with Cu metallization are embedded inside PCB material and connected to the Cu routing on the package top with plated pvias HDI PCB: High Density Interconnect PCB is a printed circuit board that has higher wiring density per unit area than known printed circuit boards. Due to smaller L/S pm the copper thickness has thickness limitations (e.g., 30pm/30pm — > 10-15pm and 75pm/75pm — > 30-35pm). Process is using thin Cu seed layers (1-12pm), pattern plating (Cu plated inside a structured photoresist) and laser pvias

In this disclosure, chip embedding technologies are described. There are several different types of embedding processes available: In a typical chip embedding process, the electronic components (chips, capacitors, resistors, etc.) are either placed inside an opening in a PCB core layer or soldered on a two or multilayer PCB. The actual embedding inside the final manufactured PCB can be performed by laminating FR4 prepregs or other polymer sheets above and below the core layer that holds the components to be embedded. The electrical connection between the embedded components and the PCB metal layers can be formed by soldering the component terminals to the inner laminate layers and subsequently laminating the PCB layers together. In more advanced embedding technologies, the components can be electrically connected by galvanically filled micro vias which is more robust, since there is no remelting of solder inside the package or board, which has to be considered when mounting the other components to the outer layers of the PCB. The micro vias are usually formed after lamination by laser drilling from the top surface through the thin laminate layer to the active chip pads or to the terminals of an embedded component package.

Through-hole technology refers to the mounting scheme used for electronic components that involves the use of leads on the components that are inserted into holes drilled in printed circuit boards (PCB) and soldered to pads on the opposite side either by manual assembly (hand placement) or by the use of automated insertion mount machines. In through-hole technology, the components are mounted on the PCB by inserting their leads through the respective hole. These holes are called through holes since they are drilled from the top to the bottom of the board.

When using plated through holes, the inner wall of the holes is covered with a thin layer of copper, which makes the entire inner hole area conductive. This conductivity benefit establishes an electrical connection between components and copper tracks. It also enhances mechanical stability and reduces the overall resistance to support smooth current flow. The average Cu plating thickness is minimum 20pm. As electronic components become more integrated and complex, double-sided and multi-layered PCBs were developed along with plated through holes, so that components may connect to the desired layers, whenever required.

According to a first aspect, the disclosure relates to a prepackage module for embedding into a multilayer printed circuit board, PCB, the prepackage module comprising: a power semiconductor component comprising at least two terminals, wherein a first terminal is formed on a top side of the power semiconductor component and a second terminal is formed on one of the top side or a bottom side of the power semiconductor component, the bottom side opposing the top side; an electrically isolating and thermally conductive substrate for transfer of heat from the power semiconductor component to a heat sink, the substrate having a top side and a bottom side opposing the top side, the substrate comprising: a first metal layer mounted at the top side of the substrate, the first metal layer being structured to form at least one contact pad; a second metal layer mounted at the bottom side of the substrate; and a thermally conductive isolation material layer placed between the first metal layer and the second metal layer for electrically isolating the first metal layer from the second metal layer; wherein the second terminal of the power semiconductor component is attached to a first contact pad of the first metal layer; a mold body at least partly encapsulating the power semiconductor component and the substrate, the mold body having an upper main face and a lower main face opposing the upper main face; a first electrically and thermally conductive spacer electrically contacting the first terminal of the power semiconductor component, the first electrically and thermally conductive spacer extending from the first terminal to the upper main face of the mold body; and a second electrically and thermally conductive spacer electrically contacting the first contact pad of the first metal layer, the second electrically and thermally conductive spacer extending from the first metal layer to the upper main face of the mold body.

This prepackage module efficiently conducts the generated heat away from the embedded power semiconductor component towards the heat sink and guarantees at the same time good electrical isolation between the heat sink and the power semiconductor component.

The prepackage module effectively transfers the generated heat from the power semiconductor component to the heat sink by providing short, direct and effective heat paths between the power semiconductor component(s) and the heat sink and at the same time a good electrical isolation.

The power semiconductor component can be a vertical device with Source and Gate on top side and Drain on bottom side. The power semiconductor component can also be a lateral current flow device (e.g., GaN), with all power contacts on the top side. The power semiconductor component can also be a diode or another component with two electrical contacts, one on top side and one on bottom side.

The electrically and thermally conductive spacers can be metal spacers. Alternatively, the spacers can be made of CERMET materials like AlSiC or carbon nanotube infused metals.

In an exemplary implementation of the prepackage module, a third terminal of the power semiconductor component is formed on the top side of the power semiconductor component; wherein the prepackage module further comprises: an electrical connector electrically connecting the third terminal of the power semiconductor component with a second contact pad of the first metal layer; and a third electrically and thermally conductive spacer electrically contacting the second contact pad of the first metal layer, the third electrically and thermally conductive spacer extending from the first metal layer to the upper main face of the mold body.

This provides the advantage that the power semiconductor component can be a three-terminal component such as a transistor or any other switch with a control terminal.

The electrical connector may be a wire bond, ribbon bond or Cu clip, for example. In one exemplary implementation, the power semiconductor chip or component can also be flip chip bonded face down to the substrate (in such a case space mounted on back side of the die).

In an exemplary implementation of the prepackage module, a third terminal of the power semiconductor component is formed on the top side of the power semiconductor component; wherein the prepackage module further comprises: a third electrically and thermally conductive spacer electrically contacting the third terminal of the power semiconductor component, the third electrically and thermally conductive spacer extending from the third terminal to the upper main face of the mold body.

In this case, the third terminal, e.g., Gate pad, has to be large enough to attach the third spacer on it.

This provides the advantage that no wire bond station is needed in an otherwise wirebondless production scenario. This can reduce production complexity.

In an exemplary implementation of the prepackage module, the bottom side of the substrate covered by the second metal layer is left uncovered by the mold body, the bottom side of the substrate forming a main heat channel for heat transfer between the power semiconductor component and the heat sink.

This provides the advantage that the bottom side of the substrate can be directly coupled to the heat sink which improves heat transfer away from the power semiconductor component.

In an exemplary implementation of the prepackage module, each of the electrically and thermally conductive spacers comprises a top side and a bottom side opposing the top side, the top side being formed planar to the top side of the mold body; wherein the top sides of the electrically and thermally conductive spacers form at least one of: an electrical connection between the power semiconductor component and a top side of the prepackage module, or an auxiliary heat channel for heat transfer between the power semiconductor component and a further heat sink.

This provides the advantage that a common plane on the top side of the mold body can be used for an efficient and easy electrical connection of the terminals of the power semiconductor component or as an auxiliary heat channel connected to an auxiliary heat sink.

In an exemplary implementation of the prepackage module, the substrate comprises a ceramic-based substrate comprising one or a combination of the following: Direct Plated Copper, DPC, Direct Bonded Copper, DBC or Active Metal Brazing, AMB; Direct Bonded Aluminum, DBA, LTCC ((Low Temperature Co-fired Ceramics) and other possible option and/or the isolation material layer comprises one or a combination of the following: Alumina Oxide, AI2O3, Aluminum Nitride, AIN or Silicon Nitride, SiN.

This provides the advantage that the ceramic-based substrate has excellent heat dissipation properties.

In an exemplary implementation of the prepackage module, the ceramic-based substrate is only applied for the main heat channel extending between the power semiconductor component and the heat sink.

This provides the advantage that the ceramic-based substrate can electrically insulate the power semiconductor component from the heat sink for the main heat channel. In an exemplary implementation of the prepackage module, the substrate comprises an Insulated Metal Substrate, IMS; and/or the isolation material layer comprises an organic polymer material with good thermal properties.

This provides the advantage of an alternative substrate with excellent thermal properties as alternative to a ceramic-based substrate.

In an exemplary implementation of the prepackage module, the second metal layer is nonstructured, forming a homogeneous heat transfer layer for heat transfer between the power semiconductor component and the heat sink.

This provides the advantage that such a second metal layer can be easily manufactured. Besides, heat transfer can be improved by such a homogeneous structure.

In an exemplary implementation of the prepackage module, the power semiconductor component comprises a die with vertical current flow and/or a die with lateral current flow.

This provides the advantage of flexibility in design, since both types of dies can be used, dies with vertical current flow as well as dies with lateral current flow.

In an exemplary implementation of the prepackage module, the prepackage module comprises: at least one second power semiconductor component comprising at least two terminals, wherein a first terminal is formed on a top side of the at least one second power semiconductor component and a second terminal is formed on a bottom side of the at least one second power semiconductor component, the bottom side opposing the top side; wherein the second terminal of the at least one second power semiconductor component is attached to a third contact pad of the first metal layer.

This provides the advantage that a multi-die prepackage module can be implemented, e.g., a prepackage module having multiple embedded power semiconductor components. By such multi-die prepackage module different combinations of high-side or low-side switches can be realized. In particular, different kinds of connections between power semiconductor switches can be realized to form recurring building blocks of a variety of power conversion topologies.

In an exemplary implementation of the prepackage module, the prepackage module comprises: a second electrical connector electrically connecting the first terminal of the at least one second power semiconductor component with the first contact pad of the first metal layer; and a fourth electrically and thermally conductive spacer electrically contacting the third contact pad of the first metal layer, the fourth electrically and thermally conductive spacer extending from the first metal layer to the upper main face of the mold body.

This provides the advantage that the terminals of both power semiconductor components can be easily electrically connected from the upper main face of the mold body.

In an exemplary implementation of the prepackage module, the second electrical connector comprises a ribbon bond or a wire bond.

This provides the advantage that the second power semiconductor component can be easily connected with the (first) power semiconductor component by applying available connection procedures.

In an exemplary implementation of the prepackage module, the second electrical connector and the second electrically and thermally conductive spacer are forming a copper clip electrically connecting the first terminal of the at least one second power semiconductor component with the second terminal of the power semiconductor component; wherein the copper clip is exposed from the mold body.

This provides the advantage that such a copper clip improves thermal and electrical connectivity by providing larger connection areas.

In an exemplary implementation of the prepackage module, the power semiconductor component and the at least one second power semiconductor component are configured to form a half-bridge configuration.

This provides the advantage that by such half-bridge configuration different combinations of high-side or low-side switches can be realized. In particular, compact implementations of different kinds of power conversion topologies can be realized.

According to a second aspect, the disclosure relates to a multilayer printed circuit board, PCB, comprising at least one prepackage module according to the first aspect described above.

This provides the advantage that the prepackage modules can be efficiently applied as basic components for the multilayer PCB. The multilayer PCB can be the final PCB or main PCB or mother board that also has the power infrastructure and cooling infrastructure integrated (like bus bars for current transport, driver circuit, heatsink, etc.)

This multilayer PCB can also be a power module or intelligent power module or smart power module but without further power infrastructure. Then it would have a connection interface to be connected to a main board, busbar, heatsink, driver board, etc.

In an exemplary implementation, the multilayer PCB comprises: one or more PCB layers arranged between the second metal layer of the at least one prepackage module and the heat sink, the one or more PCB layers comprising multiple microvias for heat transfer between the power semiconductor component and the heat sink.

This provides the advantage that multilayer PCBs with embedded components inside can be formed which have improved thermal and electrical properties.

According to a second aspect, the disclosure relates to a method for manufacturing a prepackage module for embedding into a multilayer printed circuit board, the method comprising: providing an electrically isolating and thermally conductive substrate for transfer of heat from the power semiconductor component to a heat sink, the substrate having a top side and a bottom side opposing the top side, the substrate comprising: a first metal layer mounted at the top side of the substrate, the first metal layer being structured to form at least one contact pad; a second metal layer mounted at the bottom side of the substrate; and a thermally conductive isolation material layer placed between the first metal layer and the second metal layer for electrically isolating the first metal layer from the second metal layer; providing a power semiconductor component comprising at least two terminals, wherein a first terminal is formed on a top side of the power semiconductor component and a second terminal is formed on one of the top side or a bottom side of the power semiconductor component, the bottom side opposing the top side; attaching the second terminal of the power semiconductor component to a first contact pad of the first metal layer; electrically contacting the first terminal of the power semiconductor component by a first electrically and thermally conductive spacer; electrically contacting the first contact pad of the first metal layer by a second electrically and thermally conductive spacer; encapsulating the power semiconductor component, the substrate and the electrically and thermally conductive spacers at least partly by a mold body, the mold body having an upper main face and a lower main face opposing the upper main face; wherein the first electrically and thermally conductive spacer is extending from the first terminal to the upper main face of the mold body; and wherein the second electrically and thermally conductive spacer is extending from the first metal layer to the upper main face of the mold body.

By such method, a prepackage module can be manufactured which efficiently conducts the generated heat away from the embedded power semiconductor component towards the heat sink and guarantees at the same time good isolation between the heat sink and the power semiconductor component. The method provides an effective transfer of the generated heat from the power semiconductor component to the heat sink by the manufacture of short, direct and effective heat paths between the power semiconductor component(s) and the heat sink and at the same time a good electrical isolation.

In particular, the method ensures effective use of expensive high-performance substrate material because it is employed as close to the power semiconductor component(s) as possible, and by this kept as small in size as possible.

This method can be applied to both kind of devices, e.g., devices with vertical current flow as well as devices with lateral current flow. Note that for power dies with vertical current flow (like GaN) the second terminal can be only for thermal purposes. In GaN devices, the substrate (the second terminal) is usually also connected electrically. This is important to properly define the substrate potential. Usually, the substrate can be connected to source potential, and there is no high current flow through this connection.

When applying the method to lateral devices like GaN, an exemplary embodiment is manufacturing a flip-chip on (DPC) substrate. This way, a better heat extraction path that does not lead through the GaN EPI and GaN substrate can be achieved.

The terminals of the power semiconductor component can be electrically and/or thermally connected by electrically and thermally conductive spacers attached to the respective contact pads of the power semiconductor component. Alternatively, e.g., in the case that the contact pads are too small for attaching a spacer, in particular for Gate pads, the contact pads can be connected by wire bonds, ribbon bonds, Cu clips, etc. to other contact pads of larger size onto which spacers can be mounted. The die can also be mounted face down (flip chip bonding), with or even without Cu spacer mounted on back side of the die.

In an exemplary implementation of the method, the method comprises: attaching the power semiconductor component to the substrate by soldering, diffusion soldering, sintering or conductive adhesives. This provides the advantage that attaching the power semiconductor component to the substrate will result in a prepackage module having excellent thermal and electrical properties.

In an exemplary implementation of the method, the method comprises: attaching the first electrically and thermally conductive spacer to the top side of the power semiconductor component by soldering, diffusion soldering, sintering or conductive adhesives; and attaching the second electrically and thermally conductive spacer to the substrate by soldering, diffusion soldering, sintering, conductive adhesives, electro-welding, friction stir welding, ultrasonic welding, laser assisted welding, thermo-sonic bonding.

For the attaching of the second spacer, there is no sensitive die. This provides the advantage that more energy can be used to make the connection.

These manufacturing steps can be used as alternatives for attaching the first electrically and thermally conductive spacer to the top side of the power semiconductor component. Each of them results in the production of a prepackage module having excellent thermal and electrical properties.

In an exemplary implementation of the method, the method comprises: embedding the prepackage module inside a multilayer PCB; electrically connecting the prepackage module with plated vias; and applying stacked or staggered vias from the bottom side of the substrate to the heat sink for heat conduction.

Such method provides a flexible design of the multilayer PCB having excellent thermal and electrical properties. More details are presented below.

The disclosure presents a new type of package specifically for chip embedding that has an integrated isolation.

This allows to use the expensive ceramic materials more efficiently: concentrated in the chip- near heat-path, only in areas where isolation & thermal conductivity are required at the same time (Alternatively, use of organic polymer-based isolation material with enhanced thermal conductivity, e.g., use of BN or other type of fillers, nano-fillers, etc.).

This allows more degrees of freedom on package/system level since isolation is already taken care of at prepackage level. No need to worry about vertical clearance at the cost of cooling performance. Chip embedding can be used more efficiently allowing more complex designs otherwise not possible or with high cost on ceramic substrates.

The prepackage and embedding process is designed specifically for HV embedding purposes but can be also used for other purposes. The following advantages can thus be achieved:

The die is protected from non-clean PCB materials and the HV reliability is expected to improve.

Better creepage and leakage current prevention by use of epoxy mold compounds that usually have higher purity than the PCB materials used for chip embedding.

Increase of product lifetime due to higher HV reliability.

Improved thermal performance and isolation between the module and heat sink can be achieved since the thermal pad is on the bottom side of the prepackage that is isolated from the bond pad with ceramic material that has high thermal conductivity (thermal conductive up to 230 W/mK).

The presented new type of prepackage for power die embedding provides the advantageous effect of enabling of HV for chip-embedding using standard PCB materials by avoiding direct chip contact of those materials.

The presented prepackage with integrated high-voltage insulation provides the advantageous effect of die protection against PCB material impurities. Those are particular limiting for HV power applications. This allows more degrees of freedom in design of the package/system, and no wasted area due to package external insulation considerations on board level.

The chip-scale insulated prepackage provides lowest possible use of ceramic area to avoid high cost of ceramic substrate area.

The chip-near insulation interface allows efficient use of best available isolation material with high thermal conductivity.

A heat path with only high thermally conductive material (>230 W/mK possible) allows higher current capability in comparison to non-isolated prepackages with limited copper thickness.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the disclosure will be described with respect to the following figures, in which: Figure 1 shows a schematic cross section of a single die prepackage module 100 for embedding into a multi-layer PCB 500 according to a first and third embodiment;

Figure 2 shows a schematic cross section of a multi-die prepackage module for embedding into a multi-layer PCB 500 according to a second embodiment;

Figure 3 shows a schematic diagram illustrating two process flows for single die prepackage with ceramic substrate according to a fourth embodiment, where process steps 301-304 represent a process flow for purely space-based contact elements and process steps 311-315 represent a process flow for wire bond based gate contacts in case the gate pad is too small for spacer attach;

Figure 4a and 4b show schematic diagrams illustrating a process flow to embed and connect prepackage inside 2-layer PCB and laminate additional build up layers according to a fifth embodiment;

Figure 5 shows a schematic cross section of a single die prepackage module according to a first aspect prior to embedding and two single die prepackage modules after embedding into a multilayer PCB according to a second aspect of this disclosure; and

Figure 6 shows a schematic diagram illustrating a method 600 for manufacturing a prepackage module for embedding into a multi-layer PCB according to the disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

Figure 1 shows a schematic cross section of a single die prepackage module 100 for embedding into a multi-layer PCB 500 according to a first and third embodiment. In the following the prepackage module 100 is described in general, while the first embodiment and the third embodiment are described below in more detail. The prepackage module 100 can be embedded into a multilayer PCB, e.g., as shown in Figure 5.

The prepackage module 100 comprises: a power semiconductor component 140 comprising at least two terminals 141 , 142. A first terminal 141 is formed on a top side 140a of the power semiconductor component 140. A second terminal 142 is formed on one of the top side 140a or a bottom side 140b of the power semiconductor component 140. The bottom side 140b is opposing the top side 140a.

The prepackage module 100 comprises: an electrically isolating and thermally conductive substrate 130 for transfer of heat from the power semiconductor component 140 to a heat sink 510 (shown in Figure 5). For example, the substrate 130 can be an integrated isolation with high thermal conductivity substrate. The substrate 130 has a top side 130a and a bottom side 130b opposing the top side 130a.

The substrate 130 comprises: a first metal layer 131a, 131b mounted at the top side 130a of the substrate 130. The first metal layer 131a, 131 b is structured to form at least one contact pad. The substrate 130 comprises a second metal layer 132 mounted at the bottom side 130b of the substrate 130. The substrate 130 comprises a thermally conductive isolation material layer 133 placed between the first metal layer 131a, 131 b and the second metal layer 132 for electrically isolating the first metal layer 131a, 131b from the second metal layer 132.

The second terminal 142 of the power semiconductor component 140 is attached to a first contact pad 131a of the first metal layer 131a, 131 b.

The prepackage module 100 comprises: a mold body 150 at least partly encapsulating the power semiconductor component 140 and the substrate 130. The mold body 150 has an upper main face 150a and a lower main face 150b opposing the upper main face 150a. The encapsulant, i.e., mold body 150 can also be on left and right side (in the picture) of the substrate 130 (e.g., ceramic substrate). In one example, molding can be done after singulation of the ceramic modules.

The prepackage module 100 comprises: a first electrically and thermally conductive spacer 111 electrically contacting the first terminal 141 of the power semiconductor component 140. The first electrically and thermally conductive spacer 111 is extending from the first terminal 141 to the upper main face 150a of the mold body 150. The prepackage module 100 comprises: a second electrically and thermally conductive spacer 112 electrically contacting the first contact pad 131a of the first metal layer 131a, 131b. The second electrically and thermally conductive spacer 112 is extending from the first metal layer 131a, 131b to the upper main face 150a of the mold body 150.

The power semiconductor component can be a vertical device with Source and Gate on top side and Drain on bottom side. The power semiconductor component can also be a lateral power component (e.g., GaN) where all electrical power contacts are on top side. The power semiconductor component can also be a diode or another component with two electrical contacts, one on top side and one on bottom side.

The electrically and thermally conductive spacers can be metal spacers. Alternatively, the spacers can be made of CERMET materials like AlSiC or carbon nanotube infused metals.

A third terminal 143 of the power semiconductor component 140 is formed on the top side 140a of the power semiconductor component 140.

The prepackage module 100 may further comprise: an electrical connector 114 electrically connecting the third terminal 143 of the power semiconductor component 140 with a second contact pad 131b of the first metal layer 131a, 131 b.

The prepackage module 100 may further comprise: a third electrically and thermally conductive spacer 113 electrically contacting the second contact pad 131 b of the first metal layer 131a, 131 b. The third electrically and thermally conductive spacer 113 may be extending from the first metal layer 131a, 131b to the upper main face 150a of the mold body 150.

The electrical connector 114 may be a wire bond, ribbon bond or Cu clip, for example.

The prepackage module 100 may further comprise: a third electrically and thermally conductive spacer 113 electrically contacting the third terminal 143 of the power semiconductor component 140. The third electrically and thermally conductive spacer 113 may be extending from the third terminal 143 to the upper main face 150a of the mold body 150.

In this case, the third terminal, e.g., Gate pad, has to be large enough to attach the third spacer on it. The bottom side 130b of the substrate 130 covered by the second metal layer 132 may be left uncovered by the mold body 150. The bottom side 130b of the substrate 130 may be forming a main heat channel for heat transfer between the power semiconductor component 140 and the heat sink.

Each of the electrically and thermally conductive spacers 111 , 112, 113 may comprise a top side and a bottom side opposing the top side. The top side may be formed planar to the top side 150a of the mold body 150.

The electrically and thermally conductive spacer 111 may form a Source terminal, the electrically and thermally conductive spacer 112 may form a Drain terminal, the electrically and thermally conductive spacer 113 may form a Gate terminal.

The top sides of the electrically and thermally conductive spacers 111 , 112, 113 may form at least one of: an electrical connection between the power semiconductor component 140 and a top side of the prepackage module 100, or an auxiliary heat channel for heat transfer between the power semiconductor component 140 and a further heat sink.

According to the first embodiment, the substrate 130 may comprise a ceramic-based substrate comprising one or a combination of the following: Direct Plated Copper, DPC, Direct Bonded Copper, DBC or Active Metal Brazing, AMB, Direct Bonded Aluminum, DBA, LTCC ((Low Temperature Co-fired Ceramics) and other possible option and/or the isolation material layer 133 may comprise one or a combination of the following: Alumina Oxide, AI2O3, Aluminum Nitride, AIN or Silicon Nitride, SiN. The ceramic-based substrate may only be applied for the main heat channel extending between the power semiconductor component 140 and the heat sink.

According to the first embodiment, the substrate 130 may comprise an Insulated Metal Substrate, IMS; and/or the isolation material layer 133 may comprises an organic polymer material.

The second metal layer 132 may be non-structured, forming a homogeneous heat transfer layer for heat transfer between the power semiconductor component 140 and the heat sink.

The power semiconductor component 140 may comprise a die with vertical current flow and/or a die with lateral current flow. In the following the specific details of the first embodiment and the third embodiment are described.

The first embodiment describes single die prepackage with integrated ceramic isolation. The ceramic substrate that is used can be DPC, DBC or AMB substrate, Direct Bonded Aluminum, DBA, LTCC ((Low Temperature Co-fired Ceramics) and other possible option and the material can be e.g., Aluminum Nitride (AIN), Alumina Oxide, Silicon Nitride (SiN).

DPC substrate (Direct Plated Copper) is a ceramic substrate where copper is plated to one or both sides of the ceramic material. Instead of copper, also aluminum can be used. The copper thickness is typically from 10um to 140um. Top side Cu is typically structured and the bottom side Cu is non-structured because it is used to make the good thermal connection to the heat sink or case. DPC substrates can have through-ceramic via connections.

DBC substrate (Direct Bonded Copper) is a ceramic substrate where the copper sheets are bonded to the ceramic material by using high-temperature oxidation process. The copper thickness can be slightly thicker than in DPC (typically from 140um to 350um). Like in DPC the top side Cu is typically structured and while the bottom side Cu is non-structured because it is used to make the good thermal connection to the heat sink or case.

AMB is the latest development in ceramic substrates. The copper is joined/brazed directly to the ceramic substrate in vacuum and in high temperature and due to that the Cu thickness can be very thick (up to 800pm).

LTCC (Low Temperature Co-fired Ceramics) is a multi-layer glass ceramic (2 or more layers) substrate that can be manufactured by sintering all ceramic layers and metal structures together at the same time in lower sintering temperatures (less than 1000°C). The substrate is a combination of glass and alumina. This kind of ceramic substrate can be beneficial in more complicated modules where components are flip chip mounted and that may include also driver, controller, passives.

The ceramic material can be e.g., Alumina Oxide (AI2O3), Aluminum Nitride (AIN) or Silicon Nitride (SiN). The Alumina Oxide (AI2O3) is the most common material used in Ceramic substrates. The material is relatively cheap, it is excellent electrical insulator, but the thermal conductivity is not very high (24-29W/mK). Aluminum Nitride (AIN) has much higher thermal conductivity than Aluminum Oxide (150-170W/mK), very low CTE, high insulation resistivity, high mechanical strength and it is suitable for high frequency applications due to low signal loss but it is more expansive than Aluminum Oxide. The thermal conductivity value of Silicon Nitride (SiN) is between AI2O3 and AIN (85-90W/mK), it has very low CTE and it is very strong and suitable for high frequency applications due to low signal loss.

The cross section of the package is shown in figure 1 (only example and not limited on to the structure presented in the picture). The basic idea is to bond the power die on a ceramic substrate and bring all contacts to the package top side with Cu spacers (more detailed process flow explained in embodiment 4). The bottom side of the package is used for thermal connection. The ceramic substrate also isolates the die and circuity from back side contact but at the same time allows an effective heat transfer from the die to the backside of the package.

Figure 1 shows the power die (Mosfet, IGBT, SiC, etc.), i.e., power semiconductor component 140 that is bonded (soldering, diffusion soldering, sintering, etc.) face up (source and gate up) on a substrate. The drain of the die can be connected to the metal plate on the ceramic substrate. The drain plain extends outside of the die area and copper spacer is soldered to the same metal plate. The gate is wire bonded to a separate landing pad where also a second copper spacer is soldered onto. On top of the source pad a third Cu spacer is soldered. The whole module is protected by molding material and the soldered Cu spacers are exposed by e.g., grinding or milling. The mold can cover the ceramic substrate side wall (in case individual ceramic substrate are used of molding is done after separation) or the side walls of the ceramic can be exposed (if separation is done after molding). The picture shows a die with vertical current flow but also dies with lateral current flow can be used.

The third embodiment describes a version of a single die or multi die prepackage that is using integrated organic polymer-based isolation. The package using IMS substrate is similar than in embodiments 1 and 2 and the main difference is the substrate type. Unlike in embodiments 1 and 2 where the isolation between top and bottom side of the substrate was done with ceramic materials, in this embodiment the isolation is done by using organic polymer material. IMS substrate is an insulated metal substrate that consists of two different metal layers that are connected together and isolated from each other with organic polymer based dielectric layer (filled epoxies, PI, etc). The metal layers on both sides can typically be from 100pm to 1 mm or more and the layer thickness can vary in both sides of the module. Usually the top metal layer is thinner and structured, whereas the bottom metal layer is thicker and unstructured, as it provides the mechanical stability and thermal interface. Like in ceramic substrates the top side of the substrate can be patterned. The top side metal is Cu (but not limited to) and the bottom side can be Cu or Al. The insulated metal substrate (IMS) consists of a metal baseplate, a thin of dielectric layer and top Cu layer. The base plate can be Cu or Al but aluminum is commonly used because of its low cost and density. The thickness of the base plate is typically 100pm - 1mm or even thicker. The Cu layer is typically from 35 to 300 pm thick. The isolation layer between the top metal layer and bottom metal layer is typically epoxy based and it might include also glass fibers (FR4) but also other polymer materials can be used (PI, etc). Due to the relatively low thermal conductivity of the polymer materials (typically from 0,4 to 3 W/mK) the layer thickness is kept as thin as possible (typically ~100pm but depends on the voltage class and isolation requirements). Higher thermal conductivity is preferred and under development (some polymer materials are available/under development up to 10W/mK. Compared to a known PCB, the IMS provides a better heat dissipation but is not as good as the ceramic substrates. Recently, IMS insulation materials with improved thermal conductivity of up to 10 W/(m*K) are claimed by suppliers (thermal cladding), which can promote its use in other applications.

Figure 2 shows a schematic cross section of a multi-die prepackage module 100a, 100b for embedding into a multi-layer PCB 500 according to a second embodiment.

The structure of the multi-die prepackage module 100a, 100b is similar to the structure of the single die prepackage module 100 described above with respect to Figure 1.

For the multi-die prepackage module 100a, 100b, the prepackage module 100 described above with respect to Figure 1 additionally comprises: at least one second power semiconductor component 240 comprising at least two terminals 241 , 242. The first terminal 241 is formed on a top side 240a of the at least one second power semiconductor component 240. A second terminal 242 is formed on a bottom side 240b of the at least one second power semiconductor component 240. The bottom side 240b is opposing the top side 240a.

The second terminal 242 of the at least one second power semiconductor component 240 is attached to a third contact pad 131c of the first metal layer 131a, 131b.

The prepackage module 100a, 100b may further comprise a second electrical connector 214 electrically connecting the first terminal 241 of the at least one second power semiconductor component 240 with the first contact pad 131a of the first metal layer 131a, 131 b.

The prepackage module 100a, 100b may further comprise a fourth electrically and thermally conductive spacer 212 electrically contacting the third contact pad 131c of the first metal layer 131a, 131 b. The fourth electrically and thermally conductive spacer 212 may be extending from the first metal layer 131a, 131 b to the upper main face 150a of the mold body 150.

The second electrical connector 214 may comprise a ribbon bond or a wire bond as shown for the prepackage module 100a in the top of Figure 2.

The second electrical connector 214 and the second electrically and thermally conductive spacer 112 may be forming a copper clip electrically connecting the first terminal 241 of the at least one second power semiconductor component 240 with the second terminal 142 of the power semiconductor component 140 as shown for the prepackage module 100b in the bottom of Figure 2. The copper clip is exposed from the mold body 150.

The power semiconductor component 140 and the at least one second power semiconductor component 240 may be configured to form a half-bridge configuration.

The second embodiment describes multi-die prepackage with integrated ceramic isolation. The material and process used for multi-die package variant is similar to that of single die prepackage (described in embodiment 1). The cross section of half bridge prepackage is shown in figure 2. The multi-die package can include two or more dies and optionally additional passives. The routing is done in one layer on top of the ceramic substrate and all connections are brought to the top side of the molded package with Cu spacers or Cu clips. Figure 2 shows a half bridge package where the power die 1 is connected same way than in single die variant. The source of the Power die 2 is connected with wire bond, ribbon bond or Cu clip to the drain pad of the power die 1 and brought to the top of the package with soldered Cu clip. The solution is not limited to half bridge configurations but also other multi die configurations can be manufactured (e.g., paralleled dies, etc.). The number of the dies is not limited, it can be from 2 to 12 or even more but in ideal case it is smaller (2-6) so that the module area can be kept small.

Figure 3 shows a schematic diagram illustrating two process flows for single die prepackage with ceramic substrate according to a fourth embodiment. The substrate may be an integrated isolation with high thermal conductivity substrate, e.g. DPC, e.g., as described above with respect to Figure 1. Process steps or blocks 301-304 represent a process flow for purely space-based contact elements and process steps 311-315 represent a process flow for wire bond based gate contacts in case the gate pad is too small for spacer attach. The fourth embodiment describes a manufacturing process flow for isolated prepackage. The manufacturing process is similar to normal molded packages and ceramic modules.

In process block 301 , the integrated isolation with high thermal conductivity substrate 130, e.g., DPC, is provided. The substrate 130 may be a substrate as described above with respect to Figure 1. I.e., the substrate 130 comprises: a first metal layer 131a, 131 b mounted at the top side 130a of the substrate 130. The first metal layer 131a, 131 b is structured to form at least one contact pad. The substrate 130 comprises a second metal layer 132 mounted at the bottom side 130b of the substrate 130. The substrate 130 comprises a thermally conductive isolation material layer 133 placed between the first metal layer 131a, 131b and the second metal layer 132 for electrically isolating the first metal layer 131a, 131 b from the second metal layer 132.

Process block 302 comprises soldering, diffusion soldering or sintering of the dies 140.

Process block 303 comprises soldering, diffusion soldering or sintering of the Cu spacers, e.g., conductive spacers 111 , 112, 113 as described above with respect to Figure 1 .

Process block 304 comprises molding 150 and exposure of the Cu spacers 111 , 112, 113.

In process block 311 , i.e., first process block of the process flow for wire bond based gate contacts, the integrated isolation with high thermal conductivity substrate 130, e.g., DPC, is provided. The substrate 130 may be a substrate as described above with respect to Figure 1.

Process block 312 comprises soldering, diffusion soldering or sintering of the dies 140.

Process block 313 comprises wire bonding 114 of the Gate connection.

Process block 314 comprises soldering, diffusion soldering or sintering of the Cu spacers 111 , 112, 113, e.g., conductive spacers 111 , 112, 113 as described above with respect to Figure !

Process block 315 comprises molding 150 and exposure of the Cu spacers 111 , 112, 113.

The electrically and thermally conductive spacer 321 may form a Source terminal, the electrically and thermally conductive spacer 322 may form a Drain terminal, the electrically and thermally conductive spacer 323 may form a Gate terminal, the electrically and thermally conductive spacer 324 may form another Drain terminal. Depending on the module size and ceramic substrate size individual substrates or larger multi substrate panels can be used. The first process step is to print the solder (or sinter paste) on the substrate, place the component (face up or face down, depending on the design) on the correct position and reflow solder the components. After soldering an optional cleaning can be done and the gate connection is done with wire bonding (in case the gate pad is large enough a Cu spacer can also be used). Next step is to dispense the solder (or sinter paste) on the substrate and the source pad of the die. The Cu spacers are mounted with a normal pick and place machine (unless pressure sintering is used, in such case a die bonder is required to apply the necessary pressure and heat) and soldered with normal reflow process. In case of larger panels with multiple substrates on one panel the substrates can be separated before molding. After molding the Cu spacers are exposed with grinding or milling and the modules are tested.

The process flow shown in Figure 3 is only an example and it can be modified or changed depending on the manufacturer and module design.

Figure 4a and 4b show schematic diagrams illustrating a process flow to embed and connect a prepackage inside 2-layer PCB and laminate additional build up layers according to a fifth embodiment.

The fifth embodiment describes the process flow and final structure of the product where the isolated prepackages, i.e., the prepackage modules 100 described above with respect to Figure 1 , are embedded inside a multilayer PCB. The process flow to embed the prepackages 100 inside the final manufactured PCB 500 as shown in the last diagram in Figure 4b and in Figure 5 is relatively simple. The process starts by forming openings 411 into the core layer 410 (e.g., FR4) where the module 100 will be embedded. This can be done by routing, punching or laser cutting (the core layer can be replaced also with several thinner cores and/or prepreg layers). Next step is lay-up 401 and lamination 402, where a lamination stack 430 is build and all layers 421 , 422, 423, 424 are laminated together with normal PCB vacuum lamination. The lay-up 401 consists at least of a bottom Cu foil 424, prepreg 423, core layer 410 with openings 411 and the prepackage module 100 that are placed inside the openings 411 , prepreg 422 and top Cu foil 421. After the lamination process vias 441 to connect to module top side and back side are done by via drilling, e.g., laser drilling or mechanical drilling 403 (depth drilled blind vias 441 that extend only to the Cu of the module 100). After drilling 403 the vias 441 are filled with Cu 442 with electrochemical plating and pattern is formed by plating and structuring 404 on both sides of the PCB with photolithography process and etching. After this process the product 450 is ready for final finishing or in case of multilayer PCB 500 for additional build up layer manufacturing process(es).

It follows build up layer manufacturing process. Additional build up layers 451 , 452, 453, 454 (1 or more) can be manufactured 405, 406 on both sides of the panel by second lamination, via drilling, plating and structuring 405 and 3 ^rd lamination, via drilling, plating and structuring 406. The process flow of each build up layer 451 , 452, 453, 454 includes a lay-up and lamination step (Cu foil + prepreg + PCB with embedded module + prepreg + Cu foil), via drilling (laser dilling and or mechanical drilling), plating, lithography and etching. This process can be done as many times as needed to achive the correct PCB structure. After all layers 451 , 452, 453, 454 are manufactured the surface is covered with solder mask and the visible metal structures are covered with solderable surface finishing (e.g. ENIG, etc).

Figure 5 shows a schematic cross section of a single die prepackage module 100 according to a first aspect prior to embedding and two single die prepackage modules 100 after embedding into a multilayer PCB 500 according to a second aspect of this disclosure.

The multilayer PCB 500 shown in Figure 5 may comprise at least one prepackage module 100 as described above with respect to Figure 1 or at least one prepackage module 100a, 100b as described above with respect to Figure 2.

The multilayer PCB 500 may comprise: one or more layers 511 arranged between the second metal layer 132 of the at least one prepackage module 100 and the heat sink 510.

The one or more layers 511 may comprise multiple microvias 512 or mechanically depth-drilled blind vias for heat transfer between the power semiconductor component (140) and the heat sink. Currently the structure should be symmetrical, but in the future (with development) the structure may be nonsymmetrical, meaning that additional layers on the bottom side may be removed or number r on those reduced.

In particular, Figure 5 shows the schematic cross section from the module that is mounted on the heat sink 510. As can be seen from the figure the back sides of all embedded modules are connected with multiple vias to the outer-next metal layer (in the figure at the bottom side) and finally to the outermost metal layer of the PCB. The top side of the modules are connected to the PCB layer above where the necessary routing is done. The heat sink 510 on the back side can be connected (illustrated by the thick arrow) to the PCB directly with soldering, with TIM or thermal grease. If needed passive component and the remaining active components can be soldered on top side of the PCB or an additional heat sink can be mounted on top side of the PCB by using isolating TIM material.

Figure 6 shows a schematic diagram illustrating a method 600 for manufacturing a prepackage module for embedding into a multi-layer PCB according to the disclosure.

The method 600 comprises: providing 601 an electrically isolating and thermally conductive substrate 130 for transfer of heat from the power semiconductor component 140 to a heat sink, the substrate 130 having a top side 130a and a bottom side 130b opposing the top side 130a, the substrate 130 comprising: a first metal layer 131a, 131b mounted at the top side 130a of the substrate 130, the first metal layer 131a, 131 b being structured to form at least one contact pad; a second metal layer 132 mounted at the bottom side 130b of the substrate 130; and a thermally conductive isolation material layer 133 placed between the first metal layer 131a, 131 b and the second metal layer 132 for electrically isolating the first metal layer 131a, 131 b from the second metal layer 132.

The method 600 comprises: providing 602 a power semiconductor component 140 comprising at least two terminals 141 , 142, wherein a first terminal 141 is formed on a top side 140a of the power semiconductor component 140 and a second terminal 142 is formed on one of the top side 140a or a bottom side 140b of the power semiconductor component 140, the bottom side 140b opposing the top side 140a.

The method 600 comprises: attaching 603 the second terminal 142 of the power semiconductor component 140 to a first contact pad 131a of the first metal layer 131a, 131 b.

The method 600 comprises: electrically contacting power semiconductor component 604, i.e. , the first terminal 141 of the power semiconductor component 140 by a first electrically and thermally conductive spacer 111.

The method 600 comprises: electrically contacting substrate metal layer 605, i.e., the first contact pad 131a of the first metal layer 131a, 131b by a second electrically and thermally conductive spacer 112.

The method 600 comprises: encapsulating 606 the power semiconductor component 140, the substrate 130 and the electrically and thermally conductive spacers 111 , 112 at least partly by a mold body 150, the mold body 150 having an upper main face 150a and a lower main face 150b opposing the upper main face 150a, wherein the first electrically and thermally conductive spacer 111 is extending from the first terminal 141 to the upper main face 150a of the mold body 150; and wherein the second electrically and thermally conductive spacer 112 is extending from the first metal layer 131a, 131b to the upper main face 150a of the mold body 150.

This method can be applied to both kind of devices, e.g. devices with vertical current flow as well as devices with lateral current flow. Note that for power dies with vertical current flow (like GaN) the second terminal can be only for thermal purposes. In GaN devices, the substrate (the second terminal) is usually also connected electrically. This is important to properly define the substrate potential. Usually, the substrate can be connected to source potential, and there is no high current flow through this connection.

Note that the terminals of the power semiconductor component 140 can be electrically and/or thermally connected by electrically and thermally conductive spacers attached to the respective contact pads of the power semiconductor component 140. Alternatively, e.g., in the case that the contact pads are too small for attaching a spacer, in particular for Gate pads, the contact pads can be connected by wire bonds, ribbon bonds, Cu clips, etc. to other contact pads of larger size onto which spacers can be mounted.

The method 600 may further comprise: attaching the power semiconductor component 140 to the substrate 130 by soldering, diffusion soldering, sintering or conductive adhesives.

The method 600 may further comprise: attaching the first electrically and thermally conductive spacer 111 to the top side 140a of the power semiconductor component 140 by soldering, diffusion soldering, sintering or conductive adhesives; and attaching the second electrically and thermally conductive spacer 112 to the substrate 130 by soldering, diffusion soldering, sintering, conductive adhesives, electro-welding, friction stir welding, ultrasonic welding, laser assisted welding or thermo-sonic bonding.

The method 600 may further comprise: embedding the prepackage module 100 inside a multilayer PCB; electrically connecting the prepackage module 100 with plated vias; and applying stacked or staggered vias from the bottom side 130b of the substrate 130 to the heat sink for heat conduction.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.