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Patent Searching and Data


Title:
PROCESS CHAMBER AND PARALLELISM TESTING METHOD
Document Type and Number:
WIPO Patent Application WO/2023/216958
Kind Code:
A9
Abstract:
Disclosed in the present application are a process chamber and a parallelism testing method. The process chamber comprises a chamber body and a chamber cover plate covering on the chamber body. A bearing device is provided with a bearing surface for bearing a wafer; a dielectric plate has a first surface arranged opposite to the bearing surface and a second surface far away from the bearing surface; a testing assembly comprises a processor and a plurality of testers arranged on the chamber cover plate; in the projection direction of each tester on the bearing surface, a first distance is formed between the second surface and the corresponding tester, a second distance is formed between the first surface and the bearing surface, and a third distance is formed between each tester and the bearing surface; the testers measure the corresponding first distances, and then the processor calculates the difference value between each two of the plurality of second distances according to the plurality of first distances and a plurality of pre-obtained third distances, and compares the absolute values of the plurality of difference values with a preset threshold value separately; and a plurality of leveling assemblies are connected to the dielectric plate. The present application achieves simple operation and high efficiency in testing and leveling a process chamber.

Inventors:
WANG YUEJIAO (CN)
LIU ZHENHUA (CN)
LI YUNFEI (CN)
ZHAO ZHONGSHENG (CN)
GUO SHIXUAN (CN)
Application Number:
PCT/CN2023/092025
Publication Date:
January 04, 2024
Filing Date:
May 04, 2023
Export Citation:
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Assignee:
BEIJING NAURA MICROELECTRONICS EQUIPMENT CO LTD (CN)
International Classes:
H01J37/32; G01B21/24; H01L21/67
Attorney, Agent or Firm:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS (CN)
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