Title:
PROCESSING MULTI-CYCLE COMMANDS IN MEMORY DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS
Document Type and Number:
WIPO Patent Application WO/2021/112955
Kind Code:
A8
Abstract:
Methods of operating a memory device are disclosed. A method may include receiving, at a first die of a number of dies, a first number of bits including one or more command bits, one or more identification bits, and a first number of address bits associated with a command during a first clock cycle. The method may further include conveying, from the first die to at least one other die, at least some of the first number of bits. Further, the method may include receiving, at the first die, a second number of bits including a second number of address bits associated with the command during a second, subsequent clock cycle. Also, the method may include conveying, from the first die to the at least one other die, at least some of the second number of bits. Memory devices and electronic systems are also disclosed.
Inventors:
VANKAYALA VIJAYAKRISHNA J (US)
Application Number:
PCT/US2020/055198
Publication Date:
June 30, 2022
Filing Date:
October 12, 2020
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
G11C7/22; G06F3/06; G11C5/04; G11C8/12; G11C8/18
Attorney, Agent or Firm:
NIXON, Jason P. et al. (US)
Download PDF:
Previous Patent: TILTING MECHANISM WITH TELESCOPING ACTUATOR
Next Patent: WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS
Next Patent: WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS