Title:
PROCESSOR AND DATA PATH RECONSTRUCTION METHOD
Document Type and Number:
WIPO Patent Application WO/2021/182223
Kind Code:
A1
Abstract:
A processor (10) in which a plurality of PEs (16) are two-dimensionally arranged to perform parallel processing deactivates, upon detection of a malfunction of a PE (16), all PEs (16) included in at least one of the row and the column including the malfunctioning PE (16), and performs processing without using the deactivated PEs (16). To this end, each PE (16) has a normal state data path (30A) for exchanging data with another PE (16) which is adjacent and has a deactivation state data path (30B) for exchanging data with yet another PE (16) which is adjacent but with one in between. A PE (16) adjacent to a deactivated PE (16) does not exchange data with the deactivated PE (16) using the normal state data path (30A) but exchanges data with another PE (16) using the deactivation state data path (30B).
Inventors:
HIROTSU TEPPEI (JP)
Application Number:
PCT/JP2021/008133
Publication Date:
September 16, 2021
Filing Date:
March 03, 2021
Export Citation:
Assignee:
NSITEXE INC (JP)
DENSO CORP (JP)
DENSO CORP (JP)
International Classes:
G06F15/177
Foreign References:
| JP2014038494A | 2014-02-27 | |||
| JPS62274454A | 1987-11-28 |
Attorney, Agent or Firm:
SUZUKI Mamoru et al. (JP)
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