Title:
PROCESSOR AND REGISTER INHERITANCE METHOD
Document Type and Number:
WIPO Patent Application WO/2020/213397
Kind Code:
A1
Abstract:
A processor (100) is equipped with: a plurality of PEs (114); a thread scheduler (110) for allocating threads to the plurality of PEs (114); a register file (104) shared by the plurality of PEs (114); a register controller (108) for assigning a register region used by a thread in the register file (104); and a management table (116) in which information identifying a thread and a register, and the address of the register region assigned to the relevant register, are stored in association with each other. When the register used by a previous thread is inherited by a subsequent thread, the register controller (108) does not release the register region to be inherited even after the process of the previous thread has finished, and uses the information identifying the subsequent thread and register to rewrite the information in the management table (116) associated with the address of the relevant register region to be inherited.
Inventors:
ISHIWATARI KAZUYOSHI (JP)
NEMOTO MANABU (JP)
NEMOTO MANABU (JP)
Application Number:
PCT/JP2020/014996
Publication Date:
October 22, 2020
Filing Date:
April 01, 2020
Export Citation:
Assignee:
NSITEXE INC (JP)
DENSO CORP (JP)
DENSO CORP (JP)
International Classes:
G06F9/34; G06F9/38; G06F9/46; G06F17/16
Foreign References:
| JPH1078880A | 1998-03-24 | |||
| US20100161948A1 | 2010-06-24 |
Attorney, Agent or Firm:
SUZUKI Mamoru et al. (JP)
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