Technical Field

[0001] This disclosure relates generally to the field of semiconductor devices, and more specifically, to lll-N transistor devices/arrangements with modified profiles that allow reducing contact resistance to two-dimensional (2D) electron gas (2DEG).

Background

[0002] Solid-state devices that can be used in high voltage and/or high frequency applications are of great importance in modern semiconductor technologies. For example, power management integrated circuits (PM IC) and radio frequency integrated circuits (RFIC) may be critical functional blocks in system on a chip (SoC) implementations. Such SoC implementations may be found in mobile computing platforms such as smartphones, tablets, laptops, netbooks, and the like. In such implementations, the PM IC and RFIC are important factors for power efficiency and form factor, and can be equally or even more important than logic and memory circuits.

[0003] Due, in part, to their large bandgap and high mobility, lll-N material based transistors, such as e.g. gallium nitride (GaN) based transistors, may be particularly advantageous for high voltage and/or high frequency applications. For example, because GaN has a larger band gap (-3.4 eV) than silicon (Si; ~1.1 eV), a GaN transistor should be able to withstand a larger electric field (resulting e.g. from applying a large voltage to the drain, Vdd) before suffering breakdown, compared to a Si transistor of similar dimensions. Furthermore, GaN transistors may advantageously employ a 2D electron gas (i.e. a group of electrons, an electron gas, free to move in two dimensions but tightly confined in the third dimension, e.g. a 2D sheet charge) as its transport channel, enabling high mobilities without using impurity dopants. For example, the 2D sheet charge may be formed at an abrupt hetero-interface formed by epitaxial deposition, on GaN, of a charge-inducing film of a material having larger spontaneous and piezoelectric polarization, compared to GaN (such a film is generally referred to as a "polarization layer"). Providing a polarization layer on a lll-N material such as GaN allows forming very high charge densities, e.g. densities of about 2-10 ¹³ charges per square centimeter (cm ² ), without impurity dopants, which, in turn, enables high mobilities, e.g. mobilities greater than about 1000 cm ² /(V-s).

[0004] Despite the advantages, challenges arising from damage during manufacturing process of III- N transistors hinder their large-scale implementation. Improvements in that respect are always desirable. Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIG. 1 is a cross-sectional side view of an exemplary MOSFET.

[0007] FIG. 2 is a cross-sectional side view providing a schematic illustration of conventional epitaxial growth of a doped semiconductor material in S/D etch-out regions in a lll-N transistor.

[0008] FIG. 3 is a cross-sectional side view providing a schematic illustration of epitaxial growth of a doped semiconductor material in S/D etch-out regions in a lll-N transistor with an undercut in the channel material, in accordance with various embodiments.

[0009] FIGS. 4A-4C provide enlarged views of various portions of the cross-sectional side view as shown in FIG. 3 which include different undercut profiles shown for S/D etch-out regions, in accordance with various embodiments.

[0010] FIG. 5 provides a schematic illustration of an exemplary real-life structure with an undercut profile as described herein, according to some embodiments of the present disclosure.

[0011] FIG. 6 is a flow diagram of an example method of manufacturing a lll-N transistor incorporating an undercut profile in S/D etch-out regions, in accordance with various embodiments.

[0012] FIGS. 7A and 7B are top views of a wafer and dies that include one or more lll-N transistors incorporating an undercut profile in S/D etch-out regions in accordance with any of the

embodiments disclosed herein.

[0013] FIG. 8 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more lll-N transistors incorporating an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein.

[0014] FIG. 9 is a cross-sectional side view of an IC device assembly that may include one or more lll-N transistors incorporating an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein.

[0015] FIG. 10 is a block diagram of an example computing device that may include one or more III- N transistors incorporating an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein.

Detailed Description

[0016] During operation of a transistor, current flows between source and drain terminals of the transistor. Therefore, resistance associated with source and drain (S/D) contact regions affects performance of a transistor. Disclosed herein are transistor devices/arrangements which address the S/D contact resistance issues when a channel material of a transistor includes one or more of group III semiconductor material(s) and nitrogen (i.e. when a transistor is a "lll-N transistor"), e.g. a GaN transistor. Proposed transistor arrangements incorporate an undercut profile in the channel material bordering S/D etch-out regions, where, as used herein "S/D etch-out regions" refer to regions/openings where the channel material is etched out so that one or more doped

semiconductor materials for forming future S/D regions of a transistor can be deposited. Thus, a portion of the channel material between a source region and a drain region has an undercut profile at an interface with the S/D etch-out regions on each side of the undercut portion. As described in greater detail below, providing an undercut profile in S/D etch-out regions promotes/increases growth of substantially monocrystalline doped semiconductor, e.g. doped InGaN, in those regions, forming future S/D regions (also referred to as "diffusion regions" or "highly doped (HD) regions" of the transistor) to which S/D electrodes will be connected to. In particular, due to the undercut profile of the channel material in the S/D etch-out regions, during the subsequent epitaxial growth of the doped semiconductor material to form future S/D regions of a transistor, highly crystalline form of the epitaxially grown doped semiconductor can wrap around the ledge(s) of the channel material and make contact to the 2DEG of the lll-N channel material, inhibiting growth of polycrystalline doped semiconductor which has inferior conductivity compared to the same doped semiconductor in its monocrystalline form. As a result, contact resistance to the 2DEG in the channel material may be decreased, thus improving performance of lll-N transistors.

[0017] As is known in the art, monocrystalline materials (also referred to as "monocrystalline solids" or "single crystal materials") refer to materials in which the crystal lattice of the entire sample is substantially continuous and unbroken to the edges of the sample, with no grain boundaries. An opposite of a monocrystalline material is a fully amorphous material (i.e. a material having no crystallinity at all). In between fully amorphous (no crystallinity) and single crystalline materials (100% single phase single orientation long range order with zero imperfections) there is a wide spectrum of materials with varying level of crystallinity. In the present disclosure, the term "highly crystalline" is used to describe materials at least 80% of which, preferably at least 90% of which, is in a single crystal/monocrystalline form but which may also include some defects (e.g. dislocations, grain boundaries, etc.), polycrystals, or other imperfections/issues which make the materials just short of being monocrystalline.

[0018] lll-N transistors having an undercut profile in S/D etch-out regions as described herein may be implemented in one or more components associated with an integrated circuit (IC) or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

[0019] For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0020] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which are shown, by way of illustration, embodiments that may be practiced. The accompanying drawings are not necessarily drawn to scale. For example, to clarify various layers, structures, and regions, the thickness of some layers may be enlarged. Furthermore, while drawings illustrating various structures/assemblies of exemplary devices may be drawn with precise right angles and straight lines, real world process limitations may prevent implementations of devices exactly as shown. Therefore, it is understood that such drawings revised to reflect example real world process limitations, in that the features may not have precise right angles and straight lines, are within the scope of the present disclosure. Drawings revised in this manner may be more representative of real world structure/assemblies as may be seen on images using various characterization tools, such as e.g. scanning electron microscopy (SEM) or transmission electron microscopy (TEM). In addition, the various structures/assemblies of the present drawings may further include possible processing defects, such as e.g. the rounding of corners, the drooping of the layers/lines, unintentional gaps and/or discontinuities, unintentionally uneven surfaces and volumes, etc., although these possible processing defects may not be specifically shown in the drawings. It is to be understood that other embodiments may be utilized and structural or logical changes to the drawings and descriptions may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0021] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0022] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0023] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. Furthermore, stating in the present disclosure that any part (e.g. a layer, film, area, or plate) is in any way positioned on or over (e.g. positioned on/over, provided on/over, located on/over, disposed on/over, formed on/over, etc.) another part means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located

therebetween. On the other hand, stating that any part is in contact with another part means that there is no intermediate part between the two parts.

[0024] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0025] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. In some examples, as used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. In another example, the term "connected" means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

[0026] For purposes of illustrating lll-N transistors having an undercut profile in S/D etch-out regions as proposed herein, it is important to understand the phenomena that may come into play in a typical transistor. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. For example, in the following, some descriptions are provided with reference to GaN transistors that use doped InGaN as the doped semiconductor material of choice for forming S/D regions. However, descriptions provided herein are equally applicable to transistors employing group lll-N semiconductor channel materials other than GaN, and/or to transistors employing doped semiconductor materials other than InGaN for S/D regions.

[0027] The performance of a transistor may depend on a number of factors. For example, one factor is mobility of charge carriers (i.e. electrons for an N-type channel or holes for a P-type channel) in a channel of a transistor. All else equal, a material with a higher carrier mobility enables carriers to move more quickly in response to a given electric field than a material with a lower carrier mobility; thus, high carrier mobilities may be associated with improved performance.

Therefore, new materials are continuously investigated in an attempt to increase channel mobility. However, some materials, while being promising in terms of their carrier mobility, present challenges when it comes to resistance offered by source/drain contact regions when such materials are used as channel materials. Group lll-N semiconductors, such as e.g. GaN, is an example of such materials. Due to their higher mobility and larger bandgap, lll-N channel materials are promising candidates for transistor nodes used e.g. in high voltage and/or high frequency applications.

However, the external resistance of the source/drain contacts regions that can be achieved with such channel materials is a significant performance limiting factors for lll-N transistors. This problem will be explained further with reference to FIGS. 1 and 2.

[0028] FIG. 1 is a cross-sectional side view of an exemplary metal-oxide-semiconductor field-effect transistor (MOSFET) 100. As shown in FIG. 1, the transistor 100 includes a substrate 102 on which a channel material 104 is provided, with S/D regions 106 provided on either side of a channel portion 108 of the channel material 104.

[0029] The substrate 102 may be any substrate on which lll-N transistors as described herein may be implemented. In some embodiments, the substrate 102 may include a semiconductor, such as silicon. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-N or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

[0030] In some embodiments, the substrate 102 may include an insulating layer, sometimes referred to as an "interlayer dielectric" material (ILD), such as an oxide isolation layer, e.g. to electrically isolate the semiconductor material of the substrate 102 from the S/D regions 106 and the channel material 104, and thereby mitigate the likelihood that a conductive pathway will form between a source and a drain regions 106 through the substrate 102. Examples of ILDs that may be included in/on a substrate 102 in some embodiments may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride.

[0031] In general, the channel material 104 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In particular, for exemplary N-type transistor embodiments, the channel material 102 may advantageously be a lll-N material having a high electron mobility, such as, but not limited to GaN, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material 104 may be a ternary lll-N alloy, such as InGaAs or GaAsSb. For some ln _x Gai- _x As fin embodiments, In content (x) is between 0.6 and 0.9, and advantageously is at least 0.7 (e.g., lno.7Gao.3As).

[0032] In some embodiments, the channel material 104 may be formed of a highly crystalline semiconductor, e.g. of substantially a monocrystalline semiconductor. In some embodiments, the channel material 104 may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material 104 may be a binary, ternary, or quaternary lll-N compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

[0033] In some embodiments, the channel material 104 may be an intrinsic lll-N semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material 104, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material 104 may be relatively low, for example below 10 ¹⁵ cm ³ , and advantageously below 10 ¹³ cm ³ .

[0034] As also shown in FIG. 1, the transistor 100 includes S/D regions 106 comprising highly doped semiconductor materials, such as e.g. highly doped InGaN. As is well-known, in a transistor, S/D regions (also sometimes interchangeably referred to as "diffusion regions") are regions of doped semiconductors, e.g. regions of doped channel material, so as to supply charge carriers for the transistor channel 108 of the transistor 100. Often, the S/D regions are highly doped, e.g. with dopant concentrations of at least above 1-10 ²¹ dopants per cubic centimeter (cm ³ ), in order to advantageously form Ohmic contacts with the respective S/D electrodes (e.g. electrodes 110 shown in FIG. 1), although these regions may also have lower dopant concentrations in some

implementations. Regardless of the exact doping levels, the S/D regions 106 are the regions having dopant concentration higher than in other regions between the source region (e.g. the region 106 shown on the left side in FIG. 1) and the drain region (e.g. the region 106 shown on the right side in FIG. 1), i.e. higher than the channel material 104, and, therefore, are sometimes referred to as HD S/D regions.

[0035] S/D electrodes 110 may be formed of any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, the S/D electrodes 110 may include one or more metals or metal alloys, with metals such as e.g. ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, the S/D electrodes 110 may include one or more electrically conductive alloys oxides or carbides of one or more metals.

[0036] FIG. 1 further illustrates a gate stack 112 provided over the channel portion 108 of the channel material 102. The gate stack 112 includes a dielectric layer 114 and a gate electrode 116.

[0037] The gate dielectric 114 is typically a high-k dielectric (i.e. a dielectric material that has a higher dielectric constant (k) than silicon dioxide) including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 114 during manufacture of the transistor 100 to improve the quality of the gate dielectric 114. The gate dielectric 114 may have a thickness, a dimension measured in the vertical direction in the view of FIG. 1, that may, in some embodiments, be between 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between 1 and 3 nanometers, or between 1 and 2 nanometers).

[0038] The gate electrode 116 may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 100 is a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor (P-type work function metal used as the gate electrode 116 when the transistors 100 is a PMOS transistor and N-type work function metal used as the gate electrode 116 when the transistor 100 is an NMOS transistor). For a PMOS transistor, metals that may be used for the gate electrode material 116 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode 116 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 116 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer.

[0039] Further layers may be included next to the gate electrode material 116 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer, not specifically shown in FIG. 1. Furthermore, in some embodiments, the gate dielectric 114 and the gate electrode 116 may be surrounded by a gate spacer, not shown in FIG. 1, configured to provide separation between the gates of different transistors. Such a gate spacer may be made of a low-k dielectric material (i.e. a dielectric material that has a lower dielectric constant (k) than silicon dioxide which has a dielectric constant of 3.9). Examples of low-k materials that may be used as the dielectric gate spacer may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g. polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon based polymeric dielectric such as e.g.

hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ)). Other examples of low-k materials that may be used as the dielectric gate spacer include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1.

[0040] As described above, one factor that affects performance of transistors such as the transistor 100 is contact resistance from S/D regions 106 to the transistor channel 108. A transistor of a given type and architecture that has lowest-resistance Ohmic contacts yields the best performance. Selective source-drain epitaxy is one of the key performance boosters for conventional silicon (Si) based microelectronics. Unfortunately, applying the same technology to other channel materials, in particular to lll-N based semiconductor materials such as GaN, results in challenges not encountered in current Si based transistors.

[0041] Currently, there are two main approaches to fabricating S/D regions in GaN transistors. The first approach employs tunneling contacts which rely on electron tunneling through a high bandgap polarization layer, e.g. AIGaN. The second approach includes performing S/D etch-out (i.e. removal of the channel material to form openings for depositing the highly doped semiconductor material of the future S/D regions, e.g. highly doped InGaN), followed by selective epitaxy to deposit into the openings the material of the S/D regions. In such an approach, first, an etch process is performed, to create openings/recesses in the channel material 104 in which the material for the S/D regions will later be deposited, and then semiconductor material for the future S/D regions, such as e.g. a group lll-N material or alloy, is epitaxially deposited, possibly doped in situ with dopants such as boron, arsenic, or phosphorous. The second approach is believed to be able to advantageously yield lower contact resistance, compared with the first approach.

[0042] However, while the second approach appears favorable, in practice it yields similar contacts resistance as that of the tunneling contacts. One cause for such poor resistance at the interface of the highly doped InGaN is believed to be the fact that dry etch of lll-N materials such as GaN, carried out to create recesses or openings for depositing the materials of future S/D regions, damages surfaces of the remaining GaN. While typical S/D etch-out for conventional channel materials such as Si can rely on wet cleans to repair crystalline damage (i.e. damage to the pristine substantially monocrystalline structure of the channel material) as well as damage due to growth of native oxide caused by dry etch, no known wet cleans or adequate alternative techniques currently exist for most of the lll-N materials. Therefore, epitaxial growth of InGaN from the damaged etch surfaces is rather poor in that it results in growth of polycrystalline InGaN which has inferior conductivity to monostystalline (i.e. single-crystal) InGaN.

[0043] Poor epitaxial growth of InGaN in conventional implementations of GaN transistors is schematically illustrated in FIG. 2, showing the transistor 100 as shown in FIG. 1 (hence the descriptions provided with respect to FIG. 1 are applicable to FIG. 2) but at an earlier stage of fabrication. Namely, FIG. 2 illustrates S/D etch-out regions 202, i.e. openings formed in the channel material 104, into which the highly doped semiconductor will be deposited to form the S/D regions 106.

[0044] Since surfaces of GaN which are damaged due to the etching process used to form the openings 202 (i.e. surfaces within the S/D etch-out regions 202 indicated in FIG. 2 with thick black lines) result in growth of polycrystalline material when doped InGaN is epitaxially grown, currently approaches include forming ledges 204, by recessing the hardmark over the channel portion 108 of the transistor, i.e. the gate stack 112 is not provided over the entire length of the channel portion 108, so that it would be aligned with the edges of S/D regions, but is centered over the middle part of the channel portion 108. Ledges 204 of the channel material 104 are illustrated in FIG. 2 as horizontal surfaces, or protrusions, projecting or extending from the portion of the channel material 104 over which the gate stack 112 is provided towards each of the S/D etch out regions 202 where future S/D regions of the transistor will be formed. The idea is that, because the ledges 204 (i.e. the upper horizontal surfaces of the channel material 104) are not damaged by the etching process for forming S/D etch-out openings 202 (or not damaged as much as the inner surfaces of the openings 202), when epitaxial growth of doped InGaN begins, these ledges will serve as nucleation sites for forming monocrystalline doped InGaN. Such monocrystalline InGaN will nucleate and wrap around the ledges 204 (i.e. get onto the inner surface of the S/D etch-out openings 202), thus connecting to the channel portion 108. Such a monocrystalline doped InGaN grown from and wrapping around the ledges 204 is schematically illustrated in FIG. 2 with rectangular portions 206 having well-defined facets. On the other hand, polycrystalline doped InGaN also grown as a result of performing epitaxial growth process is schematically illustrated in FIG. 3 with semi-oval portions 208 not having well-defined facets.

[0045] Embodiments of the present disclosure are based on recognition that growth of the monocrystalline doped semiconductor 206 in the S/D etch-out regions 202 will compete with growth of the polycrystalline doped semiconductor 208: the more polycrystalline material 208 grows on the surfaces of the S/D etch-out regions 202 closest to the channel 108, the higher the contact resistance of the final S/D regions, and the worse the performance of the transistor 100 will be. Embodiments of the present disclosure are further based on recognition that changing the shape of the S/D etch out regions 202 may allow to tip the balance between growth of the monocrystalline portions 206 and the polycrystalline portions 208 in such a way that the growth of the polycrystalline doped semiconductor is somewhat suppressed or inhibited and the growth of the monocrystalline doped semiconductor is enhanced or promoted. Namely, according to various embodiments of the present disclosure, the S/D etch-out regions are created so that the channel material bordering these regions has an undercut profile, as e.g. shown in FIG. 3.

[0046] FIG. 3 is a cross-sectional side view providing a schematic illustration of epitaxial growth of a doped semiconductor material for forming S/D regions in a lll-N transistor 300 with an undercut channel material, in accordance with various embodiments. The transistor 300 is similar to the transistor 100 shown in FIGS. 1 and 2. To illustrate that, some reference numerals used in FIG. 3 are the same used in FIGS. 1 and 2, indicating that they refer to the same or similar elements as those shown in FIGS. 1 and 2, such as e.g. the substrate 102, the channel material 104, the channel portion 108, the gate stack 112 with the gate dielectric 114 and the gate electrode 116, and the ledges 204. Descriptions of these elements provided above are applicable to the transistor 300 and, therefore, in the interests of brevity, are not repeated. Instead, the differences with respect to FIGS. 1 and 2 are described. Furthermore, while portions 206 in the transistor 300 are described herein as the "monocrystalline" doped semiconductor 206, in some implementations these portions may instead be of highly crystalline doped semiconductor (i.e. may have imperfections in the perfectly monocrystalline lattice structure of the semiconductor).

[0047] In contrast to conventional S/D etch-out regions 202 as shown in FIG. 2, the transistor 300 is formed by creating S/D etch-out regions 302 so that a portion of the channel material 104 in between the S/D etch-out regions 302 (and, hence, the portion of the channel material 104 in between the final S/D regions) has an undercut profile on at least one side of that portion of the channel material. In other words, a cross-section of a portion of the channel material 104 has an undercut, i.e. space formed by absence of the channel material from the lower part of a channel structure. For clarity, such a portion of the channel material is shown in an inset AA of FIG. 3 as an undercut portion 304, where the channel material absent to realize the undercut profile of the channel portion 304 is indicated with reference numerals 306. Conversely, the S/D etch-out regions 302 may be described as "undercut S/D etch-out regions," to indicate that they are associated with the undercut portion 304 of the channel material 104.

[0048] FIG. 3 further schematically illustrates a polarization layer 308 which may, optionally, be present within the channel material 104. As described above, the polarization layer 308 (i.e. the material above the dotted line shown in FIG. 3 near the surface of the channel material 104) is a charge-inducing film of a material having larger spontaneous and piezoelectric polarization than that of the bulk (i.e. the rest) of the channel material (i.e. the material below the dotted line shown in FIG. 3), creating a hetero-interface with the bulk portion of the channel material and leading to formation of 2DEG at that interface. In various embodiments, the polarization layer 308 may include materials such as e.g. AIN, InAIN, or AIGaN, and may have a thickness between about 2 and 30 nm, including all values and ranges therein e.g. between about 5 and 15 nm. Although not specifically shown in FIG. 2, such a polarization layer may also be present there.

[0049] Similar to FIG. 2, FIG. 3 illustrates surfaces of the channel material 104 which are likely to be damaged from the etch process used to create the S/D etch-out regions 302 with thick black lines. However, in contrast to FIG. 2, due to the undercut profile in the portion 304, the monocrystalline doped semiconductor 206 is expected to wrap around the etched surface of the channel portion 304 faster than the polycrystalline doped semiconductor 208 can reach that surface, as compared to a scenario where there is no undercut. Thus, providing an undercut below the uppermost surface of the channel material 104 in one or more lateral (i.e. side) portions of the channel material that interface the S/D etch-out regions 302 promotes growth of and, consequently, increases percentage of the monocrystalline doped semiconductor, e.g. doped InGaN, in the final S/D regions (i.e. in the final materials of the S/D regions), in particular in the areas of the S/D regions which contact the 2DEG in the channel portion 108. This is schematically illustrated in FIG. 3 with the portions of the monocrystalline doped semiconductor 206 occupying larger space than the portions of the polycrystalline doped semiconductor 208. In this manner, growth of the polycrystalline doped semiconductor 208 is inhibited/constrained by the growth of the monocrystalline doped

semiconductor 206 which has superior conductivity compared to the polycrystalline semiconductor 208, decreasing contact resistance to the 2DEG in the channel portion 108, thus improving performance of the transistor 300 compared to e.g. that shown in FIG. 2.

[0050] Various dimensions within the transistor 300 may be carefully designed to further promote growth of monocrystalline semiconductor 206 in the areas where it can make contact to the 2DEG of the channel portion. For example, each of the ledges 204 shown in FIG. 3 may measure, in the horizontal direction of FIG. 3, to be about the same as a thickness of the polarization layer 308 (i.e. a ratio of the width of the ledge 204 to the thickness of the polarization layer 308 may be about 1:1) in order to maintain pristine highly crystalline surface from which excellent epitaxial growth can commence. The depth of the S/D etch-out openings 302 (i.e. dimension measured in the vertical direction of FIG. 3) may be selected depending on the thickness of the polarization layer, e.g. the depth may be about at least 5 times larger than the thickness of the polarization layer, e.g. at least about 80 nm, in order to prevent polycrystalline doped semiconductor 208 to be deposited into the S/D etch-out regions from reaching the 2DEG area before the monocrystalline semiconductor 206 reaches it. Further, the angles 310 between the upper surface of the undercut portion 304 its the side walls may be less than about 80 degrees, e.g. be at most 75 degrees, in order to provide sufficient undercut to prevent nucleation of the polycrystalline semiconductor 208 on the sidewalls of the undercut portion 304.

[0051] In some embodiments, the dimensions of the S/D etch-out regions 302 and the dimensions of the undercut portion 304 can take on any suitable values as long as they can be supported by a manufacturing process used to form them. For example, considerations such as e.g. aspect ratio that is possible to achieve with a suitable manufacturing process may have influence on the exact depth of the S/D etch-out regions 302. In another example, considerations such as a particular etching process used may have influence on the exact shape of the undercut portions of the channel material.

[0052] It should be noted that, while illustrations and descriptions provided herein refer to the channel material having an undercut profile in both the source and the drain etch-out regions because such implementations will advantageously promote monocrystalline growth of S/D region material and reduce contact resistance in both the source and the drain regions, in other embodiments, such undercuts may be implemented only on one side (e.g. only in the source etch- out region or only in the drain etch-out region). Similarly, while each of the S/D etch-out regions 302 is shown as a substantially symmetric opening (e.g. with respect to a vertical line of the drawing going through the center of the opening), this is illustrated only because, with typical manufacturing techniques, this is often what is easier, or possible, to manufacture. In general, the S/D etch-out regions 302 do not have to be symmetrical, as long as the side of each opening that is closest to the undercut portion 304 is shaped so as to create an undercut in the channel material, as described herein. Thus, e.g. with reference to FIG. 3, the sidewall shown on the right of the right S/D etch-out region 302 of FIG. 3 and the sidewall shown on the left of the left S/D etch-out region 302 of FIG. 3 may have any profile and do not have to have undercuts as shown in FIG. 3. Still further, while the undercuts are illustrated on each side of the portion 304 with straight tilted lines, i.e. forming a single recess 306 in the portion 304 of the channel material on each side and described in greater detail below, in other embodiments, the undercut on each side may have other shapes and forms, and the undercut on the source side of the channel portion 304 may be different from the undercut on the drain region side of the channel portion 304. In general, any number of undercut features, where each feature may be some kind of a recess or in the channel material 104 to form the undercut portion 304 and may have any three-dimensional (3D) shape (i.e. not necessarily with a straight tilted line profile as shown in FIG. 3) is within the scope of the present disclosure.

[0053] FIG. 4A illustrates an enlarged version of a window 312 of the example shown in FIG. 3, where an exemplary undercut S/D etch-out region 302 has a trapezoidal shape. The polarization layer 308 within the channel material is not specifically shown in FIG. 4A (and subsequent figures) in order to not clutter the drawing.

[0054] FIG. 4A illustrates that an undercut may be achieved by ensuring that a dimension dl of the upper-most portion of the opening of the S/D etch-out region 302 is smaller than a dimension d3 of the lower-most portion. Conversely, this means that the upper-most dimension between the source and drain regions of the undercut portion 304 of the channel material is larger than the lower-most dimension of the undercut portion (as can be seen in the inset AA of FIG. 3). In this context, the terms "upper portion" and "lower portion" refer to portions which are, respectively, further away from and closer to, the substrate 102 on which the channel material 104 is provided. For example, in some embodiments, the difference between the dimension of the upper portion of the channel material of the undercut channel portion 304 may be between about 5 and 300 nanometers larger than the dimension of the lower portion of the channel material of the undercut channel portion 304, e.g. between about 5 and 50 nm, between about 30 and 250 nm, or between about 25 and 300 nm.

[0055] FIG. 4A further illustrates that an undercut in the channel material 104 means that a portion of the channel material 104 is suspended over a portion of the S/D etch-out opening 302, i.e. a portion of the channel material 104 labeled in FIG. 4A with a reference numeral 402 is suspended over a portion 404 of the S/D etch-out region 302. This means, conversely, that a portion of the semiconductor material which will be deposited as the material of the final S/D region will be under a portion of the channel material, i.e. the doped InGaN deposited in the portion 404 will be under the portion 402 of the channel material 102.

[0056] In some embodiments, the upper-most dimension dl of the undercut S/D etch-out opening 302 may be between about 20 and 200 nm, including all ranges and values therein. In some embodiments, the lower-most dimension d3 of the undercut S/D etch-out opening 302 may be between about 35 and 350 nm, including all ranges and values therein. The depth d2 of the undercut S/D etch-out opening 302 may be at least about 80 nm (about at least 5 times larger than the thickness of the polarization layer), e.g. between about 80 and 200 nm, including all ranges and values therein. In some examples, the angle 406 between each of the side walls of the S/D etch-out opening 302 and the bottom of the opening may be about the same as the angle 310, described above, e.g. be less than about 80 degrees, e.g. less than 75 degrees.

[0057] Some examples of other undercut profiles as shown with different shapes of S/D etch-out regions 302 are shown in FIGS. 4B-4C (i.e. the window 312 shown in FIG. 3 may illustrate the features of the S/D etch-out regions 302 as shown in each of FIGS. 4B-4C). Namely, FIG. 4B illustrates the S/D etch-out region 302 implemented as having a substantially circular shape, while FIG. 4C illustrates the S/D etch-out region 302 similar to that shown in FIG. 4A, but implemented with a step profile.

[0058] Reference numerals used to label elements of FIGS. 4B and 4C which are the same as reference numerals used to label elements of FIG. 3 and FIG. 4A are intended to illustrate similar/analogous or same elements and, therefore, discussions of these elements provided with respect to FIG. 3 and FIG. 4A are applicable to FIGS. 4B-4C and, in the interests of brevity, are not repeated for FIGS. 4B-4C. In particular, each of the circularly shaped S/D etch-out region 302 shown in FIG. 4B and the step-shaped S/D etch-out region 302 shown in FIG. 4C may have the upper opening dimension dl, the widest dimension d3, and the depth d2, with the portion 402 of the channel material extending over the undercut portion 404, as described above. FIG. 4C illustrates that the polarization layer 308 may be etched less than the rest of the channel material 104. This may e.g. be advantageous because it may provide preferential epitaxial crystal seeding on and around polarization layer, driving that crystal to contact 2DEG. In some implementations, formation of such an undercut may be a consequence of a particular etch process used because the material of the polarization layer 308 and the material of the rest of the channel material 104 may have different etch properties (i.e. be etch selective).

[0059] Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g. optical microscopy, Transmission Electron Microscopy (TEM), or Scanning Electron Microscopy (SEM), and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g. Physical Failure Analysis (PFA) would allow determination of the undercut profiles as described herein.

[0060] FIG. 5 provides a schematic illustration of an exemplary real-life structure 500 with an undercut profile as described herein, according to some embodiments of the present disclosure. As can be seen, FIG. 5 is drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines. Such a structure could be visible in e.g. an SEM image or a TEM image of a transistor such as the transistor 300.

[0061] FIG. 5 represents a cross-section view similar to that shown in FIG. 3, in particular a view of the undercut portion 304. Elements indicated in FIG. 5 with reference numerals 502, 504, 506, 508, 510, and 514 are similar/analogous to elements indicated with, respectively, reference numerals 102, 104, 206, 208, 308, and 302, described above. Thus, in the interests of brevity, detailed discussions of these elements are not repeated here.

[0062] As shown, FIG. 5 illustrates a structure comprising a channel material 504 provided over a substrate 502. S/D etch-out openings 514 are formed in the channel material 504 (only portions of those openings are shown in Fig. 5), and doped semiconductor material is deposited into the openings by epitaxial growth. In particular, FIG. 5 illustrates that the channel material 504 between the S/D etch-out openings 514 has an undercut below the uppermost surface 503 of the channel material in each of the lateral portions 505 of the channel material (i.e. FIG. 5 illustrates an undercut on the side of a source etch-out opening 514 and another undercut on the side of a drain etch-out opening 514). The epitaxial growth process carried out to fill the S/D etch-out openings 514 with a doped semiconductor material suitable for forming S/D regions of a transistor results in formation of a substantially monocrystalline/highly crystalline form of the doped semiconductor material, shown in FIG. 5 as a material 506 in the openings 514, and of a polycrystalline form of that material, shown in FIG. 5 as a material 508 filling the openings 514. The high level of crystallinity in the material 506 would be seen in an SEM or a TEM image with a diamond-like structures with well-defined edges (as 506 is shown in FIG. 5). In such an image of a real structure, possible processing defects could also be visible, such as e.g. discontinuities in the monocrystalline and/or polycrystalline portions of the doped semiconductor (e.g. as indicated with a discontinuity 516 in the example of FIG. 5), egregious surface roughness that may degrade contact resistance (e.g. as indicated with a rough surfaces 518 in the example of FIG. 5), voids (e.g. as indicated with voids/gaps 520 in the example of FIG. 5), particles in the film, and/or potential intermixing between various layers (i.e. non-discrete interfaces).

[0063] As also shown in FIG. 5, the substantially monocrystalline material 506 may wrap around the ledges of the channel material 504 and make contact with the 2DEG at the interface between a polarization layer 510 of the channel material and the bulk 512 of the channel material. Once the doped semiconductor is grown, the lateral portions 505 of the channel material (i.e. the portions with the undercuts) interfaces (i.e. is in contact with, at least at some points) the doped

semiconductor materials of the source region and the drain region. As used herein, a lateral (i.e. side) portion of the channel material interfacing the source region or the drain region implies that a portion of the channel material is in contact with at least some points/areas of the material(s) of the source region or the drain region (i.e. the interface may be not continuous). Such "interfacing" does not imply that that a portion of the channel material is in contact with the material (s) of the source region or the drain region at all points where these materials are supposed to meet (i.e. does not imply that the interface is continuous). For example, in some implementations, various

imperfections such as gaps (e.g. gaps 520 shown in FIG. 5) and discontinuous coverage (e.g. a discontinuity 516 shown in FIG. 5) by the material (s) of the source/drain regions may prevent formation of a continuous interface. In another example, various intentional or unintentional materials or layers may be formed on/at at least some portions of the intended interface, also preventing formation of a continuous interface between the channel material and the material(s) of the source/drain regions. All of such interfaces are within the scope of the present disclosure.

[0064] In various embodiments, undercut profiles of the channel material at the interfaces with the S/D regions of a transistor, as described herein, may be included in any suitable transistor structure. For example, such structures may be included within transistors having any planar architecture as known in the art, such as e.g. single-gate or double-gate transistors, as well as within transistors having a non-planar architectures such as e.g. tri-gate/FinFET or all-around gate transistors. FinFETs refer to transistors having a non-planar architecture where the channel material is shaped as a fin that extends away from a base. FinFETs are sometimes referred to as "tri-gate transistors," where the name "tri-gate" originates from the fact that, in use, such a transistor may form conducting channels on three "sides" of the fin. FinFETs potentially improve performance relative to single-gate transistors and double-gate transistors. All-around gate transistors refer to transistors where the channel material is shaped as a wire and the gate stack wraps around the wire. All-around gate transistors may form conducting channels on more than three "sides" of the wire, potentially improving performance relative to FinFETs.

[0065] The transistors illustrated in FIGS. 3-5 do not represent an exhaustive set of transistor structures in which an undercut profile in S/D etch-out regions as described herein may be implemented, but merely provide examples of such structures. Although particular arrangements of materials are discussed with reference to FIGS. 3-5, intermediate materials may be included in the transistor devices of these FIGS. Note that FIGS. 3-5 are intended to show relative arrangements of the components therein, and that transistor devices of these FIGS may include other components that are not illustrated (e.g., gate spacers or various interfacial layers). Additionally, although some components of the transistor devices are illustrated in FIGS. 3-5 as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these transistors may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate the transistors.

[0066] Transistors having an undercut profile in S/D etch-out regions as described herein may be manufactured using any suitable techniques. For example, FIG. 6 is a flow diagram of an example method 600 of manufacturing a lll-N transistor incorporating an undercut profile in S/D etch-out regions, in accordance with various embodiments. Although the operations of the method 600 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple transistors having undercut profiles as described herein. In another example, the operations may be performed in a different order to reflect the structure of a transistor in which an undercut profile as described herein will be included.

[0067] At 602, one or more semiconductor materials for forming a channel material layer may be provided over a substrate. The one or more semiconductor materials provided at 602 may take the form of any of the embodiments of the channel material 104 disclosed herein and the substrate may take form of any of the embodiments of the substrate 102, for example (e.g., any of the

embodiments discussed herein with reference to the transistor 300 and other transistors with undercut profiles described herein). The channel material may be provided at 602 using any suitable deposition and patterning techniques known in the art. [0068] At 604, the channel material provided at 602 is etched to form openings for later depositing materials of future S/D regions. At 604, the channel material is etched so that ledges are left at the upper surface of the channel material, to provide relatively pristine/undamaged crystalline surfaces from which monocrystalline superconductor for the future S/D regions may be grown. The openings provided at 604 may take the form of any of the embodiments of the S/D etch-out regions 302 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the transistor 300 and other transistors with undercut profiles described herein). The openings may be formed at 604 may using any suitable etching techniques known in the art, possibly using suitable masks (e.g. to leave the undamaged ledges such as the ledges 204). In some embodiments, the S/D etch-out openings may be formed at 604 using e.g. isotropic etching to create an undercut profile in the channel material, as described herein. Isotropic etching etches in multiple directions (both vertically and horizontally), unlike e.g. anisotropic dry etching which only etches in a single direction, and, therefore, can be used to achieve undercutting of the channel material, possibly under the polarization layer of the channel material, thereby providing a void or a gap between an upper portion of the channel material and the lower portion of the channel material or the substrate. Any substance suitable for isotropically etching the channel material 104 may be used at 604. In various embodiments, an etchant may be e.g. a chemically active ionized gas (i.e. plasma) using e.g. bromine (Br) and chloride (CI) based chemistries.

[0069] At 606, an epitaxial growth of a doped semiconductor material to form S/D regions of a transistor in the openings created at 604 is performed. In this context, epitaxial growth refers to the deposition of a crystalline overlayer in the form of the desired doped semiconductor material for forming the S/D regions on a crystalline underlayer, i.e. the channel material in the S/D etch-out regions/openings. The epitaxial growth of 606 may be carried out using any known gaseous or liquid precursors for forming the desired material of S/D regions. Because, during the epitaxial growth, the underlayer acts as a seed crystal where it is expected that the ledges 204 will have a relatively pristine monocrystalline structure compared to the channel material within the S/D etch-out openings, it is expected that the epitaxial growth of 606 will result in monocrystalline semiconductor grown from the ledges and wrapping around the upper portion of the undercut portion of the channel material.

[0070] Transistors having an undercut profile in S/D etch-out regions as disclosed herein may be included in any suitable electronic device. FIGS. 7-10 illustrate various examples of apparatuses that may include one or more of the lll-N transistor devices having an undercut profile in S/D etch-out regions, as disclosed herein. [0071] FIGS. 7A-B are top views of a wafer 2000 and dies 2002 that may include one or more lll-N transistor devices having an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein. The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more transistors 300, or any other transistors having undercut profiles as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more transistors 300, or any other transistors having undercut profiles as described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more lll-N transistor devices having an undercut profile in S/D etch-out regions as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include one or more transistors (e.g., one or more of the transistors 2140 of FIG. 8, discussed below, which may take the form of any of the transistors having undercut profiles as described herein) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2302 of FIG. 10) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0072] FIG. 8 is a cross-sectional side view of an IC device 2100 that may include one or more lll-N transistor devices having an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein. The IC device 2100 may be formed on a substrate 2102 (e.g., the wafer 2000 of FIG. 7A) and may be included in a die (e.g., the die 2002 of FIG. 7B). The substrate 2102 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. The substrate 2102 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the semiconductor substrate 2102 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 2102. Although a few examples of materials from which the substrate 2102 may be formed are described here, any material that may serve as a foundation for an IC device 2100 may be used. The substrate 2102 may be part of a singulated die (e.g., the dies 2002 of FIG. 7B) or a wafer (e.g., the wafer 2000 of FIG. 7A).

[0073] The IC device 2100 may include one or more device layers 2104 disposed on the substrate 2102. The device layer 2104 may include features of one or more transistors 2140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2102. The device layer 2104 may include, for example, one or more source and/or drain (S/D) regions 2120, a gate 2122 to control current flow in the transistors 2140 between the S/D regions 2120, and one or more S/D contacts 2124 to route electrical signals to/from the S/D regions 2120. Although not specifically shown in FIG. 8, the S/D regions 2120 may have the undercut profiles as described herein with reference to the S/D etch-out regions 302. The S/D regions 2120 may be formed within the substrate 2102 either adjacent to or at a distance from the gate 2122 of each transistor 2140, using any suitable processes known in the art, some of which are described above. The transistors 2140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 2140 are not limited to the type and configuration depicted in FIG. 8 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or FinFETs, and wrap-around or all- around gate transistors, such as nanoribbon and nanowire transistors. In particular, at least some of the one or more of the transistors 2140 may have an undercut profile in accordance with any of the embodiments disclosed herein. For example, a transistor 2140 may take the form of any of the transistors 300, or other transistors with undercut profiles disclosed herein.

[0074] Each transistor 2140 may include a gate 2122 formed of at least two layers, a gate dielectric layer and a gate electrode layer. Generally, the gate dielectric layer of a transistor 2140 may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistor 2140 may take the form of any of the embodiments of the high-k dielectric 114 disclosed herein, for example.

[0075] In some embodiments, when viewed as a cross section of the transistor 2140 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate (e.g., in a FinFET). In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may include a V-shaped structure (e.g., when the fin of a FinFET does not have a "flat" upper surface, but instead has a rounded peak). The gate electrode of the transistor 2140 may take the form of any of the embodiments of the gate electrode 116 disclosed herein, for example.

[0076] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0077] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 2140 of the device layer 2104 through one or more interconnect layers disposed on the device layer 2104 (illustrated in FIG. 8 as interconnect layers 2106-2110). For example, electrically conductive features of the device layer 2104 (e.g., the gate 2122 and the S/D contacts 2124) may be electrically coupled with the interconnect structures 2128 of the interconnect layers 2106-2110. The one or more interconnect layers 2106-2110 may form an interlayer dielectric (ILD) stack 2119 of the IC device 2100.

[0078] The interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2128 depicted in FIG. 8). Although a particular number of interconnect layers 2106-2210 is depicted in FIG. 8, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0079] In some embodiments, the interconnect structures 2128 may include trench structures 2128a (sometimes referred to as "lines") and/or via structures 2128b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal. The trench structures 2128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2102 upon which the device layer 2104 is formed. For example, the trench structures 2128a may route electrical signals in a direction in and out of the page from the perspective of FIG. 8. The via structures 2128b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2102 upon which the device layer 2104 is formed. In some embodiments, the via structures 2128b may electrically couple trench structures 2128a of different interconnect layers 2106-2110 together.

[0080] The interconnect layers 2106-2110 may include a dielectric material 2126 disposed between the interconnect structures 2128, as shown in FIG. 8. In some embodiments, the dielectric material 2126 disposed between the interconnect structures 2128 in different ones of the interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the dielectric material 2126 between different interconnect layers 2106-2110 may be the same.

[0081] A first interconnect layer 2106 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 2104. In some embodiments, the first interconnect layer 2106 may include trench structures 2128a and/or via structures 2128b, as shown. The trench structures 2128a of the first interconnect layer 2106 may be coupled with contacts (e.g., the S/D contacts 2124) of the device layer 2104.

[0082] A second interconnect layer 2108 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 2106. In some embodiments, the second interconnect layer 2108 may include via structures 2128b to couple the trench structures 2128a of the second interconnect layer 2108 with the trench structures 2128a of the first interconnect layer 2106. Although the trench structures 2128a and the via structures 2128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2108) for the sake of clarity, the trench structures 2128a and the via structures 2128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0083] A third interconnect layer 2110 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2108 according to similar techniques and configurations described in connection with the second interconnect layer 2108 or the first interconnect layer 2106.

[0084] The IC device 2100 may include a solder resist material 2134 (e.g., polyimide or similar material) and one or more bond pads 2136 formed on the interconnect layers 2106-2110. The bond pads 2136 may be electrically coupled with the interconnect structures 2128 and configured to route the electrical signals of the transistor(s) 2140 to other external devices. For example, solder bonds may be formed on the one or more bond pads 2136 to mechanically and/or electrically couple a chip including the IC device 2100 with another component (e.g., a circuit board). The IC device 2100 may have other alternative configurations to route the electrical signals from the interconnect layers 2106-2110 than depicted in other embodiments. For example, the bond pads 2136 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components. [0085] FIG. 9 is a cross-sectional side view of an IC device assembly 2200 that may include components having one or more lll-N transistors incorporating an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein. The IC device assembly 2200 includes a number of components disposed on a circuit board 2202 (which may be, e.g., a motherboard). The IC device assembly 2200 includes components disposed on a first face 2240 of the circuit board 2202 and an opposing second face 2242 of the circuit board 2202; generally, components may be disposed on one or both faces 2240 and 2242. In particular, any suitable ones of the components of the IC device assembly 2200 may include any of the transistors having undercut profiles in accordance with any of the embodiments disclosed herein.

[0086] In some embodiments, the circuit board 2202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2202. In other embodiments, the circuit board 2202 may be a non-PCB substrate.

[0087] The IC device assembly 2200 illustrated in FIG. 9 includes a package-on-interposer structure 2236 coupled to the first face 2240 of the circuit board 2202 by coupling components 2216. The coupling components 2216 may electrically and mechanically couple the package-on-interposer structure 2236 to the circuit board 2202, and may include solder balls (as shown in FIG. 9), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0088] The package-on-interposer structure 2236 may include an IC package 2220 coupled to an interposer 2204 by coupling components 2218. The coupling components 2218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2216. Although a single IC package 2220 is shown in FIG. 9, multiple IC packages may be coupled to the interposer 2204; indeed, additional interposers may be coupled to the interposer 2204. The interposer 2204 may provide an intervening substrate used to bridge the circuit board 2202 and the IC package 2220. The IC package 2220 may be or include, for example, a die (the die 2002 of FIG. 7B), an IC device (e.g., the IC device 2100 of FIG. 8), or any other suitable component. Generally, the interposer 2204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2204 may couple the IC package 2220 (e.g., a die) to a ball grid array (BGA) of the coupling components 2216 for coupling to the circuit board 2202. In the embodiment illustrated in FIG. 9, the IC package 2220 and the circuit board 2202 are attached to opposing sides of the interposer 2204; in other embodiments, the IC package 2220 and the circuit board 2202 may be attached to a same side of the interposer 2204. In some embodiments, three or more components may be interconnected by way of the interposer 2204.

[0089] The interposer 2204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-N and group IV materials. The interposer 2204 may include metal interconnects 2208 and vias 2210, including but not limited to through-silicon vias (TSVs) 2206. The interposer 2204 may further include embedded devices 2214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (M EMS) devices may also be formed on the interposer 2204. The package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.

[0090] The IC device assembly 2200 may include an IC package 2224 coupled to the first face 2240 of the circuit board 2202 by coupling components 2222. The coupling components 2222 may take the form of any of the embodiments discussed above with reference to the coupling components 2216, and the IC package 2224 may take the form of any of the embodiments discussed above with reference to the IC package 2220.

[0091] The IC device assembly 2200 illustrated in FIG. 9 includes a package-on-package structure 2234 coupled to the second face 2242 of the circuit board 2202 by coupling components 2228. The package-on-package structure 2234 may include an IC package 2226 and an IC package 2232 coupled together by coupling components 2230 such that the IC package 2226 is disposed between the circuit board 2202 and the IC package 2232. The coupling components 2228 and 2230 may take the form of any of the embodiments of the coupling components 2216 discussed above, and the IC packages 2226 and 2232 may take the form of any of the embodiments of the IC package 2220 discussed above. The package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.

[0092] FIG. 10 is a block diagram of an example computing device 2300 that may include one or more components including one or more lll-N transistors incorporating an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2300 may include a die (e.g., the die 2002 (FIG. 7B)) having one or more lll-N transistors incorporating an undercut profile in S/D etch-out regions in accordance with any of the embodiments disclosed herein. Any one or more of the components of the computing device 2300 may include, or be included in, an IC device 2100 (FIG. 8). Any one or more of the components of the computing device 2300 may include, or be included in, an IC device assembly 2200 (FIG. 9).

[0093] A number of components are illustrated in FIG. 10 as included in the computing device 2300, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2300 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0094] Additionally, in various embodiments, the computing device 2300 may not include one or more of the components illustrated in FIG. 10, but the computing device 2300 may include interface circuitry for coupling to the one or more components. For example, the computing device 2300 may not include a display device 2306, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2306 may be coupled. In another set of examples, the computing device 2300 may not include an audio input device 2318 or an audio output device 2308, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2318 or audio output device 2308 may be coupled.

[0095] The computing device 2300 may include a processing device 2302 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2300 may include a memory 2304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2304 may include memory that shares a die with the processing device 2302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-M RAM).

[0096] In some embodiments, the computing device 2300 may include a communication chip 2312 (e.g., one or more communication chips). For example, the communication chip 2312 may be configured for managing wireless communications for the transfer of data to and from the computing device 2300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0097] The communication chip 2312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2312 may operate in accordance with other wireless protocols in other embodiments. The computing device 2300 may include an antenna 2322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0098] In some embodiments, the communication chip 2312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2312 may include multiple communication chips. For instance, a first communication chip 2312 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2312 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2312 may be dedicated to wireless communications, and a second communication chip 2312 may be dedicated to wired communications.

[0099] The computing device 2300 may include battery/power circuitry 2314. The battery/power circuitry 2314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2300 to an energy source separate from the computing device 2300 (e.g., AC line power).

[0100] The computing device 2300 may include a display device 2306 (or corresponding interface circuitry, as discussed above). The display device 2306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0101] The computing device 2300 may include an audio output device 2308 (or corresponding interface circuitry, as discussed above). The audio output device 2308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0102] The computing device 2300 may include an audio input device 2318 (or corresponding interface circuitry, as discussed above). The audio input device 2318 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output).

[0103] The computing device 2300 may include a global positioning system (GPS) device 2316 (or corresponding interface circuitry, as discussed above). The GPS device 2316 may be in

communication with a satellite-based system and may receive a location of the computing device 2300, as known in the art.

[0104] The computing device 2300 may include an other output device 2310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0105] The computing device 2300 may include an other input device 2320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFI D) reader.

[0106] The computing device 2300 may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2300 may be any other electronic device that processes data.

[0107] The following paragraphs provide various examples of the embodiments disclosed herein.

[0108] Example 1 provides a transistor structure, the transistor structure including a source region, a drain region, and a channel material between the source region and the drain region. The channel material includes a lll-N semiconductor material and has an undercut below an uppermost surface of the channel material in a lateral portion of the channel material that interfaces (i.e. is in contact with, at least at some points) the source region or the drain region (i.e. the channel material between the source region and the drain region has an undercut profile on at least one lateral side/face of the channel material). As used herein, a lateral (i.e. side) portion of the channel material interfacing the source region or the drain region implies that a portion of the channel material is in contact with at least some points/areas of the material(s) of the source region or the drain region (i.e. the interface may be not continuous). Such "interfacing" does not imply that that a portion of the channel material is in contact with the material (s) of the source region or the drain region at all points where these materials are supposed to meet (i.e. does not imply that the interface is continuous). For example, in some implementations, various imperfections such as gaps and discontinuous coverage by the material (s) of the source/drain regions may prevent formation of a continuous interface. In another example, various intentional or unintentional materials or layers may be formed on/at at least some portions of the intended interface, also preventing formation of a continuous interface between the channel material and the material(s) of the source/drain regions. All of such interfaces are within the scope of the present disclosure.

[0109] In all Examples described herein, each of the source and drain regions of a transistor are regions of doped semiconductor materials, while the channel material may include one or more semiconductor materials with doping concentrations significantly smaller than those of the source and drain regions. For example, in some embodiments, the channel material may be an intrinsic (i.e. undoped) lll-N semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material are still significantly lower than in the source and drain regions, for example below 10 ¹⁵ dopant elements per cubic centimeter (cm ³ ), and advantageously below 10 ¹³ cm ³ . Also in all Examples described herein, the gate electrode material, as well as each of the source electrode material and the drain electrode material, may include one or more of conductor materials, e.g. one or more metals.

[0110] Example 2 provides the transistor structure according to Example 1, where the channel material between the source region and the drain region having the undercut (or having the undercut profile) means that a dimension, between the source region and the drain region, of an upper portion of the channel material is larger than a dimension, between the source region and the drain region, of a lower portion of the channel material.

[0111] Example 3 provides the transistor structure according to Example 2, where the dimension of the upper portion of the channel material is between about 5 and 300 nanometers larger than the dimension of the lower portion of the channel material, e.g. between about 5 and 50 nm, between about 30 and 250 nm, or between about 25 and 300 nm.

[0112] Example 4 provides the transistor structure according to any one of the preceding Examples, where the undercut is in the portion of the channel material that interfaces the source region.

[0113] Example 5 provides the transistor structure according to Example 4, where a portion of a semiconductor material of the source region is under an upper portion of the channel material.

[0114] Example 6 provides the transistor structure according to Examples 4 or 5, where the portion of the channel material that interfaces the source region includes at least one recess.

[0115] Example 7 provides the transistor structure according to any one of the preceding Examples, where the undercut is in the portion of the channel material that interfaces the drain region.

[0116] Example 8 provides the transistor structure according to Example 7, where a portion of a semiconductor material of the drain region is under an upper portion of the channel material.

[0117] Example 9 provides the transistor structure according to Examples 7 or 8, where the portion of the channel material that interfaces the drain region includes at least one recess.

[0118] Example 10 provides the transistor structure according to any one of the preceding

Examples, further including a gate stack provided over an upper portion (i.e. a portion of the uppermost surface) of the channel material.

[0119] Example 11 provides the transistor structure according to Example 10, where the gate stack includes a gate dielectric material provided over the upper portion of the channel material and a gate electrode material provided over the gate dielectric material.

[0120] Example 12 provides the transistor structure according to Examples 10 or 11, where the channel material includes a ledge (i.e. a horizontal surface), or a protrusion, projecting from the upper portion of the channel material over which the gate stack is provided towards the source region. [0121] Example 13 provides the transistor structure according to any one of Examples 10-12, where the channel material includes a ledge, or a protrusion, projecting from the upper portion of the channel material over which the gate stack is provided towards the drain region.

[0122] In some Examples, the channel material may be shaped as a fin, and the gate stack may wrap around a portion of the fin. In other Examples, the channel material may be shaped as a wire, and the gate stack may wrap around a portion of the wire, e.g. the gate stack may wrap entirely around the wire.

[0123] Example 14 provides the transistor structure according to any one of the preceding

Examples, where the drain region is a region of a semiconductor material having a dopant concentration higher than a dopant concentration of a semiconductor material between the drain region and the source region.

[0124] Example 15 provides the transistor structure according to any one of the preceding

Examples, where the drain region has a dopant concentration of at least 5-10 ¹⁶ dopant elements per cubic centimeter.

[0125] Example 16 provides the transistor structure according to any one of the preceding

Examples, where the source region and/or the drain region includes a doped semiconductor material including indium, gallium, and nitride (e.g. doped InGaN).

[0126] Example 17 provides the transistor structure according to any one of the preceding

Examples, where the channel material includes a stack of materials, the stack including a polarization layer (e.g. a layer of AIN, InAIN, or AIGaN) over the lll-N semiconductor material (i.e. the polarization layer is the uppermost layer of the channel material).

[0127] Example 18 provides the transistor structure according to any one of the preceding

Examples, where at least 33% of the source region or the drain region includes a substantially monocrystalline, or highly crystalline, semiconductor material.

[0128] Example 19 provides the transistor structure according to any one of the preceding

Examples, further including a drain electrode electrically connected to the drain region and a source electrode electrically connected to the source region.

[0129] Further Examples provides a computing device which includes a substrate and an IC die coupled to the substrate, where the IC die includes a transistor structure according to any one of Examples 1-19.

[0130] Example 20 provides a method of fabricating a transistor structure. The method includes providing a channel material over a substrate, the channel material including a group lll-N semiconductor material; etching the channel material to form an opening in the channel material such that a portion of the channel material is suspended over the opening (i.e. so that the channel material has an undercut profile on the side of the opening); and depositing a doped semiconductor material in the opening.

[0131] Example 21 provides the method according to Example 20, where providing the channel material includes epitaxially growing the channel material over the substrate.

[0132] Example 22 provides the method according to Examples 20 or 21, where etching the channel material includes performing an isotropic etch of the channel material.

[0133] Example 23 provides the method according to any one of Examples 20-22, where depositing the doped semiconductor material in the opening includes performing an epitaxial growth of the doped semiconductor material.

[0134] Example 24 provides the method according to any one of Examples 20-23, where the doped semiconductor material includes a doped material including indium, gallium, and nitride (e.g. doped InGaN).

[0135] Example 25 provides the method according to any one of Examples 20-24, where the opening with the doped semiconductor material forms a source region or a drain region of the transistor structure.

[0136] Example 26 provides the method according to any one of Examples 20-25, further including providing a source/drain electrode to be in contact with the doped semiconductor material in the opening. Thus, the method includes providing a source/drain electrode material to be in electrical contact with a source/drain region. In further embodiments, the method may further include providing a gate stack that includes a gate dielectric and a gate electrode. In various Examples, providing transistor structure electrodes (i.e. gate, source, and drain electrode materials) includes depositing titanium, aluminum, titanium nitride, erbium, gadolinium, or ytterbium, using any suitable deposition and patterning techniques.

[0137] Example 27 provides a computing device which includes a substrate and an IC die coupled to the substrate, where the IC die includes a transistor structure having a source region, a drain region, and a channel material between the source region and the drain region, the channel material including a group l ll-N semiconductor material and having an undercut profile on at least one side of the channel material.

[0138] Example 28 provides the computing device according to Example 27, where the undercut profile means that a dimension, between the source region and the drain region, of an upper portion of the channel material is larger than a dimension, between the source region and the drain region, of a lower portion of the channel material.

[0139] Example 29 provides the computing device according to Example 28, where a difference between the dimension of the upper portion of the channel material is between about 5 and 300 nanometers larger than the dimension of the lower portion of the channel material, e.g. between about 5 and 50 nm, between about 30 and 250 nm, or between about 25 and 300 nm.

[0140] Example 30 provides the computing device according to any one of Examples 27-29, where the undercut profile on at least one side of the channel material includes an undercut on a side of the channel material closest to the source region.

[0141] Example 31 provides the computing device according to Example 30, where a portion of a semiconductor material of the source region is under a portion of the channel material.

[0142] Example 32 provides the computing device according to Examples 30 or 31, where the side of the channel material closest to the source region includes at least one recess.

[0143] Example 33 provides the computing device according to any one of Examples 27-32, where the undercut profile on at least one side of the channel material includes an undercut on a side of the channel material closest to the drain region.

[0144] Example 34 provides the computing device according to Example 33, where a portion of a semiconductor material of the drain region is under a portion of the channel material.

[0145] Example 35 provides the computing device according to Examples 33 or 34, where the side of the channel material closest to the drain region includes at least one recess.

[0146] Example 36 provides the computing device according to any one of Examples 27-35, further including a gate stack provided over a portion of the channel material.

[0147] Example 37 provides the computing device according to Example 36, where the gate stack includes a gate dielectric material provided over the portion of the channel material and a gate electrode material provided over the gate dielectric material.

[0148] Example 38 provides the computing device according to Examples 36 or 37, where the channel material includes a ledge (i.e. a horizontal surface), or a protrusion, projecting from the portion of the channel material over which the gate stack is provided towards the source region.

[0149] Example 39 provides the computing device according to any one of Examples 36-38, where the channel material includes a ledge, or a protrusion, projecting from the portion of the channel material over which the gate stack is provided towards the drain region.

[0150] Example 40 provides the computing device according to any one of Examples 27-39, where the drain region is a region of a semiconductor material having a dopant concentration higher than a dopant concentration of a semiconductor material between the drain region and the source region.

[0151] Example 41 provides the computing device according to any one of Examples 27-40, where the drain region has a dopant concentration of at least 5- 10 ¹⁶ dopant elements per cubic centimeter. [0152] Example 42 provides the computing device according to any one of Examples 27-41, where the source region and/or the drain region includes a doped semiconductor material including indium, gallium, and nitride (e.g. doped InGaN).

[0153] Example 43 provides the computing device according to any one of Examples 27-42, where the channel material includes a stack of materials, the stack including a polarization layer over the ll l-N semiconductor material (i.e. the polarization layer is the upper-most layer of the channel material), the polarization layer comprising one or more of a material comprising aluminum and nitrogen (e.g. AI N), a material comprising indium, aluminum and nitrogen (e.. InAIN), or a material comprising aluminum, gallium and nitrogen (AIGaN).

[0154] Example 44 provides the computing device according to any one of Examples 27-43, where at least 33% of the source region or the drain region includes a highly crystalline semiconductor material.

[0155] Example 45 provides the computing device according to any one of Examples 27-44, further including a drain electrode electrically connected to the drain region and a source electrode electrically connected to the source region.

[0156] Example 46 provides the computing device according to any one of Examples 27-45, where the computing device is a wearable or handheld computing device.

[0157] Example 47 provides the computing device according to any one of Examples 27-46, where the computing device further includes one or more communication chips and an antenna.

[0158] Example 48 provides the computing device according to any one of Examples 27-47, where the substrate is a motherboard.

[0159] Further Examples provide the transistor structure as the one described to be within the computing device according to any of Examples 27-48, but as a stand-alone structure (i.e. not included within a computing device).

[0160] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0161] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.