Title:
PROGRAM, INFORMATION CONVERSION DEVICE, AND INFORMATION CONVERSION METHOD
Document Type and Number:
WIPO Patent Application WO/2020/235616
Kind Code:
A1
Abstract:
[Problem] To provide a compiler, a compiling device, and a compiling method for generating an object code that realizes a high processing performance and a small size with respect to a processor capable of executing out of order without performing register renaming. [Solution] One aspect of the present invention provides a program that causes a computer to serve as an information conversion device, the information conversion device being equipped with at least one of constituent elements (A)-(E): (A) a replication necessity analysis processing unit that specifies a location where an instruction referred to from a plurality of phi functions present in one basic block is present and that inserts an inter-register transfer instruction in the instruction location; (B) an intra-loop constant analysis processing unit that specifies a closed path in which the references of the phi functions are circulated and that inserts the inter-register transfer instruction in the closed path; (C) an inter-instruction dependency analysis processing unit that specifies a location where data dependency is present between instructions, which are reference destinations of the plurality of phi functions, and that inserts the inter-register transfer instruction in the location; (D) an identical instruction reference analysis processing unit that specifies, in a plurality of execution paths, a location where the phi functions referring to a result of the identical instruction before branching are present and that inserts the inter-register transfer instruction in the execution path; and (E) a spill-out effectiveness analysis processing unit that stores a parameter value present in loop processing and targeted by the inter-register transfer instruction in a storage element other than a general-purpose register before start of the loop processing, loads the value after end of the loop processing, and deletes the inter-register transfer instruction.
Inventors:
IRIE HIDETSUGU (JP)
SAKAI SHUICHI (JP)
KOIZUMI TORU (JP)
NAKAE SATOSHI (JP)
FUKUDA AKIFUMI (JP)
SAKAI SHUICHI (JP)
KOIZUMI TORU (JP)
NAKAE SATOSHI (JP)
FUKUDA AKIFUMI (JP)
Application Number:
PCT/JP2020/020033
Publication Date:
November 26, 2020
Filing Date:
May 21, 2020
Export Citation:
Assignee:
UNIV TOKYO (JP)
International Classes:
G06F8/41
Foreign References:
| JP2000284968A | 2000-10-13 |
Other References:
MATSUZAKI, HIDENORI ET AL..: "A Register Allocation Method for an Out of-order System without Register Renaming Mechanism", 2000 COMMEMORATIVE MEETING OF JOINT SYMPOSIUM ON PARALLEL PROCESSING, vol. 2000, no. 6, 30 May 2000 (2000-05-30)
SAKAI, KAZUNORI ET AL.,: "Review of the implementation of speculative memory forwarding in STRAIGHT", IPSJ SIG TECHNICAL REPORTS [ONLINE], vol. 34, 16 January 2017 (2017-01-16), pages 1 - 6
SAKAI, KAZUNORI ET AL.,: "Review of the implementation of speculative memory forwarding in STRAIGHT", IPSJ SIG TECHNICAL REPORTS [ONLINE], vol. 34, 16 January 2017 (2017-01-16), pages 1 - 6
Attorney, Agent or Firm:
IPX PATENT PARTNERS (JP)
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