CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63/314,725 entitled “Programmable Precision Etching,” filed on February 28, 2022, which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

[0002] The present invention relates generally to wafer thinning, and more particularly to programmable precision etching to improve the precision of wafer thinning.

BACKGROUND

[0003] Wafer thinning is the process of removing material from the backside of a wafer to a desired final target thickness. The two most common methods of wafer thinning are conventional grind and chemical-mechanical planarization (CMP).

[0004] Conventional grinding is an aggressive mechanical process that utilizes a diamond and a resin bonded grind wheel mounted onto a high speed spindle to perform the material removal. The grind recipe dictates the spindle revolutions per minute (RPM), rate of material removal, and the final target thickness of the work piece. Harder materials, such as sapphire, typically require slower feed rates compared to more forgiving materials, such as silicon.

[0005] The wafer is positioned on a porous ceramic rotating vacuum chuck with the backside of the wafer facing upwards (towards the grind wheel). Both the grind wheel and wafer chuck rotate during grind. Deionized water is jetted onto the work piece to provide cooling and wash away material particles generated during the grind. A grinding tape is applied to the front side of the wafer to protect the devices from being damaged during thinning.

[0006] For conventional grinding, the thinning is a two-step process. The first step is a coarse grind that performs the bulk of the material removal. The second step is a fine grind.

[0007] Polishing is the final step in producing a deformation-free surface that is flat, scratch free and mirror-like in appearance. Mechanical polishing requires a separate process and equipment from conventional grinding. Mechanical polishing is a minimal removal process of only 2-3 pm of material and is typically only performed on silicon. [0008] Tn CMP, abrasive chemical slurry is used with a polishing pad to perform material removal. CMP provides greater planarization compared to mechanical grinding, however, it is considered a “dirtier” and more costly process. The wafers are mounted to a backing film, such as a wax mount, which can be difficult to remove or leave a residue on the front side of the wafer.

[0009] CMP does have the advantage of being more forgiving when it comes to processing hard or exotic materials, such as tungsten.

[0010] Unfortunately, such processes still need improvement in the precision for wafer thinning.

SUMMARY

[0011] In one embodiment of the present disclosure, a method for thinning a group of two or more dies comprises introducing an etch gas chemistry into a plasma generator. The method further comprises generating a plasma using the etch gas chemistry by the plasma generator. The method additionally comprises etching the two or more dies placed within an etch chamber to thin the two or more dies until the two or more dies achieve a desired thickness using the plasma. Furthermore, the method comprises implementing a spatially variable closed loop control of etch rates of the etching to provide spatially variable etch rates during the thinning of the two or more dies.

[0012] In another embodiment of the present disclosure, a system for thinning a group of two or more dies uses the method described above.

[0013] The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present disclosure in order that the detailed description of the present disclosure that follows may be better understood. Additional features and advantages of the present disclosure will be described hereinafter which may form the subject of the claims of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A better understanding of the present disclosure can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:

[0015] Figure 1 illustrates an architecture for precision substrate thinning (PST) equipment in accordance with an embodiment of the present disclosure;

[0016] Figure 2 is a flowchart of a method for performing substrate thinning using a dry etching process in accordance with an embodiment of the present disclosure;

[0017] Figure 3 is a flowchart of a method for performing substrate planarization using nP3 in accordance with an embodiment of the present disclosure;

[0018] Figure 4 is a flowchart of a method for performing substrate planarization using spatial etch rate control in accordance with an embodiment of the present disclosure;

[0019] Figure 5 is a flowchart of a method for minimizing total thickness variation (TTV) using nP3 in accordance with an embodiment of the present disclosure;

[0020] Figure 6 is a flowchart of a method for minimizing TTV using spatial etch rate control in accordance with an embodiment of the present disclosure;

[0021] Figure 7 illustrates an alternative architecture for PST equipment in comparison to the architecture presented in Figure 1 in accordance with an embodiment of the present disclosure;

[0022] Figure 8 illustrates an additional alternative architecture for PST equipment in accordance with an embodiment of the present disclosure;

[0023] Figure 9 is a flowchart of a method for performing precision substrate thinning using spatial etch rate control in accordance with an embodiment of the present disclosure;

[0024] Figure 10 depicts the variation in etch rates as a function of temperature for silicon in accordance with an embodiment of the present disclosure;

[0025] Figure 11 illustrates an embodiment of the present disclosure of the thermal actuation subsystem; [0026] Figures 12A-12E illustrate the thermal simulation results for quantifying temperature across a die for a given heat input in accordance with an embodiment of the present disclosure;

[0027] Figure 13 is a methodology for the pulse width modulation (PWM) control of the illumination sources used in one instance of the thermal actuation sub-system in accordance with an embodiment of the present disclosure;

[0028] Figures 14A-14B illustrate simulation and experimental results of the optical lens stack to focus diverging light from a laser diode in accordance with an embodiment of the present disclosure;

[0029] Figures 15A-15C illustrate substrate scale metrology using single point sensors in accordance with an embodiment of the present disclosure;

[0030] Figure 16 illustrates the inter-die features to address edge non-uniformities in accordance with an embodiment of the present disclosure;

[0031] Figure 17 is a flowchart of a method for generating inter-die features in accordance with an embodiment of the present disclosure;

[0032] Figures 18A-18F depict the cross-sectional views for generating inter-die features using the steps described in Figure 17 in accordance with an embodiment of the present disclosure;

[0033] Figures 19A-19B illustrate an exemplary process for profile correcting using nP3 in accordance with an embodiment of the present disclosure;

[0034] Figures 20A-20C illustrate a process for profile correction using an intermediate film in accordance with an embodiment of the present disclosure;

[0035] Figure 21 is a flowchart of a method for PST using nP3 in accordance with an embodiment of the present disclosure;

[0036] Figure 22 illustrates a substrate having dies of different thickness in accordance with an embodiment of the present disclosure;

[0037] Figure 23 illustrates an exemplary method for three-dimensional (3D) integration, one of the use cases for PST, in accordance with an embodiment of the present disclosure; [0038] Figure 24 is a flowchart of an alternative method for generating inter-die features in accordance with an embodiment of the present disclosure; and

[0039] Figures 25A-25C depict the cross-sectional views for generating inter-die features using the steps described in Figure 24 in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0040] As stated in the Background section, wafer thinning is the process of removing material from the backside of a wafer to a desired final target thickness. The two most common methods of wafer thinning are conventional grind and chemical-mechanical planarization (CMP).

[0041] Conventional grinding is an aggressive mechanical process that utilizes a diamond and a resin bonded grind wheel mounted onto a high speed spindle to perform the material removal. The grind recipe dictates the spindle revolutions per minute (RPM), rate of material removal, and the final target thickness of the work piece. Harder materials, such as sapphire, typically require slower feed rates compared to more forgiving materials, such as silicon.

[0042] The wafer is positioned on a porous ceramic rotating vacuum chuck with the backside of the wafer facing upwards (towards the grind wheel). Both the grind wheel and wafer chuck rotate during grind. Deionized water is jetted onto the work piece to provide cooling and wash away material particles generated during the grind. A grinding tape is applied to the front side of the wafer to protect the devices from being damaged during thinning.

[0043] For conventional grinding, the thinning is a two-step process. The first step is a coarse grind that performs the bulk of the material removal. The second step is a fine grind.

[0044] Polishing is the final step in producing a deformation-free surface that is flat, scratch free and mirror-like in appearance. Mechanical polishing requires a separate process and equipment from conventional grinding. Mechanical polishing is a minimal removal process of only 2-3 pm of material and is typically only performed on silicon.

[0045] In CMP, abrasive chemical slurry is used with a polishing pad to perform material removal. CMP provides greater planarization compared to mechanical grinding, however, it is considered a “dirtier” and more costly process. The wafers are mounted to a backing film, such as a wax mount, which can be difficult to remove or leave a residue on the front side of the wafer.

[0046] CMP does have the advantage of being more forgiving when it comes to processing hard or exotic materials, such as tungsten.

[0047] Unfortunately, such processes still need improvement in the precision for wafer thinning. [0048] The embodiments of the present disclosure provide a means for improving the precision for substrate thinning. Embodiments of a process for precision substrate thinning and its equipment are discussed below.

[0049] In one embodiment, the equipment can be used for one or more of the following processes: (i) thinning (or mean thickness reduction); (ii) planarizing a surface; and (iii) total thickness variation (TTV) minimization. TTV, as used herein, refers to the difference between the maximum and minimum value of thickness encountered during measurement of one or more contiguous or non-contiguous substrates. Precision substrate thinning (PST) is a combination of the above processes. In one embodiment, PST is used to thin substrates to below one of the following: 50 pm, 10 pm, 5 pm and 1 pm. In one embodiment PST is used to minimize TTV to below one of the following: 200 nm, 100 nm, 50 nm, 25 nm and 10 nm.

[0050] In one embodiment, the equipment consists of a process chamber in which the etching gases are introduced and turned into plasma to etch the substrate. A metrology system is described below that measures the thickness and thickness variation across the substrate. A process for correcting TTV and flatness errors is also described below. In one embodiment, such correction is accomplished via the use of a sub-system which generates desired spatially variable etch rates. The spatially variable etch rates along with the metrology sub-system enable the implementation of a closed-loop control scheme to accurately achieve the low thickness and thickness variation desired for precision substrate thinning (PST). In one embodiment, the spatially variable etch rates are determined using an algorithm executed in one or more of the following locations: a local computer, a remote computer and a cloud-based computer.

[0051] In another embodiment for the correction process, the TTV across the substrate is corrected using the nP3 process. A discussion regarding the nP3 process is provided in International Application No. PCT/US2021/019732, which is incorporated by reference herein in its entirety. In one embodiment, the TTV across the substrate is measured and recorded using the metrology sub-system. nP3 is then used to coat the substrate with a nanometer-precise film of polymer onto the non-uniform substrate. The planarized profile is then etched back into the original substrate. A discussion regarding such equipment is provided below in connection with Figure 1. [0052] Referring to Figure 1, Figure 1 illustrates an architecture for PST equipment in accordance with an embodiment of the present disclosure.

[0053] As shown in Figure 1, a substrate 101 to be etched is placed inside a vacuum chamber 102 (also called an etch chamber) on a substrate clamp 103. In one embodiment, vacuum pressure is controlled by implementing a closed-loop control scheme between a pressure sensor 104 and a vacuum pump 105. The output of vacuum pump 105 is exhaust 106.

[0054] In one embodiment, plasma is generated through a remote plasma source, however, other sources as discussed further below can be used. In one embodiment, mass flow controllers (MFC) 107A-107C (identified as “MFC-1,” “MFC-2,” and “MFC-3,” respectively) are used to control the amount of etchant gases 108A-108C (identified as “Etch Gas-1,” “Etch Gas-2,” and “Etch Gas-3,” respectively) injected into the plasma generator 109, which creates the plasma. MFC 107A-107C may collectively or individually be referred to as MFCs 107 or MFC 107, respectively. Etchant gases 108A-108C may collectively or individually be referred to as etchant gases 108 or etchant gas 108, respectively. While Figure 1 illustrates three MFCs 107 and three etchant gases 108, s any number of MFCs 107 and etchant gases 108 may be utilized.

[0055] In one embodiment, a sub-assembly 110 for uniform substrate heating can be present below substrate clamp 103. In one embodiment, substrate clamp 103 is connected to an RF power source 111 to generate a DC bias on substrate 101 to induce a physical etch if needed.

[0056] In one embodiment, an optical metrology system can be present above etch chamber 102. In this instance, a single point metrology sensor 112 (e.g., linked color imaging (LCI) sensor) is used to measure the substrate thickness. In one embodiment, a thermal actuation sub-system 113 as described further below is present on top as shown in Figure 1. The optical metrology subsystem consisting of metrology sensor 112 and thermal actuation sub-system 113 illuminate substrate 101 through a viewport 114. In one embodiment, viewport 114 is made of a material transmissive to light from both sub-systems.

[0057] In an alternate embodiment, these sub-systems are present inside etch chamber 102 itself. In one embodiment, the instrument has a thermal camera 115 to monitor the temperature across substrate 101. In one embodiment, a closed-loop control scheme is implemented in which metrology sensor 112 and thermal camera 115 (e.g., IR camera) are used as feedback to control thermal actuation sub-system 113 to induce a spatially variable temperature and hence spatially variable etch rates for reducing thickness variation.

[0058] In one embodiment, the PST equipment consists of the following sub-systems: etch chamber 102, plasma generator 109, a DC bias cathode, a thermal actuation sub-system 113, an array of nozzles for implementing spatially varying etch rates, metrology sensor 112, a substrate scale metrology system using large apertures and a substrate scale metrology system using a single spot measuring sensor.

[0059] In one embodiment, etch chamber 102 is the process chamber in which etching takes place. In one embodiment, etching gases 108 are introduced in etch chamber 102, where the flow rates of etching gases 108 are controlled through mass flow controllers 107. In one embodiment, etching gases 108 include, but are not limited to, CF4, CHF3, SFe, NF3, Ar, O2, Ch, N2, and H2.

[0060] In one embodiment, etch chamber 102 is connected to vacuum pump 105 through a needle valve to control the vacuum pressure. In one embodiment, etch chamber 102 has viewports 114 transmissive to lights from the metrology sub-system and the thermal actuation sub-system, such as thermal actuation sub-system 113.

[0061] In one embodiment, plasma generator 109 is configured to generate plasma using various techniques, such as conductively coupled plasma (CCP), inductively coupled plasma (ICP), electron cyclotron resonance (ECR) and remote plasma source (RPS).

[0062] In one embodiment, the PST equipment includes a DC bias cathode along with the above plasma sources to induce a physical etch onto substrate 101. In one embodiment, the ratios of power of the DC-bias cathode and plasma generator 109 are adjusted to control the amount of physical versus chemical etching.

[0063] In one embodiment, the PST equipment includes a thermal actuation sub-system 113. In one embodiment, such a sub-system 113 includes various sub-systems to create a desired temperature profile on substrate 101, such as a sub-system for uniform thermal actuation, a subsystem for spatially variable thermal actuation and a sub-system for spatially variable thermal actuation using a digital micromirror device (DMD). [0064] In one embodiment, the PST equipment includes a sub-system 113 for uniform thermal actuation. In one embodiment, such a sub-system has thermal actuators for uniform heating of substrate 101 to increase the etch rates. In one embedment, such a sub-system includes resistive heating elements inside etch chamber 102 and below substrate 101, preferably mounted below the plate on which substrate 101 rests (see element 103). In another embodiment, radiative heating lamps are present inside etch chamber 102, such as quartz halogen lamps

[0065] As also discussed above, in one embodiment, thermal actuation sub-system 113 includes the sub-system for spatially variable thermal actuation. In one embodiment, such a sub-system includes high powered laser diodes (LDs) or light emitting diodes (LEDs) as sources of illumination assembled on a printed circuit board (PCB) in a two-dimensional matrix. In one embodiment, such a sub-system includes suitable heat sinks to remove heat from the PCB and LDs/LEDs. In one embodiment, such a sub-system includes a stack of optical components, including, but not limited to, aspheric lenses, cylindrical lenses, reflectors and apertures to focus the divergent light from each of the illumination sources onto substrate 101.

[0066] Furthermore, as discussed above, in one embodiment, thermal actuation sub-system 113 includes spatially variable thermal actuation using a DMD (referred to herein as the “DMD subsystem”). In one embodiment, the DMD sub-system includes a high-power laser diode used as a source of irradiation. Furthermore, in one embodiment, the DMD sub-system directs the high power laser onto substrate 101 to generate spatial temperature profdes. In one embodiment, the DMD sub-system includes aspheric lenses, cylindrical lenses and heat sinks for mounting and collimating laser diodes. In one embodiment, the DMD sub-system includes one or more of the above sub-systems mounted on a stationary platform or on a moveable XY stage which can be used to illuminate the entire substrate 101.

[0067] In one embodiment, the PST equipment includes a nozzle array for spatially varying the etch rates. In one embodiment, such a sub-system consists of an array of nozzles to inject etching gases 108 inside process chamber 102. The mass flow rates through each of the nozzles can be varied to obtain spatially variable etch rates.

[0068] In one embodiment, the PST equipment includes metrology sensor 112. In one embodiment, metrology sensor 112 in the equipment provides information about the thickness and the thickness variation across substrate 101. In one embodiment, the substrate thickness information is provided using sensing techniques, such as laser interferometry, low coherence interferometry, ellipsometry, phase-shifting interferometry, moire interferometry and spectral interface wafer thickness measurement.

[0069] In one embodiment, the PST equipment includes substrate scale metrology using large apertures. In one embodiment, such a substrate scale metrology is configured to measure across the entire substrate 101 using large apertures such that the entire substrate 101 is illuminated and measured. In one embodiment, a technique utilized for performing such illumination and measurement includes linked color imaging (LCI) with hyper-spectral imaging, which utilizes (1) a low-coherence illumination source, such as a superluminescent diode (SLD) to illuminate the entire substrate 101; (2) a reference surface on which light can undergo reflection for interferometry; (3) a hyperspectral camera, which is similar to having a two-dimensional array of single-point spectrometers, where each pixel or each single-point spectrometer corresponds to a specific location on the wafer; and (4) a software algorithm to analyze the resultant spectrogram and evaluate the thickness and/or thickness variation.

[0070] In one embodiment, metrology sensor 112 in the equipment provides information about the substrate top profile. In one embodiment, the top profile is measured using sensing techniques, such as laser interferometry, optical emission interferometry and Fizeau interferometry.

[0071] In one embodiment, the PST equipment includes a substrate scale metrology system using a single spot measuring sensor. In one embodiment, where the sensing area is smaller than substrate 101, sampling of the entire substrate 101 is implemented using sensors mounted on an XY stage. In one embodiment, such sensors are mounted on an XY stage to scan the entire substrate 101. In one embodiment, instead of a single sensor, an array of sensors are used in different orientations for high throughput. In one embodiment, sampling of the entire substrate 101 is implemented using a variable pitch mechanism (VPM). In one embodiment, one or more sensors discussed above in connection with metrology sensor 112 are mounted on a VPM to scan the entire substrate 101.

[0072] A summary of the process implementation is described below. [0073] In one embodiment, substrate thinning is performed using a dry etching process described below in connection with Figure 2. Figure 2 is a flowchart of a method 200 for performing substrate thinning using a dry etching process in accordance with an embodiment of the present disclosure.

[0074] Referring to Figure 2, in conjunction with Figure 1, in step 201, substrate 101 is placed inside etch chamber 102.

[0075] In step 202, a suitable etch gas chemistry is introduced inside etch chamber 102.

[0076] In step 203, plasma is generated to be used in etching using one of the following techniques discussed above, such as CCP, ICP, ECR or RPS.

[0077] In step 204, the etch rates are increased by heating substrate 101 using techniques discussed above, such as uniform thermal actuation, spatially variable thermal actuation and spatially variable thermal actuation using the DMD sub-system.

[0078] In one embodiment, for difficult to etch materials or materials with high bond strength, including, but not limited to, silicon dioxide, diamond, and gallium nitride, the etch rates can also be increased by inducing a physical sputter component using a DC bias cathode described above.

[0079] In step 105, etching is stopped when substrate 101 achieves the desired thickness. In one embodiment, the metrology system using metrology sensor 112 and/or the substrate scale metrology system using large apertures and/or the substrate scale metrology system using a single spot measuring sensor discussed above provide information about substrate thickness, including the mean thickness. In one embodiment, the process discussed above is stopped when substrate 101 achieves the desired thickness. In one embodiment, the thickness information is obtained in real time (for example >10 Hz). In another embodiment, the obtained metrology is performed intermittently. For example, when the etch process is stopped, metrology is subsequently performed following when the etch process is restarted. Such a cycle continues until the desired thickness is achieved.

[0080] A method for substrate planarization using nP3 is discussed below in connection with Figure 3. [0081] Figure 3 is a flowchart of a method 300 for performing substrate planarization using nP3 in accordance with an embodiment of the present disclosure.

[0082] Referring to Figure 3, in conjunction with Figure 1, in step 301, flatness information across substrate 101 is obtained using metrology sensor 112 and/or the substrate scale metrology system using large apertures and/or the substrate scale metrology system using a single spot measuring sensor discussed above.

[0083] In step 302, a nanometer precise film thickness of polymer is ink-jetted onto the non- uniform substrate 101 to result in a substantially planar top surface using the nP3 process.

[0084] In step 303, the cured resist is etched back into substrate 101 using a dry etching process, such as method 200. In one embodiment, an intermediate or a series of intermediate films are present between the polymer and substrate 101. For example, an intermediate film may correspond to silicon dioxide on a diamond substrate. In such an embodiment, the polymer profile is first transferred into silicon dioxide using a fluorine chemistry at temperatures low enough to ensure polymer stability, for example 150° C. The profile can now be etched into diamond using an oxygen dominant chemistry with high etch rates by either heating substrate 101 or through a DC- bias or both.

[0085] In one embodiment, the etch back is performed using an open loop control or using spatial etch rate control as discussed above in connection with thermal actuation sub-system 113 and the nozzle array for spatially varying etch rates.

[0086] In one embodiment, steps 301-303 can be repeated multiple times until flatness within a desired range is obtained.

[0087] A substrate planarization process using spatial etch rate control is now discussed below in connection with Figure 4.

[0088] Figure 4 is a flowchart of a method 400 for performing substrate planarization using spatial etch rate control in accordance with an embodiment of the present disclosure.

[0089] Referring to Figure 4, in conjunction with Figure 1, in step 401, optical metrology is performed continuously or intermittently or once at the beginning and once at the end to measure the top surface profile variation across substrate 101. [0090] In step 402, a control scheme is implemented in which the metrology information is used as feedback to control spatial etch rate actuators.

[0091] In step 403, the substrate is etched with spatially variable etch rates using techniques discussed above, such as uniform thermal actuation, spatially variable thermal actuation or spatially variable thermal actuation using a DMD system.

[0092] A processing for minimizing TTV using nP3 is now discussed below in connection with Figure 5.

[0093] Figure 5 is a flowchart of a method 500 for minimizing TTV using nP3 in accordance with an embodiment of the present disclosure.

[0094] Referring to Figure 5, in conjunction with Figure 1, in step 501, the substrate thickness and thickness variation across substrate 101 are measured using the techniques discussed above in connection with metrology sensor 112, the substrate scale metrology system using large apertures and the substrate scale metrology system using a single spot measuring sensor.

[0095] In step 502, the difference between the current and the desired profile is calculated and fed as input to the nP3 process which then inkjets a nanometer precise film thickness of polymer onto substrate 101.

[0096] In step 503, the cured resist is etched back into substrate 101 using a dry etching process, such as method 200. In one embodiment, an intermediate or a series of intermediate films are present between the polymer and substrate 101. For example, an intermediate film may correspond to silicon dioxide on a diamond substrate. In such an embodiment, the polymer profile is first transferred into silicon dioxide using a fluorine chemistry at temperatures low enough to ensure polymer stability, for example 150° C. The profile can now be etched into diamond using an oxygen dominant chemistry with high etch rates by either heating the substrate or through a DC- bias or both.

[0097] In one embodiment, the etch back is performed using an open loop control or using spatial etch rate control as discussed above in connection with thermal actuation sub-system 113 and the nozzle array for spatially varying etch rates. [0098] Steps 501-503 can be repeated multiple times until flatness within a desired range is obtained.

[0099] A discussion regarding minimizing TTY using spatial etch rate control is provided below in connection with Figure 6.

[0100] Figure 6 is a flowchart of a method 600 for minimizing TTV using spatial etch rate control in accordance with an embodiment of the present disclosure.

[0101] Referring to Figure 6, in conjunction with Figure 1, in step 601, optical metrology is performed continuously or intermittently or once at the beginning and once at the end to measure the thickness and thickness variation across substrate 101.

[0102] In step 602, a control scheme is implemented in which the metrology information is used as feedback to control spatial etch rate actuators by computing the spatial etch rates across substrate 101 using the metrology information.

[0103] In step 603, the die is etched using spatially variable etch rates using the techniques discussed above, such as uniform thermal actuation, spatially variable thermal actuation or spatially variable thermal actuation using a DMD system.

[0104] Referring now to Figure 7, Figure 7 illustrates an alternative architecture for PST equipment in comparison to the architecture presented in Figure 1 in accordance with an embodiment of the present disclosure.

[0105] As shown in Figure 7, a mirror 701 is used to direct light from the thermal actuation subsystem 113 onto substrate 101. In one embodiment, mirror 701 is placed on a moving stage. In one embodiment, a dichroic mirror or a beam splitter is used to allow the same optical path for metrology and thermal actuation. In another embodiment, the position and orientation of the metrology assembly, including metrology sensor 112, and/or the substrate scale metrology system using large apertures and/or the substrate scale metrology system using a single point sensor as discussed above, and thermal actuation sub-system 113 are interchanged. In one embodiment, metrology 112 is mounted on a metrology assembly for scanning substrate 101.

[0106] As shown in Figure 7, a mirror 701 is used to direct the light from thermal actuation subsystem 113 onto substrate 101. In one embodiment, mirror 701 is placed on a moving stage. In one embodiment, a dichroic mirror or a beam splitter is used to allow the same optical path for metrology and thermal actuation. In another embodiment, the position and orientation of the metrology assembly, including metrology sensor 112 and thermal actuation sub-system 113 are interchanged. In one embodiment, metrology sensor 112 is mounted on a metrology assembly for scanning substrate 101.

[0107] Referring now to Figure 8, Figure 8 illustrates an additional alternative architecture for PST equipment in accordance with an embodiment of the present disclosure.

[0108] As shown in Figure 8, thermal actuation sub-system 113 is placed below process chamber 102. Furthermore, as shown in Figure 8, substrate clamp 103 that is transparent to light from thermal actuation sub-system 113 is used. In another embodiment either or both the metrology sub-system using metrology sensor 112 and thermal actuation sub-system 113 are placed inside vacuum chamber 102.

[0109] In one embodiment, there can be an intermediate film between the die and the base (see 1602 of Figure 16), such that this film absorbs light from the thermal actuation sub-system 113. In one embodiment, this intermediate layer is carbon tape.

[0110] Figure 9 is a flowchart of a method 900 for performing precision substrate thinning using spatial etch rate control in accordance with an embodiment of the present disclosure.

[0111] Referring to Figure 9, in conjunction with Figures 1 and 7-8, in step 901, substrate 101 is inputted into etch chamber 102. In one embodiment, substrate 101 is diced. In another embodiment, substrate 101 is undiced. In one embodiment, the process time is reduced by reducing the thickness of the input substrate 101 using processes, such as wafer grinding and polishing.

[0112] In step 902, once substrate 101 is placed inside etch chamber 102, chamber 102 is pumped down to generate a vacuum.

[0113] In step 903, a plasma of etch gases 108 is generated. For example, in one embodiment, gases 108 suitable to etch the specific substrate material are injected inside chamber 102. In one embodiment, MFCs 107 are used to control the mass flow rate of the input gasses 108. In one embodiment, plasma is ignited following which substrate 101 is etched. [0114] In step 904, the thickness and/or thickness variation across substrate 101 are measured. In one embodiment, a metrology system, including metrology sensor 112, is used to measure the thickness and/or thickness variation of substrate 101. In one embodiment, the measurement is performed continuously or intermittently. In one embodiment, the measurement is performed once in the beginning and once at the end.

[0115] It is noted that etch rates may vary with temperature as shown in Figure 10. Figure 10 depicts the variation in etch rates as a function of temperature for silicon in accordance with an embodiment of the present disclosure.

[0116] Returning to Figure 9, in conjunction with Figures 1, 7-8 and 10, in step 905, a determination is made as to whether substrate 101 has achieved the desired specification. In one embodiment, the desired specification refers to one or more of the following: a desired thickness, a desired TTV and a desired top surface flatness of the substrate.

[0117] If the desired specification has not been achieved, then, in step 906, the required spatial thermal load for substrate 101 is computed.

[0118] In one embodiment, spatially variable etch rates can be induced by generating a spatially variable temperature profile on substrate 101. In one embodiment, the thickness variation obtained from the metrology sub-system is used to calculate the spatial temperature profile (thermal load for substrate 101). In one embodiment, the desired temperature profile is generated by varying heat input from the illumination source on different parts of substrate 101. Techniques, such as pulse width modulation (PWM), can be used for such a purpose.

[0119] Tn step 907, the computed spatial thermal load is applied using thermal actuation subsystem 113 and substrate 101 is etched with spatially variable etch rates.

[0120] In one embodiment, spatially variable etch rates are generated by varying the concentration of etch gases 108 or the plasma power across the surface of substrate 101. In one embodiment, substrate 101 is cooled by injecting gases 108, such as N2 or Ar, into process chamber 102 with plasma generator 109 switched off. In one embodiment, substrate 101 is cooled using backside He cooling. The process of metrology and thermal actuation is repeated until the thickness and TTV of substrate 101 are within specification. [0121] After applying the computed spatial thermal load using thermal actuation sub-system 113, the thickness and/or thickness variation across substrate 101 is measured in step 904.

[0122] Returning to step 905, if, however, the desired specification has been achieved, then, in step 908, the precision substrate thinning process is completed.

[0123] Figure 11 illustrates an embodiment of the present disclosure of thermal actuation subsystem 113.

[0124] As shown in Figure 11, thermal actuation sub-system 113 includes multiple high powered illumination sources including, but not limited to, laser diodes 1101 (LDs) or LEDs assembled in a two-dimensional matrix configuration. In one embodiment, LDs 1101 are mounted on a printed circuit board (PCB) 1102. In one embodiment, in order to remove heat from these LDs 1101, a heat sink is used. As shown in Figure 11, a water-cooled metal plate 1103 is used as a heat sink.

[0125] In one embodiment, PCB 1102 has thermal vias to provide a thermal pathway from the laser diodes 1101 to heat sink 1103. In one embodiment, PCB 1102 is made of standard PCB materials, such as, but not limited to, epoxy resins. In one embodiment, insulated metal substrate (IMS) PCBs 1102 are used to improve thermal conduction between heat sink 1103 and LDs 1101.

[0126] In one embodiment, a stack of optical components including, but not limited to, lenses 1104A-1104D (identified as “Lens 1,” “Lens 2,” “Lens 3,” and “Lens 4,” respectively), apertures, and reflectors are used to capture light from the illumination sources and focus them onto substrate 101. One such instance is depicted in Figure 11 where a stack of four lenses 1104A-1104D is used for each laser diode 1101. Lenses 1104A-1104D may collectively or individually be referred to as lenses 1104 or lens 1104, respectively. Tn one embodiment, the position of these optical components is varied to achieve the desired focusing distance. In one embodiment, the whole assembly is mounted on an XY stage 1105 to prevent any blind pots due to the pitch of LD 1101.

[0127] It is noted that while 11 illustrates four lenses 1104 that thermal actuation sub-system 113 may include any number of lenses 1104. Furthermore, it is noted that thermal actuation sub-system 113 may include any number of laser diodes 1101. [0128] Referring now to Figures 12A-12E, in conjunction with Figure 11, Figures 12A-12E illustrate the thermal simulation results for quantifying temperature across a die for a given heat input in accordance with an embodiment of the present disclosure.

[0129] In particular, Figure 12A illustrates the results from a transient thermal simulation used to calculate temperature with respect to time, where PST is performed on a diced Si wafer, such that the dimension of each die is 10 mm X 10 mm with a thickness of 0.75 mm. In one embodiment, the thermal load from a laser diode 1101 is simulated by applying a directional radiation of 0.45 W from a source of 2 mm diameter. The input radiation on the die is shown in Figure 12B. As indicated in Figure 12A, the temperature at the die center reaches about 200° C in 100 seconds. Figure 12C illustrates the two-dimensional temperature profde on the die in steady state. Figure 12E illustrates the steady state temperature across the cross-section line in Figure 12C. Figure 12D illustrates the temperature difference between the die-center and the die-edge with respect to time. As shown in Figure 12D, it can be concluded that temperature variation within a die is always less than 2.5° C.

[0130] Referring now to Figure 13, in conjunction with Figures 1 and 7-8, Figure 13 is a methodology for the PWM control of the illumination sources used in one instance of thermal actuation sub-system 113 in accordance with an embodiment of the present disclosure. PWM is used in illumination sources to modify the thermal load to generate desired temperature profiles on substrate 101. A power supply 1301 is connected to a buck controller 1302, which outputs a constant current to LDs 1101A-1101N, where N is a positive integer number, and LEDs. Laser diodes 1101A-110N may collectively or individually be referred to as laser diodes 1101 or laser diode 1101, respectively. In one embodiment, LDs 1101 are connected to a matrix manager 1303 which consists of switches 1304A-1304N (identified as “SWA. .. SWN,” where N is a positive integer number) that can be independently programmed to bypass the LD 1101 across that switch by microcontroller 1305. Switches 1304A-1304N may collectively or individually be referred to as switches 1304 or switch 1304, respectively. In one embodiment, LD 1101 can be fully on, fully off or dimmed using PWM. [0131] Referring now to Figures 14A-14B, Figures 14A-14B illustrate simulation and experimental results of the optical lens stack to focus diverging light from a laser diode in accordance with an embodiment of the present disclosure.

[0132] Illumination sources, such as LDs 1101 and LEDs, typically give out diverging light. In one embodiment, optical components are used to capture this diverging light and focus it onto substrate 101 as a small spot. In one embodiment, optical components, including, but not limited to, aspheric lenses, concave lenses, convex lenses, plano-concave lenses, plano-convex lenses, freeform lenses, parabolic reflectors, ellipsoidal reflectors, optical fibers and their combination are used for this purpose. In one embodiment, optical components have suitable coatings to enhance light transmission. Figure 14B illustrates the simulation results for an instance of such an optical assembly 1401 presented in Figure 14A, where light from the laser diode is focused on a substrate, such as substrate 101 of Figure 1, 400 mm away. Separation between lenses 1104 can be modified to adjust the focusing distance. In one embodiment, optical assembly 1401, as shown in Figure 14A, consists of an illumination source, such as a 1.6 W, 447 nm laser diode with a divergence beam angle of 56°, a first lens (Lens 1) 1104A (aspheric lens), a second lens (Lens 2) 1104B (piano convex lens with a curvature radius of 20.67 mm), a third lens (Lens 3) 1104C (piano concave lens with a curvature radius of 21.19 mm) and a fourth lens (Lens 4) 1104D (piano convex lens with a curvature radius 25.48 mm).

[0133] In one embodiment, lenses 1104 of optical assembly 1401 have a MgF2 anti-reflective coating. Figure 14B depicts the resultant illumination profile on a 4 mm X 4 mm die. As shown in Figure 14B, Figure 14B suggests that the die receives 1.39 W of power thereby indicating an efficiency of - 87%.

[0134] Referring now to Figures 15A-15C, Figures 15A-15C illustrate substrate scale metrology using single point sensors in accordance with an embodiment of the present disclosure.

[0135] In cases where the sensing area is smaller than substrate 101, various techniques can be used as illustrated in Figures 15A-15C to scan the entire substrate 101. As shown in Figure 15A, a single sensor 1501 is mounted on an XY stage 1105. As shown in Figure 15B, an array of sensors 1502 is mounted on XY stage 1105 to reduce the metrology time. In another embodiment, array of sensors 1502 is mounted on a linear stage or a rotary stage. Figure 15C illustrates a configuration in which array of sensors 1502 is placed at an angle with respect to the direction of motion which helps in achieving a lower effective pitch. In such an embodiment, the metrology may potentially be reduced to a single scan in one direction. Other configurations, including, but not limited to, VPM, rotary stages, etc. may also be used.

[0136] Referring now to Figure 16, Figure 16 illustrates the inter-die features to address edge nonuniformities in accordance with an embodiment of the present disclosure.

[0137] With diced substrates there is a possibility of thickness variation and non-uniformities around the edges of the die due to lateral etch. In one embodiment, the principles of the present disclosure address these edge non-uniformities by having features between the dies as shown in Figure 16. As illustrated in Figure 16, the substrate consists of discrete dies 1601, which can be from a variety of electronic or optical materials. Base 1602, upon which these discrete dies 1601 are placed, can be a polymer base, a tape frame, a glass carrier, a sapphire carrier, a transparent carrier, a silicon carrier, a silicon carbide carrier, etc. By adjusting the geometry of inter-die features 1603, it is possible to influence the amount of etch species in the kerf and tune the process from edge fast to edge slow. In one embodiment, inter-die features 1603 are made with materials including, but not limited to, polymers, silicon dioxide, silicon carbide, silicon nitride, alumina, copper, titanium and titanium oxide.

[0138] Figure 17 is a flowchart of a method 1700 for generating inter-die features 1603 in accordance with an embodiment of the present disclosure. Figures 18A-18F depict the cross- sectional views for generating inter-die features 1603 using the steps described in Figure 17 in accordance with an embodiment of the present disclosure.

[0139] Referring to Figure 17, in conjunction with Figures 18A-18F, in step 1701, a conformal sacrificial layer 1801 is coated on substrate dies 1601 and exposed portions of substrate 101 as shown in Figures 18A-18B. In one embodiment, coating processes include, but not limited to, chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, flowable chemical vapor deposition and atomic layer deposition. In one embodiment, conformal sacrificial film 1801 is one or more of the following: an oxide, silicon oxide, aluminum oxide, silicon carbide, silicon nitride, Fluro-polymer, polymer, photoresist, carbon and adhesive. [0140] In step 1702, an anisotropic etch of sacrificial film 1801 is performed using processes including, but not limited to, reactive-ion-etching as shown in Figure 18C. For example, as shown in Figure 18C, the top potion of the sacrificial film 1801 residing on the top surface of substrate dies 1601 and the top potion of the sacrificial film 1801 residing on the top surface of substrate 101 are etched away.

[0141] In step 1703, a gap fill material is deposited on the exposed portions of substrate 101 (as well as the top surface of substrate dies 1601) as shown in Figure 18D. In one embodiment, photoresist 1802 (e.g., polymer) is deposited using a process, such as via spin-coating or inkjetting. In another embodiment, gap fill material consists of one or more of the following: an oxide, silicon oxide, aluminum oxide, silicon carbide, silicon nitride, Fluro-polymer, polymer, photoresist, carbon and adhesive.

[0142] In step 1704, the top layer of gap fill material 1802 (residing on the top surface of substrate dies 1602) is removed as shown in Figure 18E.

[0143] In step 1705, the remaining conformal sacrificial film 1801 is removed using an etch process thereby forming inter-die features 1803 as shown in Figure 18F.

[0144] In one embodiment, the desired width of inter-die features 1803 is obtained by adjusting the thickness of the conformal sacrificial film (SiCh) 1801 in step 1701.

[0145] Referring now to Figures 19A-19B, Figures 19A-19B illustrate an exemplary process for profile correcting using nP3 in accordance with an embodiment of the present disclosure.

[0146] As shown in Figure 19 A, the original substrate 1901 is coated with polymer film 1902. In one embodiment, the material of the original substrate 1901 is silicon. In one embodiment, the top surface profile of substrate 1901 is measured using a metrology system. The nP3 process uses this information to inkjet a nanometer precise, planarized film 1902 of polymer onto the non-uniform substrate 1901. This planarized profile is now transferred to the original substrate 1901 through etch back as shown in Figure 19B.

[0147] Referring now to Figures 20A-20C, Figures 20A-20C illustrate a process for profile correction using an intermediate film in accordance with an embodiment of the present disclosure. [0148] As shown in Figure 20A, substrate (original substrate) 2001 is coated with an intermediate film 2002 and a polymer film 2003. As further shown in Figure 20A, intermediate film 2002 is used between substrate 2001 and polymer film 2003. In such an embodiment, the profile is first transferred onto intermediate film 2002 as shown in Figure 20B at temperatures low enough to ensure polymer stability. Figure 20C illustrates the profile transferred from intermediate film 2002 onto substrate 2001. In particular, this profile can now be etched into the material of substrate 2001 using high temperatures or DC-bias to enhance etch rates as shown in Figure 20C.

[0149] Referring nowto Figure 21, in conjunction with Figures 1 and 7-8, Figure 21 is aflowchart of a method 2100 for PST using nP3 in accordance with an embodiment of the present disclosure.

[0150] In step 2101, the thickness and thickness variation across substrate 101 is measured.

[0151] In step 2102, based on such a measurement, the spatial thickness profile of the polymer to be used as coating to minimize the TTV is calculated. In one embodiment, the required thickness of the polymer depends on the etch selectivity of the polymer with respect to substrate 101.

[0152] In step 2103, a polymer film of the calculated thickness (“profile”) is then coated on substrate 101, such as via an inkjet, using the nP3 process.

[0153] In step 2104, the profile is then etched back into the original substrate.

[0154] In one embodiment, an intermediate layer, such as shown in Figures 20A-20B, may also be present. In one embodiment, the process discussed above (steps 2101-2014) is repeated until the thickness variation in substrate 101 is within specification.

[0155] Referring now to Figure 22, Figure 22 illustrates a substrate having dies of different thickness in accordance with an embodiment of the present disclosure.

[0156] PST can also be used for substrate thinning when the desired thickness may be different for each or a group of substrate dies 1601. As shown in Figure 22, Figure 22 depicts such a scenario in which the desired thickness of substrate dies 1601 are different. In one embodiment, the desired thickness of substrate dies 1601 are different using method 900, such that the variable thermal load is applied on dies 1601 to achieve the desired different die thicknesses. In another embodiment, method 2100 may be used such that the thickness profile of the polymer film to be coated accounts for the different thicknesses on each substrate die 1601. [0157] Referring now to Figure 23, Figure 23 illustrates an exemplary method 2300 for three- dimensional (3D) integration, one of the use cases for PST, in accordance with an embodiment of the present disclosure.

[0158] As depicted in Figure 23, method 2300 includes a source wafer 2301 in which material on the surface of source wafer 2301 is mechanically removed using chemical mechanical polishing 2302. The source wafer may then be grounded down to a desired thickness via grinding 2303. The source wafer may then be cut or diced into dies via dicing 2304 followed by picking and placing the dies for bonding 2305. After picking and placing the dies for bonding 2305, annealing 2306 is performed thereby forming a three-dimensional (3D) integrate circuit (IC) 2307.

[0159] As shown in Figure 23, PST (precision substrate thinning) 2308 can be accommodated in different stages of method 2300. PST can be performed before or after dicing 2304, after pick and place 2305 or after annealing 2306. In one embodiment, the input substrate to PST may have variations based on where PST is accommodated in method 2300. The variations can be the substrate being diced or undiced as well as the base film being of different material among others.

[0160] In one embodiment, PST, using process 900, is performed after dicing and is further performed after pick & place assembly onto the product substrate 101. In such an embodiment, the PST is used to improve the TTV of the dies to be below one of the following: 1 pm, 500 nm, 200 nm, 100 nm, 50 nm, 25 nm and 10 nm. Furthermore, in such an embodiment, PST is performed for the dies to achieve a final mean thickness below one of the following: 100 pm, 50 pm, 10 pm, 5 pm and 1 pm.

[0161] In another embodiment, PST, using process 900, is performed after dicing and is further performed prior to pick and place assembly. In such an embodiment, PST is performed on one or more of the following carrier substrates: tape frame, glass, sapphire and silicon carbide. In such an embodiment, the PST is used to improve the TTV of the dies to be below one of the following: 1 pm, 500 nm, 200 nm, 100 nm, 50 nm, 25 nm and 10 nm. Furthermore, in such an embodiment, PST is performed for the dies with a thickness below one of the following: 100 pm, 50 pm, 10 pm, 5 pm and 1 pm.

[0162] In another embodiment, PST, using process 2100, is performed prior to dicing. In such an embodiment, PST is performed on one or more of the following carrier substrates: tape frame, glass, sapphire and silicon carbide. In such an embodiment, the PST is used to improve the TTV of the substrate to be below one of the following: 1 pm, 500 nm, 200 nm, 100 nm, 50 nm, 25 nm and 10 nm. In one embodiment, a multi-step approach is utilized, where a first step process is performed at a higher etch rate and one or more subsequent processes are performed at lower etch rates.

[0163] In one embodiment, one or more substrate thinning steps using process 2100 are performed prior to dicing followed by performing one or more substrate thinning steps using process 900 after dicing.

[0164] Table 1, shown below, describes the various potential choices for etch gases and process conditions that can be utilized for specific substrate materials in accordance with an embodiment of the present disclosure.

Table 1

[0165] Figure 24 is a flowchart of an alternative method 2400 for generating inter-die features in accordance with an embodiment of the present disclosure. Figures 25A-25C depict the cross- sectional views for generating inter-die features using the steps described in Figure 24 in accordance with an embodiment of the present disclosure.

[0166] Referring to Figure 24, in conjunction with Figures 25A-25C, in step 2401, a deposition of photoresist 1802 (e.g., polymer) onto substrate dies 1601 and substrate 101 is performed using a process, such as spin-coating or ink-jetting, as shown in Figures 25A-25B.

[0167] In step 2402, an alignment and photolithography are performed to generate inter-die features 1803 as shown in Figure 25C.

[0168] As a result of the foregoing, the principles of the present disclosure provide a means for improving the precision for substrate thinning.

[0169] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.