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Title:
PSEUDO-COMPLEMENTARY LOGIC NETWORK
Document Type and Number:
WIPO Patent Application WO/2020/122524
Kind Code:
A1
Abstract:
A pseudo-complementary logic network according to the present embodiment comprises: a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit; and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes a second pull-down circuit.

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Inventors:
KIM EUN HWAN (KR)
KIM JAE-JOON (KR)
Application Number:
PCT/KR2019/017283
Publication Date:
June 18, 2020
Filing Date:
December 09, 2019
Export Citation:
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Assignee:
POSTECH RES & BUSINESS DEV FOUND (KR)
International Classes:
H03K19/0948; H03K19/00
Foreign References:
KR20170015933A2017-02-10
JPH0746511B21995-05-17
JPH05235744A1993-09-10
KR970705869A1997-10-09
KR20000027846A2000-05-15
Attorney, Agent or Firm:
ISIS IP LAW LLC (KR)
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