Title:
PULSE WIDTH CLOCK TOPOLOGY STRUCTURE CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/071007
Kind Code:
A1
Abstract:
A pulse width clock topology structure circuit, comprising a clock pulse width generation module and a clock topology delay module. The clock pulse width generation module connects an input clock and n stages of delay sub-modules in series; an output end of each stage of delay sub-module is connected to an input end of a selector; a certain required delay clock is selected by means of m+1 control signals of the selector, and an "AND" operation is performed on the required delay clock and an original input clock, so as to generate different pulse width clock outputs and take same as inputs of the clock topology delay module; and the clock topology delay module can generate a plurality of different delay clocks for different latches to use.
Inventors:
JIANG XIAOWEI (CN)
BAO XINGGANG (CN)
BAO XINGGANG (CN)
Application Number:
PCT/CN2022/078669
Publication Date:
May 04, 2023
Filing Date:
March 01, 2022
Export Citation:
Assignee:
SHANGHAI YIJIAXIN INTEGRATED CIRCUIT DESIGN CO LTD (CN)
International Classes:
H03K7/08
Foreign References:
| CN114024532A | 2022-02-08 | |||
| CN102035514A | 2011-04-27 | |||
| CN110492872A | 2019-11-22 | |||
| CN108449078A | 2018-08-24 | |||
| CN101552600A | 2009-10-07 |
Attorney, Agent or Firm:
BEIJING TIAN LAN LAW FIRM (CN)
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