Title:
PWM SIGNAL GENERATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2007/046363
Kind Code:
A1
Abstract:
After a moment in time when the level of an output signal (S4) is inverted by first
and second short circuit FETs (55, 56) as a circuit for inhibiting level inversion,
the inverted state is sustained and level inversion is inhibited. At a moment
in time when the level is inverted next at a regular timing corresponding to the
desired duty ratio of a PWM signal S1, inhibition of level inversion is lifted.
Consequently, chattering can be prevented even when the level of a reference
signal (S3) is varied by, for example, noise during acceleration of a vehicle
and a PWM signal (S1) having a stabilized duty ratio can be generated.
Inventors:
KATO MASAYUKI (JP)
TAKAHASHI SEIJI (JP)
FURUICHI MASAHIKO (JP)
ISSHIKI ISAO (JP)
TAKAHASHI SEIJI (JP)
FURUICHI MASAHIKO (JP)
ISSHIKI ISAO (JP)
Application Number:
PCT/JP2006/320626
Publication Date:
April 26, 2007
Filing Date:
October 17, 2006
Export Citation:
Assignee:
AUTONETWORKS TECHNOLOGIES LTD (JP)
SUMITOMO WIRING SYSTEMS (JP)
SUMITOMO ELECTRIC INDUSTRIES (JP)
KATO MASAYUKI (JP)
TAKAHASHI SEIJI (JP)
FURUICHI MASAHIKO (JP)
ISSHIKI ISAO (JP)
SUMITOMO WIRING SYSTEMS (JP)
SUMITOMO ELECTRIC INDUSTRIES (JP)
KATO MASAYUKI (JP)
TAKAHASHI SEIJI (JP)
FURUICHI MASAHIKO (JP)
ISSHIKI ISAO (JP)
International Classes:
H03K7/08; H02M7/48; H03K17/16
Foreign References:
| JPH1141077A | 1999-02-12 | |||
| JPH1197989A | 1999-04-09 | |||
| JPH05168164A | 1993-07-02 |
Attorney, Agent or Firm:
GORO, Kazuo et al. (Midori Nagoya Bldg. 8th Floor 22-4, Meieki 3-chome, Nakamura-k, Nagoya-shi Aichi 02, JP)
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