Technical Field

The present invention relates generally to the field of quadrature mixers. More particularly, it relates to quadrature passive mixers suitable for receiver front-ends for wireless communication devices.

Background

Generally, a mixer may be used to convert a signal at a first carrier frequency (or baseband) to a corresponding signal at a second carrier frequency (or baseband). The inputs and outputs of the mixer may, respectively, be single-ended - where the signal is defined by a single node in relation to ground (or some other reference) - or differential - where the signal is defined by the difference between two nodes.

For example, it may be desirable in a wireless communication device to convert a received radio frequency signal to a baseband (or intermediate frequency) quadrature signal before the further processing of the received signal takes place. Such an operation is typically carried out in a receiver front-end of the wireless

communication device. An example is disclosed in F. Tillman, N. Troedsson, H.

Sjoland, "A 1.2 volt 1.8GHz CMOS quadrature front-end," VLSI Circuits, Digest of Technical Papers 2004 Symposium on, pp.362-365, 17-19 June 2004.

Generally, but in particular for applications where low cost, small size and/or low power consumption is desirable, it may be beneficial to minimize the amount of components (especially off-chip components) needed between an antenna port of the wireless communication device and the node(s) where the baseband (or intermediate frequency) signal is provided for further processing. Examples of such components where it might be beneficial to minimize or completely dispose of are antenna port filters (e.g. surface acoustic wave - SAW - filters) and amplifiers (e.g. low noise amplifiers - LNA).

Having a receiver front-end structure without (or with reduced number of) filters in the radio frequency path typically imposes high requirements on the other components (e.g. mixers) regarding linearity over a wide frequency range (out-of-band). Reducing the gain of the radio frequency amplifiers, or completely removing the radio frequency amplifiers, increases the requirements on low noise in the other components.

Other requirements that become increasingly important in such structures include harmonic mixing and local oscillator leakage to the radio frequency input.

Wireless communication devices with very low power consumption are highly sought after. O. Ikeuchi, N. Saito, B. Nauta, "Quadrature Sampling Mixer Topology for SAW-Less GPS Receivers in 0.18um CMOS", 2010 Symposium on VLSI Circuits, Technical Digest of Technical Papers, pp. 177-178 and K. Jusung, J. Silva-Martinez, "Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for

Multistandard Applications", IEEE Journal of Solid-State Circuits, vol.48, no. 9, sept 2013, pp. 2090-2103 both discloses mixer structures that may be considered in such contexts.

However, there is a need for mixers for down-conversion of radio frequency signals without (or with reduced) prior filtering or amplification, wherein the mixers have even more suitable characteristics for that purpose or, at least, represent an alternative structure.

Summary

It should be emphasized that the term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

It is an object of some embodiments to obviate at least some of the above disadvantages and to provide mixers for down-conversion of radio frequency signals without (or with reduced) prior filtering or amplification.

According to a first aspect, this is achieved by a quadrature passive mixer for a receiver front-end adapted to convert a radio frequency signal provided at an input of the mixer to a baseband, or intermediate frequency, quadrature signal at an output of the mixer. The mixer comprises first and second in-phase branches and first and second quadrature branches. The first in-phase branch is connected between the input of the mixer and an in-phase port of the output of the mixer, the second in-phase branch is connected between the input of the mixer and the in-phase port of the output of the mixer, the first quadrature branch is connected between the input of the mixer and a quadrature port of the output of the mixer, and the second quadrature branch is connected between the input of the mixer and the quadrature port of the output of the mixer.

Each of the first and second in-phase branches and first and second quadrature branches comprises first and second switch devices in series. The switch devices are adapted to be operated by respective quadrature phases of a local oscillator signal such that, at each moment in time, only one of the first and second in-phase branches and first and second quadrature branches is conductive.

The mixer also comprises a first in-phase capacitor connected at a node between the first and second switch devices of the first in-phase branch and at a node between the first and second switch devices of the second in-phase branch, and a first quadrature capacitor connected at a node between the first and second switch devices of the first quadrature branch and at a node between the first and second switch devices of the second quadrature branch.

Operating the switch devices by respective quadrature phases of a local oscillator signal such that, at each moment in time, only one of the first and second in- phase branches and first and second quadrature branches is conductive may, for example, be implemented by letting the switches of each branch be operated by respective and different pairs of adjacent quadrature phases of the local oscillator signal.

In some embodiments, the quadrature phases of the local oscillator signal may comprise first, second, third and fourth phases, wherein the second phase equals the first phase minus approximately 90° (π/2 rad), the third phase equals the first phase plus approximately 90° (π/2 rad), and the fourth phase equals the first phase plus

approximately 180° (π rad).

For example, the second phase may be in a range between the first phase minus

110° and the first phase minus 70°, the third phase is in a range between the first phase plus 70° and the first phase plus 110°, and the fourth phase is in a range between the first phase plus 160° and the first phase plus 200°.

Other ranges (than the ±20° applied in the example above) may be applied according to various embodiments, for example, ±1°, ±2°, ±5, °±10°, or ±15°.

In some embodiments, the ranges may be asymmetrical (e.g. the second phase being in a range between the first phase minus 95° and the first phase minus 70°).

Different or the same ranges may be applied for different ones of the second, third and fourth phases.

In some embodiments, the second phase equals the first phase minus 90°, the third phase equals the first phase plus 90°, and the fourth phase equals the first phase plus 180°.

The first switch device of the first in-phase branch and the first switch device of the first quadrature branch may be adapted to be operated by the first phase of the local oscillator signal. The second switch device of the first in-phase branch and the second switch device of the second quadrature branch may be adapted to be operated by the second phase of the local oscillator signal. The second switch device of the first quadrature branch and the second switch device of the second in-phase branch may be adapted to be operated by the third phase of the local oscillator signal. The first switch device of the second in-phase branch and the first switch device of the second quadrature branch may be adapted to be operated by the fourth phase of the local oscillator signal.

According to some embodiments, the first switch device of the first in-phase branch and the first switch device of the first quadrature branch may be implemented by a single switch device, and the first switch device of the second in-phase branch and the first switch device of the second quadrature branch may be implemented by a single switch device. Then, the first in-phase capacitor and the first quadrature capacitor may be implemented as a single capacitor.

In some embodiments, the quadrature passive mixer may further comprise third and fourth in-phase branches and third and fourth quadrature branches, wherein the third in-phase branch is connected between the input of the mixer and the in-phase port of the output of the mixer, the fourth in-phase branch is connected between the input of the mixer and the in-phase port of the output of the mixer, the third quadrature branch is connected between the input of the mixer and the quadrature port of the output of the mixer, and the fourth quadrature branch is connected between the input of the mixer and the quadrature port of the output of the mixer.

Each of the third and fourth in-phase branches and third and fourth quadrature branches may comprise first and second switch devices in series, wherein the switch devices are adapted to be operated by respective quadrature phases of the local oscillator signal such that, at each moment in time, only one of the third and fourth in- phase branches and third and fourth quadrature branches is conductive.

In these embodiments, the mixer may also comprise a second in-phase capacitor connected at a node between the first and second switch devices of the third in-phase branch and at a node between the first and second switch devices of the fourth in-phase branch, and a second quadrature capacitor connected at a node between the first and second switch devices of the third quadrature branch and at a node between the first and second switch devices of the fourth quadrature branch.

Switch devices and/or capacitors may, according to some embodiments, be shared by the third and fourth in-phase and quadrature branches in a similar manner as explained above for the first and second in-phase and quadrature branches.

According to some of these embodiments, the first switch device of the third in-phase branch and the first switch device of the fourth quadrature branch may be implemented by a single switch, the first switch device of the fourth in-phase branch and the first switch device of the third quadrature branch may be implemented by a single switch device, and the second in-phase capacitor and the second quadrature capacitor may be implemented as a single capacitor.

The operation by respective quadrature phases of the local oscillator signal of the switch devices of the third and fourth in-phase branches and third and fourth quadrature branches and the operation by respective quadrature phases of the local oscillator signal of the switch devices of the first and second in-phase branches and first and second quadrature branches may provide for that the first and third in-phase branches are conductive at the same time, the second and fourth in-phase branches are conductive at the same time, the first and third quadrature branches are conductive at the same time, and the second and fourth quadrature branches are conductive at the same time. This may, for example, be achieved by letting the switches of the branches that are to be conductive at the same time be operated by the same pair of adjacent quadrature phases of the local oscillator signal.

In some embodiments, the first switch device of the third in-phase branch and the first switch device of the fourth quadrature branch may be adapted to be operated by the second phase of the local oscillator signal, the second switch device of the third in- phase branch and the second switch device of the third quadrature branch may be adapted to be operated by the first phase of the local oscillator signal, the second switch device of the fourth quadrature branch and the second switch device of the fourth in- phase branch may be adapted to be operated by the fourth phase of the local oscillator signal, and the first switch device of the fourth in-phase branch and the first switch device of the third quadrature branch may be adapted to be operated by the third phase of the local oscillator signal.

Each branch of the passive quadrature mixer of the first aspect may further comprise a load capacitor according to some embodiments. The load capacitor may, for example, be connected between the second switch device and a reference node (e.g. signal ground or any other suitable reference potential). Alternatively, the load capacitor may be connected in a differential manner.

In some of these embodiments, the load capacitor of the first in-phase branch and the load capacitor of the third in-phase branch may be implemented by a single capacitor, the load capacitor of the second in-phase branch and the load capacitor of the fourth in-phase branch may be implemented by a single capacitor, the load capacitor of the first quadrature branch and the load capacitor of the third quadrature branch may be implemented by a single capacitor, and the load capacitor of the second quadrature branch and the load capacitor of the fourth quadrature branch may be implemented by a single capacitor.

A second aspect is a receiver front-end comprising the quadrature passive mixer of the first aspect.

In the receiver front-end of the second aspect, the mixer may be adapted to receive the radio frequency signal at the input of the mixer directly from the antenna (i.e. without prior amplification and/or without prior filtering) according to some embodiments.

The receiver front-end may further comprise a voltage controlled oscillator adapted to provide a voltage controlled oscillator signal having a frequency which equals a multiple of the frequency of the local oscillator signal and a frequency divider adapted to generate the quadrature phases of the local oscillator signal from the voltage controlled oscillator signal according to some embodiments. The multiple may, for example be equal to 2 according to some embodiments.

A third aspect is a wireless communication device comprising the receiver front-end of the second aspect.

The wireless communication device may, for example, be compliant with Bluetooth low energy requirements.

According to some embodiments a direct conversion receiver front-end is provided with high out-of-band linearity and low quadrature error, which seeks to mitigate, alleviate or eliminate one or more of the above-identified deficiencies in the art and disadvantages singly or in any combination.

Some embodiments relate, in general, to the field of integrated electronic devices and especially to a receiver front-end of such a device.

A fourth aspect relates to a front-end system for a radio device, wherein said front-end system comprises an LNA-less architecture with a direct conversion passive mixer structure (see e.g. Figure 3).

In some embodiments, the direct conversion passive mixer structure may be placed directly at an antenna port of said front-end system (see e.g. Figure 1).

The front-end system may comprise a local oscillator generator according to some embodiments. The local oscillator generator may comprise an oscillator (see e.g. Figure 10) and a divider (see e.g. Figure 10), wherein said divider may be a complementary divider structure adapted for offering a local oscillator with a low quadrature error.

The front-end system and receiver may be operating at 2.6 GHz.

The front-end system may be adapted for the Bluetooth Low Energy specification. A fifth aspect relates to radio device comprising the front-end system according to the previous aspect.

An ultra- low power direct conversion receiver front-end operating at 2.6 GHz with high out-of-band linearity and low quadrature error may be achieved by practicing some embodiments of the invention, use of efficient mixers with improved out-of-band suppression, and use of an LO generator achieving current reuse and rejection of VCO signal imbalance through the use of complementary devices.

An advantage of some embodiments is that the mixer characteristics provide for high linearity over a large (out-of-band) frequency range.

Another advantage of some embodiments is that the noise generated by the mixer is low.

Another advantage of some embodiments is that the quadrature error and/or the local oscillator leakage to the radio frequency input may be kept at a low level.

Yet another advantage of some embodiments is that the second order harmonic down-conversion is well suppressed.

Brief Description of the Drawings

Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings, in which.

Fig. 1 is a schematic drawing illustrating an example receiver front-end structure according to some embodiments;

Fig. 2 illustrates mixer input impedance due to frequency translation;

Fig. 3 is a schematic circuit diagram illustrating an example mixer according to some embodiments;

Fig. 4 is a schematic circuit diagram illustrating an example single balanced AND-function sampling mixer;

Fig. 5 is a schematic circuit diagram illustrating optimization of an AND- function mixer;

Fig. 6 is a schematic circuit diagram illustrating modeling of an AND-function mixer with in-phase and quadrature capacitors according to some embodiments; Fig. 7 is a schematic circuit diagram illustrating second harmonic suppression by in-phase and quadrature capacitors according to some embodiments;

Fig. 8 is a plot illustrating second harmonic suppression and interference reduction by in-phase and quadrature capacitors according to some embodiments;

Fig. 9 is a schematic drawing illustrating an example baseband amplifier;

Fig. 10 is a schematic drawing illustrating an example local oscillator circuit (voltage controlled oscillator and frequency divider) according to some embodiments;

Fig. 1 1 is a schematic drawing illustrating derivation of the voltage controlled oscillator structure;

Fig. 12 is a plot illustrating simulated maximum and minimum divider input frequency;

Fig. 13 is a schematic drawing illustrating propagation of voltage controlled oscillator imbalance;

Fig. 14 is a plot illustrating suppression of voltage controlled oscillator imbalance;

Fig. 15 is a die photo of an example receiver front-end according to some embodiments;

Fig. 16 is a plot illustrating operating frequency versus tuning voltage;

Fig. 17 is a plot illustrating measurements of input reflection;

Fig. 18 is a plot illustrating noise figure and gain;

Fig. 19 is a plot illustrating the ldB compression point as a function of offset frequency;

Fig. 20 is a plot illustrating the third-order input intercept point;

Fig. 21 is a plot illustrating quadrature error measurements;

Fig. 22 is a plot illustrating the second-order input intercept point;

Fig. 23 is a plot illustrating measured noise figure; and

Fig. 24 is a schematic circuit diagram illustrating an example mixer according to some embodiments. Detailed Description

In the following, embodiments will be described where a quadrature passive mixer for a receiver front-end adapted to convert a radio frequency signal provided at an input of the mixer to a baseband (or intermediate frequency) quadrature signal at an output of the mixer is provided with one or more capacitors, connecting a pair of in- phase branches with each other and connecting a pair of quadrature branches with each other.

Various advantages arise from the use of the capacitor(s). For example, the mixer becomes more suitable for use in a receiver front-end and/or for connection directly to an antenna port (i.e. without prior filtering or amplification) of a wireless communication device. The out-of-band linearity is excellent. Furthermore, the second harmonic down-conversion is considerably suppressed (or even completely removed).

Generally, the mixer according to embodiments presented herein comprises at least two in-phase branches and two quadrature branches connected between the input of the mixer and respective ports of the output of the mixer.

Each branch comprises two switch devices (e.g. implemented by CMOS transistors or in any other suitable way as easily realized by the skilled person) in series. Each of the switch devices is operated by a respective quadrature phase of a local oscillator signal such that, at each moment in time, only one of the two in-phase branches and two quadrature branches is conductive.

The one or more capacitors are connected from a node between the switch devices of one in-phase branch to a node between the switch devices of another in-phase branch and correspondingly for the two quadrature branches.

The size of the capacitor(s) should typically be selected based on the specific implementation of the mixer, where a tradeoff should be considered between low enough capacitance to avoid parasitic capacitance to ground and high enough capacitance to get a sharp roll-off profile.

In a typical example, one in-phase branch and one quadrature branch may share one switch device for compact implementation and/or reduced switch resistance, and the same capacitor used to connect the in-phase branches may then be used to connect the quadrature branches. To avoid or at least decrease the I/Q imbalance, DC offset, and/or LO leakage, the structure above may be complemented by a symmetry portion having two further in- phase branches and two further quadrature branches.

One example of such a mixer 300 is illustrated in Figure 3, where a radio frequency input signal is to be provided at an input port 323 for conversion to a lower frequency quadrature signal at output ports 319-322.

In this example, a first in-phase branch has a first switch device 301 and a second switch device 303, a second in-phase branch has a first switch device 302 and a second switch device 304, a first quadrature branch has a first switch device 301 (shared with the first in-phase branch) and a second switch device 305, and a second quadrature branch has a first switch device 302 (shared with the second in-phase branch) and a second switch device 306. A capacitor 313 connects the two in-phase branches (and simultaneously the two quadrature branches) between the switch devices to achieve at least some advantages (e.g. one or more of the advantages mentioned above).

A symmetry portion is also provided according to this example, wherein a third in-phase branch has a first switch device 307 and a second switch device 309, a fourth in-phase branch has a first switch device 308 and a second switch device 310, a fourth quadrature branch has a first switch device 307 (shared with the third in-phase branch) and a second switch device 311, a third quadrature branch has a first switch device 308 (shared with the fourth in-phase branch) and a second switch device 312, and a capacitor 314 connects the two in-phase branches (and simultaneously the two quadrature branches) between the switch devices.

The symmetry is achieved by controlling the switch devices of the first in- phase path with the same local oscillator phases as the switch devices of the third in- phase path to ensure that these two paths are simultaneously conductive (see e.g. 301, 303, 307 and 309 of Figure 3), and correspondingly for all symmetry path pairs.

The capacitors 315-318 represent the load capacitors between output ports and ground.

Another example of such a mixer 2400 is illustrated in Figure 24, where a radio frequency input signal is to be provided at an input port 2423 for conversion to a lower frequency quadrature signal at output ports 2419-2422. In this example, a first in-phase branch has a first switch device 2401 and a second switch device 2403, a second in-phase branch has a first switch device 2402 and a second switch device 2404, a first quadrature branch has a first switch device 2401 ' and a second switch device 2405, and a second quadrature branch has a first switch device 2402' and a second switch device 2406. A capacitor 2413 connects the two in- phase branches between the switch devices and a capacitor 2413' connects the two quadrature branches between the switch devices to achieve at least some advantages (e.g. one or more of the advantages mentioned above).

In a single-ended input version of the mixer, the above-described components make up the mixer structure. In a differential input version, however, the mixer is also provided with a third in-phase branch having a first switch device 2407 and a second switch device 2409, a fourth in-phase branch having a first switch device 2408 and a second switch device 2410, a third quadrature branch having a first switch device 2407' and a second switch device 2411, a fourth quadrature branch having a first switch device 2408' and a second switch device 2412. A capacitor 2414 connects the two in- phase branches between the switch devices and a capacitor 2414' connects the two quadrature branches between the switch devices.

Two load capacitors may, according to some example implementations, be connected in a differential manner, i.e. between the two in-phase output ports 2421, 2422 and between the two quadrature output ports 2419, 2420, respectively.

Alternatively, load capacitors may be connected between respective output port 2419, 2420, 2421, 2422 and a reference node (e.g. signal ground).

The described embodiments and their equivalents may be realized in hardware. They may be performed by specialized circuits such as for example application-specific integrated circuits (ASIC). All such forms are contemplated to be within the scope of this disclosure.

Embodiments may appear within an electronic apparatus (such as a wireless communication device) comprising circuitry/logic according to any of the

embodiments. The electronic apparatus may, for example, be a portable or handheld mobile radio communication equipment, a mobile radio terminal, a mobile telephone, a communicator, an electronic organizer, a smartphone, a computer, a notebook, a hearing aid, a wireless headset, or a mobile gaming device.

Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims. For example, it should be noted that in the description of embodiments, the partition of functional blocks into particular units is by no means limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. In the same manner, functional blocks that are described herein as being implemented as two or more units may be implemented as a single unit without departing from the scope of the claims.

Hence, it should be understood that the details of the described embodiments are merely for illustrative purpose and by no means limiting. Instead, all variations that fall within the range of the claims are intended to be embraced therein.

An illustrative example in terms of a 0.55mW SAW-less receiver front-end for Bluetooth Low Energy applications will now be disclosed in more detail with reference to the attached figures.

An ultra- low power direct conversion receiver front-end operating at 2.6 GHz with high out-of-band linearity and low quadrature error will be described in this example. This is achieved through the use of efficient mixers with improved out-of- band suppression, and an LO generator achieving current reuse and rejection of VCO signal imbalance through the use of complementary devices. Manufactured in 65 nm CMOS and with a power consumption below 550 μW from a 0.85 V supply, the front- end achieves a conversion gain of 41 dB and a noise figure of 9.6 dB. It has an out-of- band IIP ₃ and IIP ₂ of -3 dBm and 29.5 dBm, respectively. The quadrature phase error is below 0.6°. Requiring only two inductors it occupies an area of just 0.15 mm ² excluding pads. I. INTRODUCTION

As wireless technology becomes ever more ubiquitous there is increasing focus on portability, extending beyond purely cellular applications. With small and low cost radio circuits we enable communication with small devices around us or even on us. In many cases these devices should for maximum usability be able to operate extended periods, weeks, months or perhaps even years on a single battery charge, despite being small enough to fit virtually anywhere. An example of the current trend to portability is Bluetooth Low Energy (BLE), described in version 4.0 of the Bluetooth (BT) core specifications [1], which enables communication at significantly lower power consumption than classic BT. Many coming and recently released smartphones and tablets have support for Bluetooth version 4.0, and are thus prepared for communication with BLE (also known as Bluetooth SMART) devices. To enable connectivity with as many different devices as possible we need low cost circuits with very low power consumption. The radio transceiver is a major source of energy consumption in such a device, and keeping it to a minimum is a considerable challenge. To further reduce the size and cost of the device, we want to minimize the external components required, including the SAW- filter at the antenna port. Operating without a SAW-filter in an electrically noisy environment puts high requirements on the receiver out of band linearity. In this work we demonstrate an LNA-less receiver front-end with a power consumption below 550 μW achieving a noise figure of 9.6 dB and an out of band 1 dB compression point better than -15 dBm while operating on a 0.85 V supply.

The remainder of this detailed description is organized as follows. Section II presents the design specifications. Section III describes the architecture, design considerations and circuit implementations for the front-end and its building blocks. Section IV describes the LO generator. Experimental results are discussed in Section V, and a conclusion is given in Section VI.

II. SPECIFICATIONS

To understand the requirements of a Bluetooth Low Energy receiver, we should study the specifications given in [1]. BLE operates in the 2.4 GHz ISM band, with channels spaced 2 MHz apart. The specification defines a reference sensitivity level of -70 dBm with a bit error rate (BER) of 0.1%. The interference performance is specified for a wanted signal 3 dB above this reference sensitivity. BLE uses Gaussian frequency shift keying (GFSK) modulation and a raw data rate of 1Mbps, similar to regular Bluetooth, except for a higher modulation index of 0.5 compared to 0.35 for Bluetooth (BT). Correct reception should be possible with an E _b /N ₀ of 18 dB for regular Bluetooth [2] [3]. BLE is more robust due to its higher modulation index, resulting in a lower Et/No requirement. In [4] an SNR of 14 dB is specified over a 1.25 MHz bandwidth, which translates to an E _b /No of 15 dB. The maximum noise figure to meet the reference sensitivity can then be calculated according to (1) where PSENS is the reference sensitivity (in dBm), and BR is the bit rate.

NF≤ P _SENS - ^ - 10 ^■ log ₁₀ BR - log ₁₀ kT

"0

= -70 - 15 - 60 - (-174) = 29 dB (1) Interference can desensitize the receiver through different mechanisms.

Intermodulation products from receiver non-linearity can appear in channel, large blockers can cause receiver gain compression, and phase noise from the LO generator can appear in-band through reciprocal mixing with an interferer. The maximum allowed NF is quite high, and so we will assume that the sensitivity is dominated by

interference. If the thermal noise is at least 6 dB below the level of the interference induced noise, it will cause a less than 1 dB increase of the total noise.

A. In-Band interference

Bluetooth modulated adjacent channel interferers are specified at 1 , 2 & >3 MHz offset at power levels of -82, -50 & -40 dBm, respectively. Apart from requiring a sufficient compression point, such interferers impose phase noise requirements on the LO-generator. Assuming a rectangular phase noise distribution over the receiver channel, the required phase noise at 1 , 2 & 3 MHz offset is below -61 , -93 & -103 dBc/Hz, respectively. According to the intermodulation specification, the receiver should also tolerate two interferers each with -50 dBm power level, with the wanted signal 6 dB above the reference sensitivity. Including a 1 dB margin to account for the addition of thermal noise, this translates to an IIP ₃ of -32 dBm. B. Out-Of-Band interference

The Out-Of-Band (OOB) interference tolerance is specified for a desired signal in the centre of the band (2440 MHz). The receiver should tolerate a single continuous wave (CW) tone with a strength as shown in table I.

TABLE I: Out-of-band blocker strength

A strong OOB blocker may desensitize the receiver front-end either from forcing it into compression or from reciprocal mixing with the LO phase noise at large frequency offsets. Additionally some of the blocker power may be rectified due to even order distortion, leading to a DC offset. As the specification assumes a CW blocker, the even order distortion will appear purely as DC, and strictly speaking it would be possible to meet the specification by simply removing it, for instance with a digital filter, or by employing the front-end in a low-IF architecture. In practice, however, most interference is in some way modulated, and the distortion products will be spread across a range of frequencies. If we make a rough worst case approximation and assume that the low frequency IM ₂ energy is spread evenly across the entire channel we get an approximate IIP ₂ requirement of 23 dBm for a -30 dBm interferer level. Since only one OOB blocker is specified, it doesn't impose any direct limit on IIP ₃ . If a second blocker is allowed, a worst case scenario may be obtained with two -30 dBm tones. In this case the required IIP ₃ is -3.5 dBm. III. RECEIVER FRONT-END

When implementing a receiver without external SAW-filter, interference over a large bandwidth can enter the receiver with little attenuation. To handle this the receiver must have considerably better out-of- band linearity than otherwise. Since we have a strict power budget, we must use an architecture that limits the signal swing caused by interference. To achieve this as much of the filtering as possible should occur early in the receiver chain, before applying much gain. An attractive receiver architecture that can achieve good rejection of out-of-band interference is to do away with the LNA and instead to place a direct conversion passive mixer directly at the antenna port. The advantage is that the RF signal is converted to baseband almost immediately, before any gain is applied. At baseband it is considerably easier to provide narrow band filtering, and even the first order low-pass function provided by a direct sampling mixer can provide significant attenuation of out-of-band interference. While this configuration generally has too poor noise figure for cellular applications, a short range radio standard such as Bluetooth requires significantly less sensitivity.

When demonstrating an ultra-low power receiver front-end, LO generation circuits including the VCO should be co-integrated to obtain a fair comparison, since a strong external LO could otherwise hide a major source of power consumption. Fig. 1 (Receiver Front-end and LO generator) shows the structure of the implemented receiver front-end. It consists of quadrature passive sampling mixers for zero IF conversion, and baseband amplifiers to provide voltage gain. The mixer input impedance is matched to 50 Ω through a matching network, which also provides about 9 dB voltage gain. The inductor of the matching network is a tightly wound coil with ten turns, using one thin and two thicker metals connected in parallel. The conductor is 2.4 μιη wide, with a spacing of 0.6 μιη. The top aluminum layer is not used since it requires a considerably larger spacing and would not allow for such a compact coil. A metal ground shield in metals 1 & 2 is used below the coil. FastHenry simulation indicates an inductance of 10.6 nH, a self resonance frequency of 6.36 GHz, and a Q of 10.7 at 2.5 GHz. The LO generation circuit consists of a VCO operating at twice the LO frequency and a frequency divider to provide the quadrature LO signals. The LO signals are biased to VDD through high pass filters before being fed to the mixers. An advantageous property of the direct sampling mixer is that since it lacks reverse isolation, the input will be affected by the load impedance. A capacitive load at baseband will thus appear at the input as an impedance with band-pass character around the LO frequency, see Fig. 2 (Mixer input impedance due to frequency translation). This effect can help suppress interference outside the channel of interest already at the mixer input. The filtering properties of this type of mixer have been derived in [5], [6].

Since no gain is provided until after the mixer, the out-of-band interference tolerance will be determined almost entirely be the nonlinearity and filtering properties of the passive mixer. In other words, to minimize sensitivity to out-of-band interference, we should ensure the maximum possible impedance ratio at the mixer input between the in-channel and out-of-band frequencies. The limiting factor here is the resistance of the switches in the conductive state (on-resistance), providing a lower bound to the input impedance (Fig. 2). A. Mixer

A problem of quadrature passive mixers is that if there is overlap in the periods when switches in the I (In phase) and Q (Quadrature phase) branches conduct, a current can pass between the output capacitors of the different outputs, discharging some of the stored charge, increasing the mixer attenuation and noise figure [7]. This is usually solved by providing rectangle wave clock pulses with 25% duty cycle to the switch devices [8]. With four phases there is no instance when the clock pulses overlap.

Providing clock pulses with 25% duty cycle requires, however, a more complex LO generation. Either we have to supply a frequency divider capable of delivering the required clock pulses directly, or we need clock buffers with AND gates or similar.

A different approach to providing non-overlapping conductive periods is to put two switch devices in series in each branch, see Fig. 4a (Single balanced and-function sampling mixer), driven by different phases of the LO, thus incorporating an AND- function in the mixer [9]. Each path conducts in the period when both devices are on, as illustrated in Fig. 4b. All four LO phases are illustrated, together with a line through the center representing the switch threshold. The filled black areas mark the period when both switches conduct. The advantage of this type of mixer is that it can be driven by overlapping LO signals, such as square waves (50% duty cycle) or sine waves. In other words, it can be driven directly from almost any type of quadrature LO source. This is particularly useful when designing a receiver (transceiver) for operation with very low power consumption. Firstly it is easier to produce a symmetric waveform, since it contains less high frequency components. Producing the 25% duty cycle wave for use with a regular mixer requires a circuit with fast time constants to handle the short pulse period.

Secondly, with a severely restricted power budget it is advantageous to concentrate the supply current to as few blocks as possible. This way each block can be as large as possible, minimizing the effects of mismatch, and have as large signals as possible, providing reliable and low noise operation. Parasitic capacitance comprises a significant part of the total load that each block has to drive (including its own), and using more blocks than necessary will create more paths with parasitic capacitance. This could lead to reduced reliability due to unintended coupling paths and/or increased power consumption.

The disadvantage of the mixer in fig. 4 is that since there are two devices in series it has relatively high series resistance, increasing the minimum noise figure as well as degrading the input filtering properties. If we are to manage without an LNA with this type of mixer, we should find ways to reduce the series resistance. Fig. 5 illustrates optimizing an and-function mixer. The original AND-type mixer shown in Fig. 5a is organized so that the LO signals in each path occur in the same order, to ensure symmetry. If we for a moment ignore symmetry and change the order of the LO- signals on one side (Fig. 5b), we see that there are now two pairs of devices closest to the RF port that are clocked by the same phases of the LO. By merging these (Fig. 5c) the switch resistance has been reduced by 25% without any change in the total size of the mixer. The problem is that the mixer is now asymmetrical. This is especially detrimental in a zero-IF architecture, where asymmetry will lead to I/Q imbalance, DC- offsets and increased LO leakage through the RF port. To solve this we split the mixer into two halves clocked in opposite orders (Fig. 5d). For example there is a path on one side clocked from input to output with LOi ₊ to LOQ ₊ . In the other mixer half there is a corresponding path clocked in the reverse order (LOQ ₊ to LOi ₊ ). Both paths conduct simultaneously, and now all paths are fully symmetrical.

A second technique we propose to improve the operation of the AND-type mixer involves placing capacitors (Cp) across the intermediate nodes of the mixer, see Fig. 6 (Modeling and-mixer with extra capacitors, Fig. 6d). These capacitors are small compared to C _L , since the mixer is sensitive to parasitic capacitance to ground at these nodes. Since they are small they mainly effect the mixers at higher IF frequencies, such as out of band. In the example presented herein, a suitable value of Cp may be 3.5 pF.

To understand the effect of the capacitors, consider Fig. 6a,b, which show part of the mixer coupling to one of the outputs. In Fig. 6a we see the time instant when the mixer is conducting through the normal path (LOi ₊ & LOQ ₊ ), and in Fig. 6b we see the next time instant when the LOi ₊ switch has opened, and where instead we have a path to the load through LOi_, LOQ ₊ and the capacitor Cp. These operations occur 90° apart relative to the LO, and it is observed that their charge contributions to C _L are largely independent. In Fig. 6c a simple model of the mixer is shown, including the effect of switch resistances (Rsw)- In Fig. 6d the capacitors Cp are included in the schematic, and as their effect is largely independent from the usual mixer operation, they are modeled by a separate path with a mixer driven by an LO signal shifted by 90°. We can see that Cp has little or no effect close to the LO frequency. Out-of-band, however, the second path substantially halves the effective switch resistances, improving the suppression of interference at the mixer input by up to 6dB.

The extra capacitors have the additional advantage of suppressing second harmonic downconversion. Signals at twice the LO frequency will in a regular single balanced mixer be converted to a common-mode signal at the output. This could create unwanted intermodulation products, or leak directly into the signal path through finite common-mode suppression in the baseband amplifiers. To understand how the second harmonic signal is suppressed, consider Fig. 7 (Suppression of second harmonic downconversion). For each period of the LO the RF port is exited with two periods. We will be looking at the four mixer states that occur for each LO period. For illustration we have assumed here that the second harmonic starts by going high during the first state. We see that a charge is then pushed into one of the load capacitors (C _L ). In state two a path conducts across C _P while the RF port is low, discharging C _L . In state three the other load capacitor is charged. In state four it is discharged through Cp. This will also remove the charge stored in Cp during state two, since the current through the capacitor is in the opposite direction. From this it is clear that Cp will prevent charging of CL, and no voltage will then build up at the main output.

Fig. 8 (Simulated mixer input impedance vs. frequency with & without Cp) shows the input impedance of a mixer with Rs = 1 kΩ, CL = 25 pF and Rsw of 100 Ω with and without the capacitors Cp. We see that without Cp the input impedance is high around the second harmonic, since the energy is not dissipated. When adding Cp, we can observe that not only is the input impedance halved for frequencies far from f _L o, but the peak at 2 · f _L o is now gone.

Combining both these techniques we arrive at the implemented mixer structure shown in Fig. 3 (Mixer schematic). B. Baseband Amplifiers

With no LNA at RF, the main noise contributors are the mixers and baseband amplifiers. To keep the noise figure as low as possible the baseband amplifier, see Fig. 9 (Schematic of the baseband amplifier), input devices should have as high

transconductance as possible, which is achieved with a single stage design. By making the devices 3 μιη long the complementary devices achieve high output impedance, resulting in a voltage gain of over 26 dB. Large area devices also keep the flicker noise low, and ensure good matching. The feedback resistors Rp are primarily for biasing purposes, and are made large enough to have only a minor effect on the amplifier gain. The common mode feedback (CMFB) has 36 dB loop gain at DC, and for stability it is compensated with a resistor and capacitor placed in the current mirror.

IV. LO GENERATION

The LO signal generation is the dominant source of power consumption in this circuit, having to drive the relatively large passive mixers. A low quadrature error and good LO symmetry is advantageous to ensure maximum performance. This is difficult to achieve in low power design, since the devices used are small, making them susceptible to mismatch as well as parasitic capacitances that risk forming unintended coupling paths.

There exist a couple of different approaches to generating a quadrature LO signal. The most common methods are by means of a quadrature oscillator, or with a frequency divider operating from a single VCO at twice the frequency. Initially the quadrature VCO approach seems most attractive. All output nodes are connected to a resonance circuit, which is generally more power efficient, since energy is kept in storage and not immediately dissipated. The resonant loads additionally mean that the LO generation can be operated on a very low supply voltage. There are two problems with this approach, however, which favor the alternative solution with a frequency divider. Firstly we are striving for a cheap and thus small design. This effectively means that we try to avoid the use of inductors as far as possible, since they scale poorly with advancing technology nodes. A quadrature VCO requires two VCO cores with at least one inductor each. The divider based solution only requires a single VCO core, and this operates at twice the frequency, further reducing the required area. Secondly isolation should be provided between VCO and RF circuits, especially in the case of a direct conversion receiver. Without sufficient isolation to the RF path the VCO is potentially susceptible to injection locking from strong interferers. As it turns out, simulations indicate that providing the isolation by inductorless LO buffers strong enough to drive the passive mixers in the receiver, require a similar amount of power as a frequency divider with the same driving strength.

For reasons of simplicity and minimizing the number of external components, we wish to use a single supply voltage for the entire circuit. A largely inductorless low power circuit will make extensive use of complementary devices (NMOS & PMOS). To make the RF parts operate well at the frequencies used in this design we require a supply voltage of at least 0.8 V. A higher supply voltage has the advantage that we can handle larger voltage swing, thus making it easier to provide good linearity. The performance can be further helped by the inherent symmetry of a complementary design. The LO generator, consisting of oscillator and divider is shown in Fig. 10 (LO generator circuit, (a) VCO (b) Divider). It uses an architecture presented in [10]. A. VCO

The lower limit for the power consumption of the VCO is determined by the point where the oscillator loop gain drops below unity, and where oscillation cannot be maintained. The loop gain, as we see from (2)

^start-up ⁼ 9m ^' R ' ⁼ 9m ^{' ω} 0 ^' LQ > 1 (2) is given by the transconductance of the devices in the VCO core, as well as the load impedance presented by the resonant tank. Additionally, the output swing is determined by the bias current and load impedance, and it has to be sufficient to reliably drive the frequency divider. We see that in order to minimize the power consumption we need an inductor with a high LQ product. It should also preferably have a high Q value to minimize the phase noise.

The inductor is a custom designed differential coil with five turns in one thin metal, two thick metals, and the top aluminum metal layer connected in parallel. The conductor has a width of 4 μιη and the spacing between turns is 3 μιη. It has a ground shield in interleaved strips of metals 1 & 2, patterned according to the simple ground shield of [11]. Due to an initial modeling error of the VCO inductor, the operating frequency is slightly higher than intended. Since then the inductor has been remodeled with a more accurate representation, verified by simulations in FastHenry and

Momentum. The new model also corresponds well with measured receiver performance. It has an estimated inductance of 3.7 nH, a Q value of 17.9 at 5 GHz, and a self resonance frequency of 10.5 GHz.

A possible strategy for maximizing the VCO performance with a low power consumption is to lower the supply and increase the current draw. This will not only improve the transconductance, but also increase the output swing to supply voltage ratio, resulting in improved efficiency. We, however, prefer operating the front-end on a single supply voltage. To achieve this and still maintain the same low power

consumption we need to employ some sort of current reuse technique to maximize the transconductance for a given supply current, and to improve the efficiency. Existing techniques include the complementary push-pull configuration [12] and the technique in [13], where a single current flows through the devices on both sides of the inductor. We have chosen a combination of both these techniques, to achieve an additional level of current reuse (Fig. lb). In this solution the same supply current passes through all devices of the VCO, giving high loop gain for minimal current consumption. The effective supply voltage for each NMOS, PMOS inverter is less than half of the total supply voltage, allowing high efficiency at reduced output swing. An additional advantage is that since both n-type and p-type devices are connected to both sides of the resonant tank, it can achieve a higher degree of symmetry than the single stacked solution. The symmetry is improved further with a triple-well implementation, isolating the bulk of the NMOS devices from the substrate.

Another way of arriving at the proposed solution is to start with a simple push- pull oscillator, see Fig. 11 (Deriving the VCO structure, Fig. 11a). We then separate the supplies for each side, so that one pair is fed from Vdd to Vdd/2, while the other side is fed from Vdd/2 to ground (Fig. 1 lb). In essence we have placed both pairs in series with Vdd/2 as an intermediate node. By now decoupling the intermediate node and removing some unnecessary components, we arrive at the final solution (Fig. 11c). The VCO uses accumulation mode varactors as they have suitable tuning characteristics with one terminal connected to V _DD /2, with VSG in the range ±V _DD /2 [14].

B. Divider

There are many different frequency divider topologies, usually based on either injection locked oscillators [15] or static dividers using digital logic [16]. The digital approach is natural when aiming for the smallest possible area, since no inductors are required. Since a digital frequency divider has to handle quickly toggling signals they are often implemented with current mode logic (CML) which can achieve high speed. This is, however, not the most power efficient, since CML draws a constant current and uses resistive loads. Our divider is based on a common approach with a master-slave topology. This is typically implemented in CML, but we have instead made it fully complementary (Fig. 10b), making it behave more like regular CMOS logic. It thus only draws current during transitions, and nearly all current flows to and from the load. With the complementary devices working in tandem, we also get more transconductance for a given current consumption. Additionally, with devices that both push upwards and pull downwards, we can achieve high output swing with a limited supply voltage. In fact, simulations indicate that in our case the output can reach to within 100 mV of each rail in normal operation.

A divider of this type is most sensitive to the input signal at a certain frequency, depending on design and bias points. An important design choice is the ratio between the devices that couple between the two halves of the divider (M _D ) and the latches (M _L ). If the latches are made too small they will not store enough energy, while if they are made too large, too much energy is required to set the state of the latches. It has been found in similar CML-based dividers that there is an optimum W _L W _D device ratio close to 0.5, where the divider is sensitive to the broadest possible range of input frequencies [17]. Fig. 12 (Simulated maximum & minimum divider input frequency vs. W _L W _D ratio for a VCO amplitude of 190 mV (one side). The dashed line indicates the geometric mean.) shows simulated maximum and minimum frequencies where the divider can operate for an input amplitude of 190 mV, with varying ratio device width ratios (W _L /W _D ). The dashed center line shows the geometric mean of maximum and minimum frequencies. It can be seen that the largest frequency range is achieved with a W _L /W _D ratio of 0.46, but a ratio of 0.5 was chosen to simplify the layout, and to provide some margin to the sharp roll-off that occurs for smaller than optimum devices.

A fully complementary implementation has a further and not immediately obvious advantage. Since each section of the divider is driven roughly equally by both the positive and negative signals from the VCO, asymmetry in the VCO signal is suppressed. This feature is especially useful in this design, since the VCO used will never be completely symmetric. To better understand how input signal asymmetry can be suppressed we should consider how the VCO signal is injected into the divider. As the NMOS devices pull current, the PMOS devices push, resulting in a signal injected with the opposite sign. In Fig. 10b we see that Vyco- and Vyco+ work in tandem (Vy co+ ⁼ -Vyco- ^→ Ivco+ ~ Ivco- driving the same parts of the divider. Basically the PMOS devices are supplying an inverted copy of the currents injected by the NMOS devices. If the inverted currents are equal, any difference in Vyco- compared to Vyco+ will affect both sides of the divider the same, and will thus not contribute any quadrature error. Fig. 13 is an illustration of VCO imbalance propagation through a

complementary divider. The solid lines indicate the contribution to I and Q LO-signals through NMOS devices, and the dashed lines contributions through the PMOS devices

We have seen that if the injection paths are perfectly matched they can completely remove the imbalance coming from the VCO. The remaining error will thus be due to imbalance between the NMOS and PMOS paths. In an NMOS only divider Vvco+ will contribute mainly to two of the output phases, while Vyco- contributes to the remaining two. In fig. 13a output signals are represented by two vectors with amplitude 1. One vector is the inphase output, controlled primarily by one of the input signals, the other is the quadrature phase output, controlled primarily by the other input signal. Let us assume that there is a VCO imbalance resulting in a quadrature error in phase and amplitude that we represent with the vector ε placed on one of the quadrature outputs. Now let us assume that the VCO signals also contribute to the outputs through the PMOS paths (dashed lines) by a factor a (Fig. 13b). Since the quadrature error emanates from one of the input signals, it will now be present on both the outputs, scaled by a. In the case a = 1 the paths are perfectly matched and we expect the error, ε, to be fully suppressed, since it contributes exactly equally to both I and Q outputs. Investigating the difference in the in-phase and quadrature vectors, we find that the residual quadrature error Δε _90° = ε · (1 - a). The injected signals will be increased due to the extra injection paths by a factor 1 + a, and so the relative quadrature error will be ε γ—--

(l+a) shown in Fig. 14 (Suppression

of VCO imbalance vs. PMOS/NMOS injection ratio). We can see that when the PMOS device paths are matched to within ±50%, the VCO imbalance is suppressed by more than 66%. With high suppression the quadrature error will probably be dominated by mismatch in the divider itself. When a = 0 or goes to infinity, there is no suppression of VCO error. This is expected, since a = 0 indicates that there is no PMOS path, and when a =∞ there is no NMOS. V. MEASUREMENT RESULTS

The receiver front-end was manufactured in a standard 65 nm CMOS process with eight metal layers, MIM capacitors and triple-well. All pins are attached to ESD protection diodes. Fig. 15 (Die Photo of the front-end with a visible area of

0.73 x0.4mm) shows the die photo of the receiver, which occupies an area of

0.73mmx0.4mm including pads. The active area (dashed) is just below 0.15mm ² including on-chip decoupling. The circuit was wire bonded directly to a two-layer PCB. The baseband outputs were buffered by AD812 operational amplifiers configured as voltage followers, and then converted to a single ended output with AD830 video difference amplifiers. The input matching is achieved entirely on chip, i.e. no matching components were used on the PCB. Most measurements were performed on three samples.

The VCO, divider and baseband amplifiers consume below 95 μW, 355 μW and 100 μW, respectively, resulting in a total power consumption less than 550 μW.

Fig. 16 (Operating frequency vs. tuning voltage) shows the tuning

characteristic for all three samples, measured using a signal generator to produce an input signal and a spectrum analyzer to study the resulting output. As previously explained the circuit is tuned high, and operates above the 2.4 GHz ISM-band. It should, however, be easy to lower the VCO frequency in an updated design. Lowering the operating frequency should also reduce the power requirements of the frequency divider. The circuit currently operates from below 2.5 GHz to about 2.7 GHz.

The input reflection coefficient was measured with an R&S ZVC vector network analyzer. In Fig. 17 (Input matching measurements), Fig. 17a (Si i for different tuning frequencies) shows the behavior of Sn for different varactor tuning voltages of one sample. In Fig. 17b (In-channel input reflection coefficient vs. frequency) only the in-channel (close to the LO frequency) reflection coefficient has been plotted versus operating frequency. This indicates how well matched the receiver is for wanted signals. We can see that the receiver front-end is well matched in the lower frequency range close to the intended 2.4 GHz ISM-band. Even though the circuit is operating at higher frequency than intended, Sn is still better than -10 dB over most of the tuning range. The noise figure and gain were measured using an R&S FSEB spectrum analyzer. Measurements of all three samples operating in the middle of their tuning range (Vtune = 580 mV) are shown in Fig. 18 (Noise figure and gain vs. output frequency measurements (solid) and simulations (dashed)). The conversion gain reaches about 41 dB with a -3 dB bandwidth of 1.15 MHz, while the noise figure is below 9.6 dB at its best. The noise figure is below 10 dB between 150 kHz and 1.5 MHz, and at 30 kHz it has increased by 3 dB. Simulations indicate that the low frequency noise mainly comes from amplitude noise of the frequency divider. The dashed lines show the gain and noise figure predicted by simulations.

The linearity measurements were taken with the receiver front-end operating in the middle of the tuning range, while sweeping the frequency of the interfering signals. The compression and two-tone measurements were performed with a spectrum analyzer and one or two signal generators, all automated through GPIB commands issued from a Matlab script. A first impression of the large signal handling is provided by the compression point. A single tone was thus applied to the RF input at increasing offset frequencies, and at each frequency the power was swept. The resulting 1 dB

compression point for all three samples is shown in Fig. 19 (ldB compression point vs. offset frequency). All curves are for the upper sideband, but the lower sideband behaves in a near identical way. We can see that the input referred 1 dB compression point is about -41 dBm in-channel and increases with offset frequency. At 3 MHz offset it is better than -31 dBm, and at 10MHz it saturates at about -15 dBm. When the gain is high the compression point is limited by the voltage swing at the output. The dotted line shows the response predicted by the front-end conversion gain. Eventually, as the conversion gain drops, it is instead limited by the mixer, causing the curve to saturate.

The third order intercept measurements were performed by applying two tones at the RF port with frequencies such that a third order intermodulation product appears at a set frequency in-channel. In this case the frequency of the down converted intermodulation product ¾ was kept constant at 250 kHz, while the two interfering tones were placed such that f _L o + ¾F = 2 · fi _nner - f _ou ter while varying fi _ll er & fouter relative to f _L o At each point the input power was swept, and the measurements closest to forming a third order slope extrapolated. The extrapolation was compared to the gain in- channel to get a measurement of the effective intercept point. Fig. 20 (IIP ₃ vs. offset frequency) shows the effective input referred IP ₃ for all samples versus the frequency of the outer tone, f _ou ter- Though the tones are attenuated by different amounts at the output of the front-end, the behavior is very similar to that of the compression point. We can observe that IIP ₃ is about -30 dBm in channel, and increases while moving further from the operating frequency, until it saturates at 10 MHz at about -3 dBm. The difference between the 1 dB compression point and IIP ₃ is close to the often observed 10 dB.

The quadrature error was measured by applying a tone at the RF port at a small offset compared to the LO, resulting in an IF frequency of 200 kHz. The I and Q baseband outputs were recorded with a Tektronix TDS 7404 digital oscilloscope, and FFT's of the signals were then compared to each other in Matlab. Figure 21 shows quadrature error measurements. The resulting quadrature phase error (Fig. 21a) is below 0.6° for all three samples over the entire tuning range, while the amplitude error (Fig. 21b) stays below 3%. This corresponds to an image rejection ratio better than 36 dB.

Like IIP ₃ the second order intercept point was measured at varying offsets from the carrier frequency. The two tones were placed at 100 kHz above and below the reported offset frequency, placing the measured IM ₂ product at an IF frequency of 200 kHz. A power sweep was made for each offset frequency, and the region close to a second order slope was isolated. Fig. 22 (IIP ₂ vs. offset frequency; dotted lines show response predicted from amplifier gain & (5)) shows the second order intercept point for all three samples for varying offset frequency. Close to the carrier frequency IIP ₂ is better than 0 dBm, improving rapidly until saturating at about 5 MHz offset with all measurements better than 29.5 dBm.

Close to the LO frequency the gain is high and the second order distortion is dominated by the baseband amplifiers. Further out, where the conversion gain is low, it is instead dominated by the mixers, and at high offsets the mixer linearity levels out.

To understand why this happens consider the output of the mixer for large offset frequencies as a low pass RC filter with a non-linear resistance. If we excite the filter with a voltage Vs, a current ¾ will flow through R and C according to (3). At low output frequencies the current flowing will be very small, as the capacitors dominate the impedance. As the frequency increases the current will saturate to a value set by the resistance. Second order non linearity in the resistance will create a voltage V _D proportional to Is squared (4). Since the IM ₂ product of interest appears in-channel at fixed frequency, the RC filter will have little further influence. Thus, the out of band IIP ₂ due to the mixer output will act approximately as (5), starting high and tapering off to a constant value. The mixer IIP ₂ will also be depend on matching, since in a mixer free from mismatch the IM ₂ generated at the output will be a pure common mode signal.

I _S = V _S - ^j °" ^FC (3)

l )] _F RC '

l+ja> _IF RC ²

l ^l 2,OOB « _j(i)ipC ) Apart from the effects described above there are complex interactions between different distortion products. Since the sign of the second order product is set by mismatch and hence random, there may be points where IM ₂ products from the mixer and amplifier happen to cancel, creating random peaks in the IIP ₂ response.

To judge the tolerance to the strongest out of band blockers, noise figure measurements were made while applying a tone 400 MHz below the operating frequency of 2.58 GHz. To make sure that wideband phase noise from the signal generator wouldn't dominate the measurement, it was filtered through a custom made filter, providing 26 dB and 9.5 dB suppression at the LO frequency and the third harmonic of the LO, respectively. The noise figure was measured at an IF frequency of 300 kHz with a resolution bandwidth of 30 kHz. With a narrow measurement bandwidth and a DC-blocker to protect the spectrum analyzer the result is not influenced by DC signals, but does tell us how the receiver is influenced by gain compression and wideband phase noise. Fig. 23 (Measured noise figure with out of band CW blocker at 400MHz below operating frequency) shows the resulting noise figure for varying blocker strength. The receiver is desensitized by less than 1 dB at -23.5 dBm input signal power, and does not reach the maximum tolerable noise figure even at the highest measured blocker level of -6 dBm, significantly greater than the -30 dBm requirement. With a blocker of -10 dBm the noise figure is below 18 dB, which satisfies the largest out of band blocker requirements of even the regular Bluetooth specifications. The phase noise was measured on a downconverted tone using a spectrum analyzer. At 1 MHz offset it was found to be below -105.7 dBc/Hz when tuned to 2.6 GHz, and better than -107.3 dBc/Hz at the edges of the tuning range. The measured LO leakage to the RF port was below -69 dBm for all samples.

VI. CONCLUSIONS

An ultra-low power receiver front-end and LO generator has been

demonstrated in 65 nm CMOS. Operating at 2.6 GHz from a 0.85V supply it consumes below 550 μW. Using an LNA-less architecture and an efficient passive mixer structure it achieves good rejection of out-of-band interference while also rejecting interference at the even harmonic of the LO, despite using a single-ended input. A complementary divider structure offers an LO with low quadrature error despite an asymmetric oscillator structure. Using only two inductors, the circuit occupies an area of just 0.15mm ² excluding pads. Retuned to operate in the 2.4 GHz ISM band, it has sufficient performance for a Bluetooth Low Energy receiver even without a SAW- filter. The front-end performance is summarized and compared to some recently published works in table II. Works with integrated LO-generation have been primarily selected, and the active areas estimated from chip photos. The circuit performs favorably on primarily linearity, active area and power consumption.

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