FIELD OF THE INVENTION

The present disclosure relates to video compression and more particularly to the quantization step of the video compression scheme.

BACKGROUND OF THE INVENTION

Many attempts have been made to improve the coding efficiency of block-based codecs. The FIEVC (High Efficiency Video Coding, FI.265) specification allows the use of quantization matrices in the dequantization process, where coded block frequency- transformed coefficients are scaled by the a quantization step and further scaled by a quantization matrix. Quantization matrix information is conveyed from an encoder to a decoder through syntax.

SUMMARY OF THE INVENTION

These and other drawbacks and disadvantages of the prior art are addressed by the present described embodiments, which are directed to a method and apparatus to manage a trade-off between the coding efficiency provided by quantization matrices and encoding and decoding complexity.

According to an aspect of the described embodiments, there is provided a method. The method comprises steps for encoding a video block by encoding color components of the video block separately using separate quantization matrices; and including syntax in a bitstream of the encoded video indicating a quantization matrix used for a color component of the video block and for its encoding.

According to another aspect of the described embodiments, there is provided a second method. The method comprises steps for parsing a bitstream for syntax indicative of a quantization matrix used for a component of a video block; and, decoding the component of the video block using a quantization matrix based on said syntax.

According to another aspect of the described embodiments, there is provided an apparatus. The apparatus comprises a memory and a processor. The processor can be configured to encode or decode a portion of a video signal by any of the above mentioned methods.

According to another general aspect of at least one embodiment, there is provided a device comprising an apparatus according to any of the decoding embodiments; and at least one of (i) an antenna configured to receive a signal, the signal including the video block, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the video block, or (iii) a display configured to display an output representative of a video block.

According to another general aspect of at least one embodiment, there is provided a non-transitory computer readable medium containing data content generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, there is provided a signal comprising video data generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, a bitstream is formatted to include data content generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, there is provided a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out any of the described decoding embodiments or variants.

These and other aspects, features and advantages of the present principles will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a generic video compression scheme.

Figure 2 illustrates a generic video decompression scheme.

Figure 3 illustrates one embodiment of an apparatus for encoding or decoding video using quantization matrices under the general described aspects. Figure 4 illustrates one embodiment of a method for encoding video using at least one illumination compensation flag.

Figure 5 illustrates one embodiment of a method for decoding video using at least one illumination compensation flag.

Figure 6 a processor based system for encoding/decoding.

DETAILED DESCRIPTION

The domain of the embodiments described herein is video compression, more specifically the quantization step of the video compression scheme.

Dequantization in HEVC, with matrix as scale factor

The HEVC (High Efficiency Video Coding, H.265) specification allows the use of quantization matrices in the dequantization process, where coded block frequency- transformed coefficients are scaled by the current quantization step and further scaled by a quantization matrix (QM) as follows:

d[ x ][ y ] = Clip3( coeffMin, coeffMax, ( ( TransCoeffLevel[ xTbY ][ yTbY ][ cldx ][ x ][ y ] ^* m[ x ][ y ] ^* levelScale[ qP%6 ] « (qP / 6 ) ) + ( 1 « ( bdShift - 1 ) ) ) » bdShift )

Where:

• TransCoeffLevel[... ] are the transformed coefficients absolute values for the

current block identified by its spatial coordinates xTbY, yTbY and its component index cldx.

• x and y are the horizontal/vertical frequency indices.

• qP is the current quantization parameter.

• the multiplication by levelScale[qP%6] and left shift by (qP/6) is the equivalent of the multiplication by quantization step qStep = ( levelScale[qP%6] << (qP/6) )

• m[... ][... ] is the two-dimensional quantization matrix

• bdShift is an additional scaling factor to account for image sample bit depth. The term (1 « (bdShift - 1 )) serves the purpose of rounding to the nearest integer.

• d[... ] are the resulting dequantized transformed coefficients absolute values Quantization matrix signaling in HEVC

The syntax used by HEVC to transmit quantization matrices is the following:

It can be noted that

• A different matrix is specified for each transform size (sizeld)

• For a given transform size, 6 matrices are specified, for intra/inter coding and Y/Cb/Cr components

• A matrix can be either o Copied from a previously transmitted matrix of the same size, if scaling_list_pred_mode_flag is zero (the reference matrixld is obtained as matrixld - scaling_list_pred_matrix_id_delta)

o Copied from default values specified in the standard (if both scaling_list_pred_mode_flag and scaling_list_pred_matrix_id_delta are zero)

o Fully specified in DPCM coding mode, using exp-Golomb entropy coding, in up-right diagonal scanning order.

• For block sizes greater than 8x8, only 8x8 coefficients are transmitted for signaling the quantization matrix in order to save coded bits. Coefficients are then interpolated using zero-hold (= repetition), except for a DC coefficient which is transmitted explicitly.

Status of WC

The use of quantization matrices similar to FIEVC has been adopted in WC (Versatile Video Coding) draft 5 based on contribution JVET-N0847. Compared to FIEVC, WC needs more quantization matrices due to a higher number of block sizes.

In JVET-N0847, as in FIEVC, a QM is identified by two parameters, matrixld and sizeld. This is illustrated in the following two tables.

Table 1 : Block size identifier (JVET-N0847)

Table 2: QM type identifier (JVET-N0847)

An alternate QM identification with a single matrixld parameter has been proposed by JVET_O0223 as illustrated in the following table:

Table 3: unified matrixld (JVET_O0223)

Separate color planes

In both HEVC and WC, it is possible to encode a picture in separate color plane mode. This means that separate encoding can be used for each color component, each one being coded as a monochrome slice.

The VVC draft 5.0 makes use of two syntax elements, namely chroma_format_idc and separate_colour_plane_flag which are used to define picture format, as explained in the section 6.2 and table 6-1 of VVC draft 5.0, as reproduced below:

Table 6-1 - SubWidthC and SubHeightC values derived from chroma_format_idc and separate_colour_plane_flag

In monochrome sampling there is only one sample array, which is nominally considered the luma array.

In 4:2:0 sampling, each of the two chroma arrays has half the height and half the width of the luma array.

In 4:2:2 sampling, each of the two chroma arrays has the same height and half the width of the luma array.

In 4:4:4 sampling, depending on the value of separate_colour_plane_flag, the following applies:

- If separate_colour_plane_flag is equal to 0, each of the two chroma arrays has the same height and width as the luma array.

- Otherwise (separate_colour_plane_flag is equal to 1 ), the three colour planes are separately processed as monochrome sampled pictures.

In SPS semantics, the WC draft 5 defines a variable ChromaArrayType, which is based on chroma_format_idc, but forced to zero in separate color plane mode. This variable is widely used in lower-level syntax elements instead of chroma_format_idc to select the picture color format, so that in separate color plane mode, decoding process for each color plane is identical to monochrome (or luma).

During picture decoding, the current color component is identified by cldx variable. When not in separate color plane mode, the cldx variable is set successively to 0, 1 , 2 to decode the respective color components, when relevant. When in separate color plane mode, cldx is always zero, thus the same QMs are selected for all color components. Indeed, for the selection of QM for a given transform block, the matrixld specification refers to cldx:

• see table 2 above for JVET-N0847

• JVET-NO0223 make use of cldx within“QM derivation process” to select a QM, by using the following formula (see matrixTypeld): matrixld = 6 ^* sizeld + matrixTypeld (xxx-1 ) with subWidth = (cldx > 0) ? SubWidthC : 1 ,

subHeight = (cldx > 0) ? SubHeightC : 1 ,

sizeld = 6 - max( log2( blkWidth ^* subWidth ), log2( blkHeight ^* subHeight ) ), and

matrixTypeld = ( 2 ^* cldx + ( predMode = = MODEJNTER 7 1 : 0 ) )

This variable cldx is actually an input parameter of the“QM derivation process”, but is set identical to the global cldx by the parent process (“Scaling process for transform coefficients”).

The described embodiments propose to change the QM selection for separate color plane mode:

• Select QM for the actual color component instead of “luma” one, even when in separate color plane mode, i.e. make use of colour_plane_id (present in slice segment header in HEVC, but not yet present in in WC syntax, though used in semantics)

QM selection in separate color plane mode is one problem addressed herein.

For QM selection in separate color plane mode, HEVC, JVET-N0847 and JVET- 00223 use the QMs signaled for luma for all color components, though transmitting separate QMs for each color component in scaling_list_data syntax, possibly wasting bits by transmitting useless QMs, and lacking flexibility by using the same QMs for all color components.

To select separate QMs for separate components when in separate color plane mode, it is proposed to use colour_plane_id instead of cldx.

Note: in addition to what is described in the two following subsections, text in“Decoding process for a coded picture” stating that decoding process for each color plane consist of operations“identical to that of monochrome pictures” should be altered to reflect the exception of quantization matrices, e.g.:

“NOTE - The variable ChromaArrayType is derived as equal to 0 when separate_colour_plane_flag is equal to 1 and chroma_format_idc is equal to 3. In the decoding process, the value of this variable is evaluated resulting in operations essentially identical to that of monochrome pictures (when chroma_format_idc is equal to 0).”

Or

“NOTE - The variable ChromaArrayType is derived as equal to 0 when separate_colour_plane_flag is equal to 1 and chroma_format_idc is equal to 3. In the decoding process, the value of this variable is evaluated resulting in operations identical to that of monochrome pictures (when chroma_format_idc is equal to 0), except for the selection of scaling matrices.”

Example changes to JVET_O0223

In draft text proposed by JVET_O0223, the color component index provided to the QM derivation process by“Scaling process for transform coefficients” is modified as follows:

- Otherwise, m is the output of the derivation process for scaling matrix as specified in JVET_O0223, invoked with the prediction mode CuPredMode[ xTbY ][ yTbY ], the colour component variable colour_plane_id when separate_colour_plane_flag is 1 or cldx otherwise, the block width nTbW and the block height nTbH as inputs.

Example changes to JVET_N0847

“cldx” is removed from matrixld specification table (see Table 2 above), leaving just “Colour component”, and text is added to explain that“colour component” is

• colour_plane_id when separate_colour_plane_flag is true

• cldx otherwise

One embodiment of a method 400 under the general aspects described here is shown in Figure 4. The method commences at start block 401 and control proceeds to block 410 for encoding a video block by encoding color components of the video block separately using separate quantization matrices. Control proceeds from block 410 to block 420 for including syntax in a bitstream of the encoded video indicating a quantization matrix used for a color component of the video block and for its encoding.

One embodiment of a method 500 under the general aspects described here is shown in Figure 5. The method commences at start block 501 and control proceeds to block 510 for parsing a bitstream for syntax indicative of a quantization matrix used for a component of a video block. Control proceeds from block 510 to block 520 for decoding the component of the video block using a quantization matrix based on said syntax.

Figure 6 shows one embodiment of an apparatus 600 for compressing, encoding or decoding video using coding or decoding tools. The apparatus comprises Processor 610 and can be interconnected to a memory 620 through at least one port. Both Processor 610 and memory 620 can also have one or more additional interconnections to external connections.

Processor 610 is also configured to either insert or receive information in a bitstream and, either compressing, encoding or decoding using various coding tools.

The embodiments described here include a variety of aspects, including tools, features, embodiments, models, approaches, etc. Many of these aspects are described with specificity and, at least to show the individual characteristics, are often described in a manner that may sound limiting. Flowever, this is for purposes of clarity in description, and does not limit the application or scope of those aspects. Indeed, all of the different aspects can be combined and interchanged to provide further aspects. Moreover, the aspects can be combined and interchanged with aspects described in earlier filings as well.

The aspects described and contemplated in this application can be implemented in many different forms. Figures 1 , 2, and 3 provide some embodiments, but other embodiments are contemplated and the discussion of Figures 1 , 2, and 3 does not limit the breadth of the implementations. At least one of the aspects generally relates to video encoding and decoding, and at least one other aspect generally relates to transmitting a bitstream generated or encoded. These and other aspects can be implemented as a method, an apparatus, a computer readable storage medium having stored thereon instructions for encoding or decoding video data according to any of the methods described, and/or a computer readable storage medium having stored thereon a bitstream generated according to any of the methods described.

In the present application, the terms“reconstructed” and“decoded” may be used interchangeably, the terms“pixel” and“sample” may be used interchangeably, the terms “image,”“picture” and“frame” may be used interchangeably. Usually, but not necessarily, the term “reconstructed” is used at the encoder side while“decoded” is used at the decoder side.

Various methods are described herein, and each of the methods comprises one or more steps or actions for achieving the described method. Unless a specific order of steps or actions is required for proper operation of the method, the order and/or use of specific steps and/or actions may be modified or combined.

Various methods and other aspects described in this application can be used to modify modules, for example, the intra prediction, entropy coding, and/or decoding modules (160, 360, 145, 330), of a video encoder 100 and decoder 200 as shown in Figure 1 and Figure 2. Moreover, the present aspects are not limited to WC or FIEVC, and can be applied, for example, to other standards and recommendations, whether pre existing or future-developed, and extensions of any such standards and recommendations (including VVC and FIEVC). Unless indicated otherwise, or technically precluded, the aspects described in this application can be used individually or in combination.

Various numeric values are used in the present application. The specific values are for example purposes and the aspects described are not limited to these specific values.

Figure 1 illustrates an encoder 100. Variations of this encoder 100 are contemplated, but the encoder 100 is described below for purposes of clarity without describing all expected variations.

Before being encoded, the video sequence may go through pre-encoding processing (101 ), for example, applying a color transform to the input color picture (e.g., conversion from RGB 4:4:4 to YCbCr 4:2:0), or performing a remapping of the input picture components in order to get a signal distribution more resilient to compression (for instance using a histogram equalization of one of the color components). Metadata can be associated with the pre-processing and attached to the bitstream.

In the encoder 100, a picture is encoded by the encoder elements as described below. The picture to be encoded is partitioned (102) and processed in units of, for example, Cus. Each unit is encoded using, for example, either an intra or inter mode. When a unit is encoded in an intra mode, it performs intra prediction (160). In an inter mode, motion estimation (175) and compensation (170) are performed. The encoder decides (105) which one of the intra mode or inter mode to use for encoding the unit, and indicates the intra/inter decision by, for example, a prediction mode flag. Prediction residuals are calculated, for example, by subtracting (1 10) the predicted block from the original image block.

The prediction residuals are then transformed (125) and quantized (130). The quantized transform coefficients, as well as motion vectors and other syntax elements, are entropy coded (145) to output a bitstream. The encoder can skip the transform and apply quantization directly to the non-transform ed residual signal. The encoder can bypass both transform and quantization, i.e., the residual is coded directly without the application of the transform or quantization processes.

The encoder decodes an encoded block to provide a reference for further predictions. The quantized transform coefficients are de-quantized (140) and inverse transformed (150) to decode prediction residuals. Combining (155) the decoded prediction residuals and the predicted block, an image block is reconstructed. In-loop filters (165) are applied to the reconstructed picture to perform, for example, deblocking/SAO (Sample Adaptive Offset) filtering to reduce encoding artifacts. The filtered image is stored at a reference picture buffer (180).

Figure 2 illustrates a block diagram of a video decoder 200. In the decoder 200, a bitstream is decoded by the decoder elements as described below. Video decoder 200 generally performs a decoding pass reciprocal to the encoding pass as described in Figure 1 . The encoder 100 also generally performs video decoding as part of encoding video data.

In particular, the input of the decoder includes a video bitstream, which can be generated by video encoder 100. The bitstream is first entropy decoded (230) to obtain transform coefficients, motion vectors, and other coded information. The picture partition information indicates how the picture is partitioned. The decoder may therefore divide (235) the picture according to the decoded picture partitioning information. The transform coefficients are de-quantized (240) and inverse transformed (250) to decode the prediction residuals. Combining (255) the decoded prediction residuals and the predicted block, an image block is reconstructed. The predicted block can be obtained (270) from intra prediction (260) or motion-compensated prediction (i.e., inter prediction) (275). In loop filters (265) are applied to the reconstructed image. The filtered image is stored at a reference picture buffer (280).

The decoded picture can further go through post-decoding processing (285), for example, an inverse color transform (e.g. conversion from YcbCr 4:2:0 to RGB 4:4:4) or an inverse remapping performing the inverse of the remapping process performed in the pre-encoding processing (101 ). The post-decoding processing can use metadata derived in the pre-encoding processing and signaled in the bitstream.

Figure 3 illustrates a block diagram of an example of a system in which various aspects and embodiments are implemented. System 1000 can be embodied as a device including the various components described below and is configured to perform one or more of the aspects described in this document. Examples of such devices include, but are not limited to, various electronic devices such as personal computers, laptop computers, smartphones, tablet computers, digital multimedia set top boxes, digital television receivers, personal video recording systems, connected home appliances, and servers. Elements of system 1000, singly or in combination, can be embodied in a single integrated circuit (IC), multiple lcs, and/or discrete components. For example, in at least one embodiment, the processing and encoder/decoder elements of system 1000 are distributed across multiple lcs and/or discrete components. In various embodiments, the system 1000 is communicatively coupled to one or more other systems, or other electronic devices, via, for example, a communications bus or through dedicated input and/or output ports. In various embodiments, the system 1000 is configured to implement one or more of the aspects described in this document.

The system 1000 includes at least one processor 1010 configured to execute instructions loaded therein for implementing, for example, the various aspects described in this document. Processor 1010 can include embedded memory, input output interface, and various other circuitries as known in the art. The system 1000 includes at least one memory 1020 (e.g., a volatile memory device, and/or a non-volatile memory device). System 1000 includes a storage device 1040, which can include non-volatile memory and/or volatile memory, including, but not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash, magnetic disk drive, and/or optical disk drive. The storage device 1040 can include an internal storage device, an attached storage device (including detachable and non-detachable storage devices), and/or a network accessible storage device, as non-limiting examples.

System 1000 includes an encoder/decoder module 1030 configured, for example, to process data to provide an encoded video or decoded video, and the encoder/decoder module 1030 can include its own processor and memory. The encoder/decoder module 1030 represents module(s) that can be included in a device to perform the encoding and/or decoding functions. As is known, a device can include one or both of the encoding and decoding modules. Additionally, encoder/decoder module 1030 can be implemented as a separate element of system 1000 or can be incorporated within processor 1010 as a combination of hardware and software as known to those skilled in the art.

Program code to be loaded onto processor 1010 or encoder/decoder 1030 to perform the various aspects described in this document can be stored in storage device 1040 and subsequently loaded onto memory 1020 for execution by processor 1010. In accordance with various embodiments, one or more of processor 1010, memory 1020, storage device 1040, and encoder/decoder module 1030 can store one or more of various items during the performance of the processes described in this document. Such stored items can include, but are not limited to, the input video, the decoded video or portions of the decoded video, the bitstream, matrices, variables, and intermediate or final results from the processing of equations, formulas, operations, and operational logic.

In some embodiments, memory inside of the processor 1010 and/or the encoder/decoder module 1030 is used to store instructions and to provide working memory for processing that is needed during encoding or decoding. In other embodiments, however, a memory external to the processing device (for example, the processing device can be either the processor 1010 or the encoder/decoder module 1030) is used for one or more of these functions. The external memory can be the memory 1020 and/or the storage device 1040, for example, a dynamic volatile memory and/or a non-volatile flash memory. In several embodiments, an external non-volatile flash memory is used to store the operating system of, for example, a television. In at least one embodiment, a fast external dynamic volatile memory such as a RAM is used as working memory for video coding and decoding operations, such as for MPEG-2 (MPEG refers to the Moving Picture Experts Group, MPEG-2 is also referred to as ISO/IEC 13818, and 13818-1 is also known as H.222, and 13818-2 is also known as H.262), HEVC (HEVC refers to High Efficiency Video Coding, also known as H.265 and MPEG-H Part 2), or WC (Versatile Video Coding, a new standard being developed by JVET, the Joint Video Experts Team).

The input to the elements of system 1000 can be provided through various input devices as indicated in block 1 130. Such input devices include, but are not limited to, (i) a radio frequency (RF) portion that receives an RF signal transmitted, for example, over the air by a broadcaster, (ii) a Component (COMP) input terminal (or a set of COMP input terminals), (iii) a Universal Serial Bus (USB) input terminal, and/or (iv) a High Definition Multimedia Interface (HDMI) input terminal. Other examples, not shown in Figure 3, include composite video.

In various embodiments, the input devices of block 1 130 have associated respective input processing elements as known in the art. For example, the RF portion can be associated with elements suitable for (i) selecting a desired frequency (also referred to as selecting a signal, or band-limiting a signal to a band of frequencies), (ii) downconverting the selected signal, (iii) band-limiting again to a narrower band of frequencies to select (for example) a signal frequency band which can be referred to as a channel in certain embodiments, (iv) demodulating the downconverted and band-limited signal, (v) performing error correction, and (vi) demultiplexing to select the desired stream of data packets. The RF portion of various embodiments includes one or more elements to perform these functions, for example, frequency selectors, signal selectors, band- limiters, channel selectors, filters, downconverters, demodulators, error correctors, and demultiplexers. The RF portion can include a tuner that performs various of these functions, including, for example, downconverting the received signal to a lower frequency (for example, an intermediate frequency or a near-baseband frequency) or to baseband. In one set-top box embodiment, the RF portion and its associated input processing element receives an RF signal transmitted over a wired (for example, cable) medium, and performs frequency selection by filtering, downconverting, and filtering again to a desired frequency band. Various embodiments rearrange the order of the above-described (and other) elements, remove some of these elements, and/or add other elements performing similar or different functions. Adding elements can include inserting elements in between existing elements, such as, for example, inserting amplifiers and an analog-to-digital converter. In various embodiments, the RF portion includes an antenna.

Additionally, the USB and/or FIDMI terminals can include respective interface processors for connecting system 1000 to other electronic devices across USB and/or FIDMI connections. It is to be understood that various aspects of input processing, for example, Reed-Solomon error correction, can be implemented, for example, within a separate input processing IC or within processor 1010 as necessary. Similarly, aspects of USB or FIDMI interface processing can be implemented within separate interface lcs or within processor 1010 as necessary. The demodulated, error corrected, and demultiplexed stream is provided to various processing elements, including, for example, processor 1010, and encoder/decoder 1030 operating in combination with the memory and storage elements to process the datastream as necessary for presentation on an output device.

Various elements of system 1000 can be provided within an integrated housing, Within the integrated housing, the various elements can be interconnected and transmit data therebetween using suitable connection arrangement, for example, an internal bus as known in the art, including the Inter-IC (I2C) bus, wiring, and printed circuit boards.

The system 1000 includes communication interface 1050 that enables communication with other devices via communication channel 1060. The communication interface 1050 can include, but is not limited to, a transceiver configured to transmit and to receive data over communication channel 1060. The communication interface 1050 can include, but is not limited to, a modem or network card and the communication channel 1060 can be implemented, for example, within a wired and/or a wireless medium.

Data is streamed, or otherwise provided, to the system 1000, in various embodiments, using a wireless network such as a Wi-Fi network, for example IEEE 802.1 1 (IEEE refers to the Institute of Electrical and Electronics Engineers). The Wi-Fi signal of these embodiments is received over the communications channel 1060 and the communications interface 1050 which are adapted for Wi-Fi communications. The communications channel 1060 of these embodiments is typically connected to an access point or router that provides access to external networks including the Internet for allowing streaming applications and other over-the-top communications. Other embodiments provide streamed data to the system 1000 using a set-top box that delivers the data over the FIDMI connection of the input block 1 130. Still other embodiments provide streamed data to the system 1000 using the RF connection of the input block 1 130. As indicated above, various embodiments provide data in a non-streaming manner. Additionally, various embodiments use wireless networks other than Wi-Fi, for example a cellular network or a Bluetooth network.

The system 1000 can provide an output signal to various output devices, including a display 1 100, speakers 1 1 10, and other peripheral devices 1 120. The display 1 100 of various embodiments includes one or more of, for example, a touchscreen display, an organic light-emitting diode (OLED) display, a curved display, and/or a foldable display. The display 1 100 can be for a television, a tablet, a laptop, a cell phone (mobile phone), or other device. The display 1 100 can also be integrated with other components (for example, as in a smart phone), or separate (for example, an external monitor for a laptop). The other peripheral devices 1 120 include, in various examples of embodiments, one or more of a stand-alone digital video disc (or digital versatile disc) (DVR, for both terms), a disk player, a stereo system, and/or a lighting system. Various embodiments use one or more peripheral devices 1 120 that provide a function based on the output of the system 1000. For example, a disk player performs the function of playing the output of the system 1000.

In various embodiments, control signals are communicated between the system 1000 and the display 1 100, speakers 1 1 10, or other peripheral devices 1 120 using signaling such as AV.Link, Consumer Electronics Control (CEC), or other communications protocols that enable device-to-device control with or without user intervention. The output devices can be communicatively coupled to system 1000 via dedicated connections through respective interfaces 1070, 1080, and 1090. Alternatively, the output devices can be connected to system 1000 using the communications channel 1060 via the communications interface 1050. The display 1 100 and speakers 1 1 10 can be integrated in a single unit with the other components of system 1000 in an electronic device such as, for example, a television. In various embodiments, the display interface 1070 includes a display driver, such as, for example, a timing controller (T Con) chip.

The display 1 100 and speaker 1 1 10 can alternatively be separate from one or more of the other components, for example, if the RF portion of input 1 130 is part of a separate set-top box. In various embodiments in which the display 1 100 and speakers 1 1 10 are external components, the output signal can be provided via dedicated output connections, including, for example, HDMI ports, USB ports, or COMP outputs.

The embodiments can be carried out by computer software implemented by the processor 1010 or by hardware, or by a combination of hardware and software. As a non-limiting example, the embodiments can be implemented by one or more integrated circuits. The memory 1020 can be of any type appropriate to the technical environment and can be implemented using any appropriate data storage technology, such as optical memory devices, magnetic memory devices, semiconductor-based memory devices, fixed memory, and removable memory, as non-limiting examples. The processor 1010 can be of any type appropriate to the technical environment, and can encompass one or more of microprocessors, general purpose computers, special purpose computers, and processors based on a multi-core architecture, as non-limiting examples.

Various implementations involve decoding. “Decoding”, as used in this application, can encompass all or part of the processes performed, for example, on a received encoded sequence to produce a final output suitable for display. In various embodiments, such processes include one or more of the processes typically performed by a decoder, for example, entropy decoding, inverse quantization, inverse transformation, and differential decoding. In various embodiments, such processes also, or alternatively, include processes performed by a decoder of various implementations described in this application. As further examples, in one embodiment “decoding” refers only to entropy decoding, in another embodiment“decoding” refers only to differential decoding, and in another embodiment “decoding” refers to a combination of entropy decoding and differential decoding. Whether the phrase “decoding process” is intended to refer specifically to a subset of operations or generally to the broader decoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.

Various implementations involve encoding. In an analogous way to the above discussion about“decoding”,“encoding” as used in this application can encompass all or part of the processes performed, for example, on an input video sequence to produce an encoded bitstream. In various embodiments, such processes include one or more of the processes typically performed by an encoder, for example, partitioning, differential encoding, transformation, quantization, and entropy encoding. In various embodiments, such processes also, or alternatively, include processes performed by an encoder of various implementations described in this application.

As further examples, in one embodiment “encoding” refers only to entropy encoding, in another embodiment“encoding” refers only to differential encoding, and in another embodiment“encoding” refers to a combination of differential encoding and entropy encoding. Whether the phrase“encoding process” is intended to refer specifically to a subset of operations or generally to the broader encoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.

Note that the syntax elements as used herein are descriptive terms. As such, they do not preclude the use of other syntax element names.

When a figure is presented as a flow diagram, it should be understood that it also provides a block diagram of a corresponding apparatus. Similarly, when a figure is presented as a block diagram, it should be understood that it also provides a flow diagram of a corresponding method/process.

Various embodiments may refer to parametric models or rate distortion optimization. In particular, during the encoding process, the balance or trade-off between the rate and distortion is usually considered, often given the constraints of computational complexity. It can be measured through a Rate Distortion Optimization (RDO) metric, or through Least Mean Square (LMS), Mean of Absolute Errors (MAE), or other such measurements. Rate distortion optimization is usually formulated as minimizing a rate distortion function, which is a weighted sum of the rate and of the distortion. There are different approaches to solve the rate distortion optimization problem. For example, the approaches may be based on an extensive testing of all encoding options, including all considered modes or coding parameters values, with a complete evaluation of their coding cost and related distortion of the reconstructed signal after coding and decoding. Faster approaches may also be used, to save encoding complexity, in particular with computation of an approximated distortion based on the prediction or the prediction residual signal, not the reconstructed one. Mix of these two approaches can also be used, such as by using an approximated distortion for only some of the possible encoding options, and a complete distortion for other encoding options. Other approaches only evaluate a subset of the possible encoding options. More generally, many approaches employ any of a variety of techniques to perform the optimization, but the optimization is not necessarily a complete evaluation of both the coding cost and related distortion.

The implementations and aspects described herein can be implemented in, for example, a method or a process, an apparatus, a software program, a data stream, or a signal. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation of features discussed can also be implemented in other forms (for example, an apparatus or program). An apparatus can be implemented in, for example, appropriate hardware, software, and firmware. The methods can be implemented in, for example, , a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants (“PDAs”), and other devices that facilitate communication of information between end- users.

Reference to“one embodiment” or“an embodiment” or“one implementation” or “an implementation”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase“in one embodiment” or“in an embodiment” or“in one implementation” or“in an implementation”, as well any other variations, appearing in various places throughout this application are not necessarily all referring to the same embodiment.

Additionally, this application may refer to “determining” various pieces of information. Determining the information can include one or more of, for example, estimating the information, calculating the information, predicting the information, or retrieving the information from memory.

Further, this application may refer to“accessing” various pieces of information. Accessing the information can include one or more of, for example, receiving the information, retrieving the information (for example, from memory), storing the information, moving the information, copying the information, calculating the information, determining the information, predicting the information, or estimating the information.

Additionally, this application may refer to“receiving” various pieces of information. Receiving is, as with“accessing”, intended to be a broad term. Receiving the information can include one or more of, for example, accessing the information, or retrieving the information (for example, from memory). Further,“receiving” is typically involved, in one way or another, during operations such as, for example, storing the information, processing the information, transmitting the information, moving the information, copying the information, erasing the information, calculating the information, determining the information, predicting the information, or estimating the information.

It is to be appreciated that the use of any of the following 7”,“and/or”, and“at least one of”, for example, in the cases of“A/B”,“A and/or B” and“at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of“A, B, and/or C” and“at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are listed.

Also, as used herein, the word“signal” refers to, among other things, indicating something to a corresponding decoder. For example, in certain embodiments the encoder signals a particular one of a plurality of transforms, coding modes or flags. In this way, in an embodiment the same transform, parameter, or mode is used at both the encoder side and the decoder side. Thus, for example, an encoder can transmit (explicit signaling) a particular parameter to the decoder so that the decoder can use the same particular parameter. Conversely, if the decoder already has the particular parameter as well as others, then signaling can be used without transmitting (implicit signaling) to simply allow the decoder to know and select the particular parameter. By avoiding transmission of any actual functions, a bit savings is realized in various embodiments. It is to be appreciated that signaling can be accomplished in a variety of ways. For example, one or more syntax elements, flags, and so forth are used to signal information to a corresponding decoder in various embodiments. While the preceding relates to the verb form of the word“signal”, the word“signal” can also be used herein as a noun.

As will be evident to one of ordinary skill in the art, implementations can produce a variety of signals formatted to carry information that can be, for example, stored or transmitted. The information can include, for example, instructions for performing a method, or data produced by one of the described implementations. For example, a signal can be formatted to carry the bitstream of a described embodiment. Such a signal can be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal. The formatting can include, for example, encoding a data stream and modulating a carrier with the encoded data stream. The information that the signal carries can be, for example, analog or digital information. The signal can be transmitted over a variety of different wired or wireless links, as is known. The signal can be stored on a processor-readable medium.

We describe a number of embodiments, across various claim categories and types. Features of these embodiments can be provided alone or in any combination. Further, embodiments can include one or more of the following features, devices, or aspects, alone or in any combination, across various claim categories and types: • A bitstream or signal that includes one or more of the described syntax elements, or variations thereof.

• A bitstream or signal that includes syntax conveying information generated according to any of the embodiments described.

• Creating and/or transmitting and/or receiving and/or decoding according to any of the embodiments described.

• A method, process, apparatus, medium storing instructions, medium storing data, or signal according to any of the embodiments described.

• Inserting in the signaling syntax elements that enable the decoder to determine coding mode in a manner corresponding to that used by an encoder.

• Creating and/or transmitting and/or receiving and/or decoding a bitstream or signal that includes one or more of the described syntax elements, or variations thereof.

• A TV, set-top box, cell phone, tablet, or other electronic device that performs transform method(s) according to any of the embodiments described.

• A TV, set-top box, cell phone, tablet, or other electronic device that performs transform method(s) determination according to any of the embodiments described, and that displays (e.g. using a monitor, screen, or other type of display) a resulting image.

• A TV, set-top box, cell phone, tablet, or other electronic device that selects, bandlimits, or tunes (e.g. using a tuner) a channel to receive a signal including an encoded image, and performs transform method(s) according to any of the embodiments described.

• A TV, set-top box, cell phone, tablet, or other electronic device that receives (e.g. using an antenna) a signal over the air that includes an encoded image, and performs transform method(s).