BACKGROUND

Field

[0001] This invention relates to oscillators, and more specifically, to an RC oscillator based on a delay-free comparator.

Background

[0002] The resistive-capacitive (RC) oscillator is an important block in very-large- scale integration (VLSI) systems. It provides a reference clock when a crystal oscillator is not available or off for power saving purpose. However, the frequency accuracy of the RC oscillator is limited by RC process variation, resistor temperature coefficient, and comparator delay variation.

[0003] The temperature variation of the comparator delay is the major contributor of the frequency variation. Conventionally, the bias current of the comparator is boosted up to make the total delay a small fraction of the clock period. However, the comparator delay saturates at high bias current. To counter this effect, the device size is increased. However, this results in even more current requirement. Therefore, the power efficiency of the RC oscillator prevents it from use in low power applications. Other solutions include selecting low frequency for sleep-mode clock to bypass the delay issue or applying a closed-loop integrator to force the comparator trip voltage to be equal to the reference.

SUMMARY

[0004] The present invention provides for extracting and cancelling a comparator delay which causes frequency variation in a clock pulse of an RC oscillator, using a switched-capacitor technique.

[0005] In one embodiment, a method for cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse is disclosed. The method includes:

selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.

[0006] In another embodiment, an RC oscillator which generates a clock pulse is disclosed. The RC oscillator includes: a comparator delay cancellation circuit comprising: a resistor and a pair of capacitors including a first capacitor and a second capacitor; a plurality of current sources configured to charge and discharge the pair of capacitors and the resistor, wherein the first capacitor is charged during first and second phases of the clock pulse and is discharged during third and fourth phases of the clock pulse, and the second capacitor is charged during the third and fourth phases of the clock pulse and is discharged during the first and second phases of the clock pulse, wherein the first capacitor is charged at a same rate during the first phase as the second phase, and the second capacitor is charged at a higher rate during the third phase than the fourth phase; a plurality of switches configured to selectively couple the plurality of current sources to the pair of capacitors and the resistor; and a comparator having a first input and a second input, the comparator configured to generate the clock pulse by comparing a voltage on the first or second capacitor with a voltage on the resistor.

[0007] In yet another embodiment, an apparatus to generate a clock pulse is disclosed. The apparatus includes: means for comparing two voltages having a first input and a second input; means for canceling delay in the means for comparing two voltages comprising: means for charging and discharging a first capacitor and a second capacitor, wherein the means for charging and discharging charges the first capacitor at a higher rate during a first phase of the clock than a second phase of the clock pulse, and charges the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; means for selectively coupling the means for charging and discharging to the pair of capacitors and a resistor, wherein the means for comparing two voltages generates the clock pulse by comparing a voltage on the first or second capacitor with a voltage on the resistor. [0008] Other features and advantages of the present invention should be apparent from the present description which illustrates, by way of example, aspects of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The details of the present invention, both as to its structure and operation, may be gleaned in part by study of the appended further drawings, in which like reference numerals refer to like parts, and in which:

[0010] FIG. 1 is a function block diagram of an RC oscillator circuit including a delay-cancellation circuit, a chopper, a comparator, and a clock generator, implemented in accordance with one embodiment of the present invention;

[0011] FIG. 2 is a detailed schematic diagram of the delay-cancellation circuit in accordance with one embodiment of the present invention;

[0012] FIG. 3 is a diagram showing timing and voltage waveforms of the RC oscillator;

[0013] FIG. 4 is a detailed schematic diagram of the chopper in accordance with one embodiment of the present invention;

[0014] FIG. 5 is a functional block diagram of the clock generator in accordance with one embodiment of the present invention;

[0015] FIG. 6 shows the timing diagram of the clock phases generated by the clock generator;

[0016] FIG. 7 is a detailed schematic diagram of a delay-cancellation circuit including the resistor compensation current source (CS _A ) in accordance with one embodiment of the present invention;

[0017] FIG. 8 is a schematic diagram of the compensation current source (CS _A ) implemented with two sets of 10-bit switchable binary current digital-to-analog converters (DACs) in accordance with another embodiment of the present invention;

[0018] FIG. 9 is a flow diagram illustrating a method for calibrating the RC oscillator frequency in accordance with one embodiment of the present invention;

[0019] FIG. 10 is a calibration circuit configured to calibrate the RC oscillator frequency using compensation current source shown in FIG. 8 in accordance with one embodiment of the present invention; [0020] FIG. 11 is the timing diagram of the calibration method;

[0021] FIG. 12 shows the calibration timing signals;

[0022] FIG. 13 is a detailed schematic diagram of a delay-cancellation circuit in accordance with another embodiment of the present invention; and

[0023] FIG. 14 is a diagram showing timing and voltage waveforms of the RC oscillator (as shown in FIG. 1) with delay cancellation circuit (as shown in FIG. 13).

DETAILED DESCRIPTION

[0024] As stated above, the RC oscillator is an important block in VLSI systems. It provides a reference clock when a crystal oscillator is not available or off for power saving purpose. However, the frequency accuracy of the RC oscillator is limited by RC process variation, resistor temperature coefficient, and comparator delay variation. In a conventional RC oscillator design, the offset voltage of the comparator is canceled by comparing two capacitor voltages with a resistor voltage. When the voltage on the first capacitor is ramped up as it is being charged by the first charging current, the second capacitor is shorted to the ground. The comparator compares the first capacitor voltage to the resistor voltage. Upon transition of the comparator, the first capacitor is shorted to the ground, while the voltage on the second capacitor is ramped up as it is being charged by the second charging current. The comparator now compares the second capacitor voltage to the resistor voltage with connections of the capacitor voltage and the resistor voltage to the comparator inputs swapped. The voltage offsets of the comparator are equal in value but opposite in sign during the two phases of the clock cycle (i.e., T _\ and T ₂ ), and thus, they cancel out. Equation (1) shows the duration of the first phase of the clock cycle as RC minus the product of C and the offset voltage Vos divided by the current I, plus the time delay (T _d ). Equation (2) shows the duration of the second phase of the clock cycle as RC plus the product of C and the offset voltage Vos divided by the current I, plus T _d . Equation (3) shows the derivation of the clock period (T) of the RC oscillator as the sum of the durations of the first phase and the second phase. Thus, the clock period is shown as being equal to two times the RC time constant plus rise and fall time delays (2*T _d ) of the comparator. Therefore, equation (3) shows the cancellation of the comparator offset voltage (VosX but the time delays of the comparator remain.

T _{1 =} RC - CVos/I + T _d (1) T ₂ = RC + CVos/I + T _d (2) T = Ti+T ₂ = 2*RC + 2*T _d (3)

[0025] Certain embodiments as described herein provide for extracting and cancelling the comparator delay which causes frequency variation in a clock pulse of an RC oscillator, using a switched-capacitor technique. After reading this description it will become apparent how to implement the invention in various implementations and applications. Although various implementations of the present invention will be described herein, it is understood that these implementations are presented by way of example only, and not limitation. As such, this detailed description of various implementations should not be construed to limit the scope or breadth of the present invention.

[0026] FIG. 1 is a function block diagram of an RC oscillator circuit 100 including a delay-cancellation circuit 110, a chopper 120, a comparator 130, and a clock generator 140, implemented in accordance with one embodiment of the present invention. The combination of the delay-cancellation circuit 110 and the chopper 120 extracts and cancels the comparator delay in a clock pulse using a switched-capacitor technique (see FIG. 2). The duration of the clock pulse is equal to the summation of the clock turn-on and turn-off times of the comparator and the feedback loop. During clock phases Φ ₁ and Φ ₃ of the clock pulse, the active capacitor is ramped down with the same amount of discharging current, and the inactive capacitor starts ramping up at a rate that is 50% higher than a nominal rate, and the inactive capacitor becomes active and is then ramped up at the nominal rate during Φ ₂ and Φ ₄ . Accordingly, the clock pulse meets the trip point of the comparator (i.e., V _CL = _R or V _CR = V _R ) earlier so that at the instant of transition, the total delay is equal to that of a delay-free comparator with a nominal ramp-up rate.

[0027] FIG. 2 is a detailed schematic diagram of the delay-cancellation circuit 110 in accordance with one embodiment of the present invention. In the illustrated

embodiment of FIG. 2, the delay-cancellation circuit 110 includes capacitors C _L and C _R , resistor R, current sources CSi through CS ₅ , and switches Si through Sg. Current sources CSi, CS ₃ , CS ₄ , and CS ₅ supply current /, when connected, while current source CS ₂ supply current 0.5*1, when connected. Further, current sources CSi, CS ₂ , CS ₃ , and CS ₅ are coupled to the supply voltage for charging the capacitors, while CS ₄ is coupled to the ground voltage for discharging the capacitors. The delay-cancellation circuit 110 also includes three output nodes, V _CL (left capacitor voltage), V _CR (right capacitor voltage), and V _R (resistor voltage).

[0028] During the first clock phase (Φι), switches Si, S ₂ , and S ₆ are closed so that capacitor C _L is charged with current from current sources CSi and CS ₂ , while capacitor C _R is discharged by current sink CS ₄ . Moreover, capacitor C _L is charged at 50% higher rate than a nominal rate because current source CSi supplies current / (nominal rate), while current source CS ₂ supplies additional current 0.5*1 (50% more) to capacitor C _L . During the second clock phase (Φ ₂ ), switches Si and Sg are closed so that capacitor C _L is charged with current from current source CSi, while capacitor C _R is shorted to the ground. During the third clock phase (Φ ₃ ), switches S3, S ₄ , and S5 are closed so that capacitor C _R is charged with current from current sources CS ₂ and CS ₃ , while capacitor C _L is discharged by current sink CS ₄ . Moreover, capacitor C _R is charged at 50% higher rate than the nominal rate because current source CS ₃ supplies current / (nominal rate), while current source CS ₂ supplies additional current 0.5*1 (50% more) to capacitor C _R . During the fourth clock phase (Φ ₄ ), switches S ₄ and S ₇ are closed so that capacitor C _R is charged with current from current source CS ₃ , while capacitor C _L is shorted to the ground. Current source CS ₅ supplies current / to resistor R so that the resistor voltage V _R will have a constant value IR. The clock pulse repeats the four phases as described above.

[0029] FIG. 3 is a diagram showing timing and voltage waveforms of the RC oscillator 100 (as shown in FIG. 1) with delay cancellation circuit 110 (as shown in FIG. 2). As described above with respect to FIG. 2, during the first clock phase (Φι), capacitor C _L is charged at 50% higher rate than a nominal rate by current sources CSi and CS ₂ , while capacitor C _R is discharged by current sink CS ₄ . Correspondingly, during the first clock phase (Φι) shown in FIG. 3, V _CL ramps up at a slope (solid line SLi) that is 50% higher than the nominal rate (dotted line slope SL ₂ ). Moreover, V _CR ramps down (capacitor C _R discharging) at the nominal rate (solid line slope SL ₃ ). During the second clock phase (Φ ₂ ) shown in FIG. 2, capacitor C _L is charged at the nominal rate by the current source CS _1; while capacitor C _R is shorted to the ground. Correspondingly, during the second clock phase (Φ ₂ ) shown in FIG. 3, V _CL ramps up at the nominal rate (solid line slope SL ₄ = SL ₂ ). Moreover, V _CR is tied to the ground voltage. Further, during the second clock phase (Φ ₂ ), when the capacitor voltage (i.e., V _CL ) reaches the trip point of the comparator (when V _CL = V _R ), the comparator's output transitions after some delay (T _f ). During the third clock phase (Φ ₃ ) shown in FIG. 2, capacitor C _R is charged at 50% higher rate than the nominal rate by current sources CS ₂ and CS ₃ , while capacitor C _L is discharged by current sink CS ₄ . Correspondingly, during the third clock phase (Φ ₃ ) shown in FIG. 3, V _CR ramps up at a slope (solid line SL ₅ ) that is 50% higher than the nominal rate (dotted line slope SL ₆ ). Moreover, V _CL ramps down (capacitor C _L discharging) at the nominal rate (solid line slope SL ₇ ). Thus, after the comparator's output transitions, the capacitor voltage (V _CL ) stays connected to the comparator, but it is ramped down (solid line slope SL ₇ ) with the same amount of discharging current. After some delay (T _r ), it causes the comparator to make an opposite transition. The time duration between the two transitions is equal to the fall time delay (T _f ) plus the rise time delay (T _r ) of the comparator. During the fourth clock phase (Φ ₄ ) shown in FIG. 2, capacitor C _R is charged by the current source CS ₃ , while capacitor C _L is shorted to the ground. Correspondingly, during the fourth clock phase (Φ ₄ ) shown in FIG. 3, V _CR ramps up at the nominal rate (solid line slope SLg = SL ₆ ). Moreover, V _CL is tied to the ground voltage. Thus, the cancellation of the comparator delay from the clock period is shown in FIG. 3 by comparing the real comparator (solid lines) with an ideal delay-free comparator (dashed lines), wherein the real comparator with the delay transitions at the same time. Equations (4), (5), and (6) show the derivation of the clock period (T).

[I*Ti+I/2*(T _r +T _f )]/C=I*R-Vos+I*T _f /C (4) [I*T ₂ +I/2*(T _f +T _r )]/C=I*R+Vos+I*TJC (5) T=Ti+T ₂ =2*RC (6)

[0030] Equation (4) shows the comparator voltage during the first time period (T including the first phase (Φ and the second phase (Φ ₂ ) of the clock pulse. Equation (5) shows the comparator voltage during the second time period (T ₂ ) including the third phase (Φ ₃ ) and the fourth phase (Φ ₄ ) of the clock pulse. The difference in the comparator voltage during these two time periods is the opposite polarity of the offset voltage and the time delay, which cancel out to produce resultant equation (6). Thus, equation (6) shows that the clock period depends solely on the time constant (RC).

[0031] FIG. 4 is a detailed schematic diagram of the chopper 120 in accordance with one embodiment of the present invention. In the illustrated embodiment of FIG. 4, switches Si and S ₂ select between VCL and VCR, whereas switches S ₃ through S ₆ select between the capacitor voltage (VCL or VCR) and the resistor voltage (VR). Thus, the switches couple the capacitor voltage and the resistor voltage to the two comparator input nodes (V _p and V _m ). By closing switches S ₃ and S ₆ , while keeping switches S ₄ and S ₅ open, the capacitor voltage (VCL or VCR) couples to the plus comparator input node (V _p ), while the resistor voltage (VR) couples to the minus comparator input node (V _m ). In contrast, by closing switches S ₄ and S ₅ , while keeping switches S ₃ and S ₆ open, the resistor voltage (VR) couples to the plus comparator input node (V _p ), while the capacitor voltage (VCL or VCR) couples to the minus comparator input node (V _m ).

[0032] FIG. 5 is a functional block diagram of the clock generator 140 in accordance with one embodiment of the present invention. As shown, the clock generator 140 employs shift registers 510, 520 running in parallel to construct the different clock phases. The states (e.g., one-hot states) of the shift registers 510, 520 are combined through XOR and XNOR gates in the combinational logic 530. The comparator output (V _cmp ) serves as a clock input for the shift registers 510, 520 and includes four phases (Φ _{1 ;} Φ ₂ , Φ ₃ , and Φ ₄ ). The left shift register 510 generates the main control clocks (Φ ₁₂ , Φ ₂₃ , Φ ₃₄ , and Φ ₁₄ ). The right shift register 520 samples at the short pulses to generate non-overlapping clock phases (Φ ₂₃₍₁ and Φ ₁₄₍₁ ). The right shift register 520 also generates clock phase Φ ₅ to temporarily increase the comparator bias current.

[0033] FIG. 6 shows the timing diagram of the clock phases generated by the clock generator 140. As stated above, the comparator output (V _cmp ) includes four basic phases (Φ _{1 ;} Φ ₂ , Φ ₃ , and Φ ₄ ) in one clock cycle. Thus, the four phases (Φ _{1 ;} Φ ₂ , Φ ₃ , and Φ ₄ ) and the control clocks (Φι ₂ , Φ ₂₃ , Φ ₃₄ , and Φ ₁₄ ) derived from those basic phases are used to control the charging and discharging of the current sources in the cancellation circuit 110, and to control the switches in the chopper 120. During each phase of clock phases Φ ₂ and Φ ₄ , there is a short pulse caused by the swapping of the comparator inputs in the chopper 120. This short pulse is used to generate non-overlapping phases Φ ₂ 3ά and Φ ₁₄₍ ι. The non-overlapping phases are used in the chopper 120 to eliminate the charge sharing during the swapping of the comparator inputs. The clock generator 140 also generates clock phase Φ ₅ using the short pulse to temporarily increase the comparator bias current which reduces the pulse width.

[0034] After mitigating the temperature and voltage-dependence, the RC oscillator frequency is still dependent on process parameters. For example, the frequency of the RC oscillator can vary up to +20% across corners, which is due to the resistance and capacitance variation at different corners. To remove or calibrate out the process variation in the oscillator design, a compensation current (ΔΙ) can be added to the resistor by adding a compensation current source. FIG. 7 is a detailed schematic diagram of a delay-cancellation circuit 700 including the resistor compensation current source (CS _A ) in accordance with one embodiment of the present invention. The delta increase or decrease of the compensation current corrects for the variation of the RC time constant as shown below in equation (7).

Τ = Τι+Τ ₂ = 2(1+Δ) * RC (7)

[0035] FIG. 8 is a schematic diagram of the compensation current source (CS _A ) 800 implemented with two sets of 10-bit switchable binary current digital-to-analog converters (DACs) 810, 820 in accordance with another embodiment of the present invention. In one embodiment, the double binary currents are generated from a folded current mirror. The top 5 MSB DACs (32, 64, 128, 256, 512) use the first scaled-down gate bias voltage for higher current density, and the lower 5 LSB DACs (1, 2, 4, 8, 16) use the second scaled-down gate bias voltage for lower current density. Therefore, DACs are of the same or substantially similar transistor size.

[0036] In the illustrated embodiment of FIG. 8, the double binary current DACs are configured to compensate for the variations in the current mirror itself. Two coarse current DACs (IDACs) can be used to achieve high-resolution since any MSB DAC mismatch can be compensated for by the redundancy of the lower LSB DAC. Accordingly, no mismatch compensation or monotonicity is required for the double binary IDACs.

[0037] FIG. 13 is a detailed schematic diagram of a delay-cancellation circuit 1300 in accordance with another embodiment of the present invention. In the illustrated embodiment of FIG. 13, the delay-cancellation circuit 1300 includes capacitors CL and CR, resistor R, current sources CSi through CS ₅ , current sources CSA, and switches Si through S ₆ . Current sources CSi through CS ₅ supply current /, when connected, while current source CSA supply current AI, when connected. Further, current sources CSi, CS ₂ , CS ₃ , CS ₅ , and CSA are coupled to the supply voltage for charging the capacitors, while CS ₄ is coupled to the ground voltage for discharging the capacitors. The delay- cancellation circuit 1300 also includes three output nodes, VCL (left capacitor voltage), VCR (right capacitor voltage), and VR (resistor voltage).

[0038] During the first and second clock phases (Φ ₁ and Φ ₂ ), switches Si and S ₆ are closed so that capacitor CL is charged with current from current source CSi, while capacitor CR is shorted to the ground. Thus, during these clock phases, capacitor CL is charged at a nominal rate because current source CSi supplies current / (nominal rate) to capacitor CL- During the third clock phase (Φ ₃ ), switches S ₂ , S3, and S ₄ are closed so that capacitor CR is charged with current from current sources CS ₂ and CS ₃ , while capacitor CL is discharged by current sink CS ₄ . Moreover, capacitor CR is charged at 100% higher rate (i.e., CR has double the ramp-up rate of CL during Φ3) than the nominal rate because current source CS ₃ supplies current / (nominal rate), while current source CS ₂ supplies additional current / (100% more) to capacitor CR. During the fourth clock phase (Φ ₄ ), switches S ₃ and S ₅ are closed so that capacitor CR is charged with current from current source CS ₃ only at a nominal rate, while capacitor CL is shorted to the ground. Current source CS ₅ and CSA supply current I+AI to resistor R (similar to the delay-cancellation circuit configuration 700 including the resistor compensation current source (CSA) shown in FIG. 7) so that the resistor voltage VR will have a constant value IR. Accordingly, VCR has two times faster ramp-up rate than VCL during Φ ₃ , but VCR is reset at the beginning of every clock cycle (i.e., no ramp down but short to the ground with S ₆ ). In contrasts, VCL ramps up at a nominal rate, but it is ramped down (with CS ₄ ) for delay extraction. [0039] FIG. 14 is a diagram showing timing and voltage waveforms of the RC oscillator 100 (as shown in FIG. 1) with delay cancellation circuit 1300 (as shown in FIG. 13). As described above with respect to FIG. 13, during the first and second clock phases (Φ ₁ and Φ ₂ ), capacitor C _L is charged at a nominal rate by current source CS _1; while capacitor C _R is reset by switch S ₆ . Correspondingly, during the first and second clock phases (Φ ₁ and Φ ₂ ) shown in FIG. 14, V _CL ramps up at slope SLi at the nominal rate. Moreover, V _CR is reset to the ground by switch S6. During the third clock phase (Φ ₃ ) shown in FIG. 13, capacitor C _R is charged at 100% higher rate than the nominal rate by current sources CS ₂ and CS ₃ , while capacitor C _L is discharged by current sink CS ₄ . Correspondingly, during the third clock phase (Φ ₃ ) shown in FIG. 14, V _CR ramps up at slope SL ₂ that is 100% higher than the nominal rate. Moreover, V _CL ramps down (capacitor C _L discharging) at the nominal rate (slope SL ₃ ). Thus, after the comparator's output transitions, the capacitor voltage (V _CL ) stays connected to the comparator, but it is ramped down at slope SL ₃ with the same amount of discharging current. After some delay (T _r ), it causes the comparator to make an opposite transition. The time duration between the two transitions is equal to the fall time delay (T _f ) plus the rise time delay (T _r ) of the comparator. During the fourth clock phase (Φ ₄ ) shown in FIG. 13, capacitor C _R is charged by the current source CS ₃ , while capacitor C _L is shorted to the ground by switch S5. Correspondingly, during the fourth clock phase (Φ ₄ ) shown in FIG. 14, V _CR ramps up at the nominal rate (slope SL ₄ ). Moreover, V _CL is reset to the ground voltage. Thus, the cancellation of the comparator delay from the clock period is shown in FIG. 14 with Equations (8), (9), and (10) showing the derivation of the clock period (T).

PT^PR-Vos+PT _f /C (8)

[PT ₂ +P(T _f +T _r )]/C=PR+V _OS +PTJC (9) T=Ti+T ₂ =2*RC (10)

[0040] Equation (8) shows the comparator voltage during the first time period (T including the first phase (Φ0 and the second phase (Φ ₂ ) of the clock pulse. Equation (9) shows the comparator voltage during the second time period (T ₂ ) including the third phase (Φ ₃ ) and the fourth phase (Φ ₄ ) of the clock pulse. The difference in the comparator voltage during these two time periods is the opposite polarity of the offset voltage and the time delay, which cancel out to produce resultant equation (10). Thus, equation (10) shows that the clock period depends solely on the time constant (RC).

[0041] FIG. 9 is a flow diagram illustrating a method 900 for calibrating the RC oscillator frequency in accordance with one embodiment of the present invention. At the beginning of the calibration, the RC oscillator frequency is compared with a reference frequency, at step 910, to determine if the RC oscillator frequency is higher or lower than the reference frequency. The frequency comparison also generates (n+l)-bit code Q. For the 10-bit double binary current DACs shown in FIG. 8, the frequency comparison generates 11-bit code Q. From the frequency comparison,

Q/(2RC) = f _RCO *2 ⁿ , (11)

wherein RC is the time constant, f _R co is the RC oscillator frequency, and n is the number of bits in the compensation current source.

[0042] In one example in which n = 10 and f _R co= 9.6MHz, Q is equal to

9.6M*1024*2RC. In order to make the RC oscillator frequency equal to 9.6MHz, the delta current can be derived as 1+A=1024/Q. Since the LSB current has been scaled down by 1024, the normalized binary compensation current (Y) is given below in equations (12) and (13).

Y=(1024-Q)/Q*1024 (for Q < 1024) (12) Y=(Q-1024)/Q*1024 (for Q > 1024) (13) Although code Y is not directly used to control the compensation current mirror, it provides an index indicating where to start the calibration. For example, if Y = 14, the calibration should start from the fourth LSB. In another example, if Y is 122, the calibration should start from the fourth MSB, and if Y is 277, the calibration should start from the second MSB. Therefore, once code Y is generated, it is then converted to a one-hot code. The hot position indicates the highest bit of code Y which is one.

Accordingly, the one-hot code indicates to the controller where to start the calibration.

[0043] Once the RC oscillator frequency is compared to the reference frequency, at step 910, and it is determined that the oscillator frequency is greater than the reference frequency, ΔΙ is set to positive (POS), at step 920, and Y is calculated to be (2 ⁿ - Q) / Q*2 ⁿ , at step 922, where n is the resolution of the compensation current source. In the example of FIG. 8, n is equal to 10. Otherwise, if the oscillator frequency is less than the reference frequency, ΔΙ is set to negative (NEG), at step 926, and Y is calculated to be (Q - 2 ⁿ ) / Q*2 ⁿ , at step 928. Further, if the oscillator frequency is equal to the reference frequency, then the frequency calibration ends, at step 924. The current source index (i) is then set, at step 930, to MSB of Y.

[0044] During the calibration, the binary current source is turned on, at step 932, for bit i, and the new oscillator frequency is compared to the reference frequency, at step 940. Thus, the binary currents are turned on one at a time from MSB to LSB. If the frequency comparison keeps the same polarity, then the binary current source is kept on, and the calibration process jumps to the next current source. That is, if the new oscillator frequency is greater than the reference frequency and ΔΙ is equal to POS (i.e., the previous oscillator frequency was also greater than the reference frequency) to produce a YES answer, at step 942, then the binary current source at bit i is kept on, at step 950. However, if the new oscillator frequency is greater than the reference frequency and ΔΙ is equal to NEG (i.e., the previous oscillator frequency was less than the reference frequency) to produce a NO answer, at step 942, then the binary current source at bit i is turned off, at step 952. Otherwise, if the new oscillator frequency is less than the reference frequency and ΔΙ is equal to NEG (i.e., the previous oscillator frequency was also less than the reference frequency) to produce a YES answer, at step 944, then the binary current source at bit i is kept on, at step 954. However, if the new oscillator frequency is less than the reference frequency and ΔΙ is equal to POS (i.e., the previous oscillator frequency was greater than the reference frequency) to produce a NO answer, at step 944, then the binary current source at bit i is turned off, at step 952.

[0045] After step 950, 952, or 954, the index for the binary current source shifts to the next bit, at step 960. If it is determined, at step 962, that the incremented index for the binary current source is equal to 2*n, then the calibration ends, at step 970. Otherwise, if the incremented index for the binary current source has not yet reached 2*n, then the calibration resumes, at step 932, by turning the binary current source on at bit i on. Thus, during the calibration, a selected set of binary current sources is used to provide the correct amount of compensation current to adjust the RC oscillator frequency. After each calibration, a 2*n-bit calibration code is provided to the current mirror. [0046] FIG. 10 is a calibration circuit 1000 configured to calibrate the RC oscillator frequency using compensation current source shown in FIG. 8 in accordance with one embodiment of the present invention. In the illustrated embodiment of FIG. 10, the calibration circuit 1000 includes a frequency comparator 1010 and a controller 1030. The frequency comparator 1010 includes a divide -by-2 ⁿ unit 1020, a 2 ⁿ⁺¹ counter 1022, and a control unit 1024. The controller 1030 includes a register 1040, a mapping unit 1042, a digital comparator 1044, an arbiter 1046, a current control unit 1048, and a one- hot generator 1050.

[0047] In the illustrated embodiment of FIG. 10, when Start signal is high, the control unit 1024 keeps the frequency comparator 1010 in a hold state for the input RC oscillator frequency to settle. The divide-by- 2 ⁿ unit 1020 then divides the RC oscillator clock (RC_CLK) for 2 ⁿ times (where n is the resolution of the compensation current source). This results in a time window equal to 2 ⁿ times RC oscillator clock cycles. During this time window, the 2 ⁿ⁺¹ counter 1022 counts the reference clock (M_CLK) to relate the RC oscillator frequency with the reference frequency and generate code Q. During the frequency comparison, the control unit 1024 keeps Busy signal high, while the signal is driven low once the comparison is done. Busy signal is transmitted to the arbiter unit 1046 of the controller 1030. The arbiter unit 1046 of the controller 1030 then reads code Q to determine the next step.

[0048] In the controller 1030, the arbiter unit 1046 generates multiple timing control signals, which are sent to the D-flip-flops (DFF) in other sub-blocks. The one-hot generator 1050 generates (2n+l)-bit one-hot code, which indicates the current position or index of the double binary current sources under comparison. The current control unit 1048 includes 2n DFF pairs, which turns the current sources on or off. In the illustrated embodiment of the controller 1030 in FIG. 10, when calibration input is high, the arbiter unit 1046 of the controller 1030 generates Start signal which starts the frequency comparison. The first frequency comparison triggered by Start signal compares the nominal RC oscillator frequency with the reference frequency. Further, the comparison result determines the polarity of the calibration which either increases or decreases the resistor current. After the frequency comparison, Busy signal is driven low. In one embodiment, the arbiter unit 1046 uses the high-to-low transition of Busy signal to perform several operations between two frequency comparisons, and those operations need to be sequential since one operation uses the results of the other operation.

Therefore, the arbiter unit 1046 delays Busy signal by two M_CLK cycles to generate Busy_d signal and delays Busy signal by four M_CLK cycles to generate Busy_d2 signal. Code Q is generated at the falling edge of Busy signal. The mapping block 1042 uses Busy signal to determine the starting index for the one-hot generator 1050, which shifts the one-hot bit at the falling edge of Busy_d signal. The output of the one-hot generator 1050 is then sent to the current control unit 1048, which uses the falling edge of Busy_d2 signal as the clock. At the beginning of the calibration, the one-hot state is all zero. After the first frequency comparison, the one-hot state transitions to a higher state at the falling edge of Busy_d2 signal. The one-hot status sent to the register 1040 indicates this transition. The low-to-high transition of the one-hot_status signal clocks the register block, which saves the nominal RC oscillator frequency comparison results and the calibration polarity as described above. The digital comparator 1044 compares each frequency comparison results with value 2 ⁿ . When the RC oscillator frequency reaches the target frequency, the calibration cycle ends. Otherwise, the calibration cycle transitions from the starting index to the last LSB. Start and Busy signals serve as handshaking signals between the frequency comparator 1010 and the controller 1030. FIG. 11 is the timing diagram of the calibration method and FIG. 12 shows the calibration timing signals.

[0049] Although several embodiments of the invention are described above, many variations of the invention are possible. For example, although the illustrated embodiments described above use two charging capacitors for the RC oscillator, more than two capacitors can be used. Further, features of the various embodiments may be combined in combinations that differ from those described above. Moreover, for clear and brief description, many descriptions of the systems and methods have been simplified. Many descriptions use terminology and structures of specific standards. However, the disclosed systems and methods are more broadly applicable.

[0050] Those of skill will appreciate that the various illustrative blocks and modules described in connection with the embodiments disclosed herein can be implemented in various forms. Some blocks and modules have been described above generally in terms of their functionality. How such functionality is implemented depends upon the design constraints imposed on an overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention. In addition, the grouping of functions within a module, block, or step is for ease of description. Specific functions or steps can be moved from one module or block without departing from the invention.

[0051] The various illustrative logical blocks, units, steps, components, and modules described in connection with the embodiments disclosed herein can be implemented or performed with a processor, such as a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of

microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Further, circuits implementing the embodiments and functional blocks and modules described herein can be realized using various transistor types, logic families, and design methodologies.

[0052] The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles described herein can be applied to other embodiments without departing from the spirit or scope of the invention. Thus, it is to be understood that the description and drawings presented herein represent presently preferred embodiments of the invention and are therefore representative of the subject matter which is broadly contemplated by the present invention. It is further understood that the scope of the present invention fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present invention is accordingly limited by nothing other than the appended claims.