Title:
READ OPERATION CIRCUIT, SEMICONDUCTOR MEMORY AND READ OPERATION METHOD
Document Type and Number:
WIPO Patent Application WO/2021/077780
Kind Code:
A1
Abstract:
Provided are a read operation circuit, a semiconductor memory and a read operation method. The read operation circuit comprises: a data determination module for reading read data from a storage block and determining, according to the number of bits of changed data between the previous read data and the current read data, whether to flip the current read data, so as to output global bus data to be transmitted by a global bus and flip flag data to be transmitted by a flip flag signal line; a data receiving module for determining, according to the flip flag data, whether to flip the global bus data, so as to output buffer data; a parallel-series conversion circuit for performing parallel-series conversion on the buffer data, so as to generate output data of a DQ port; and a data buffer module for determining an initial state of the global bus according to an enable signal and the current read data. By means of the technical solutions of the embodiments of the present application, the number of flips of an internal global bus can be reduced under a TriState architecture, thereby greatly compressing a current and reducing power consumption.
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Inventors:
ZHANG LIANG (CN)
Application Number:
PCT/CN2020/097410
Publication Date:
April 29, 2021
Filing Date:
June 22, 2020
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/409
Foreign References:
| CN210667806U | 2020-06-02 | |||
| CN102611951A | 2012-07-25 | |||
| CN101771497A | 2010-07-07 |
Other References:
See also references of EP 3926630A4
Attorney, Agent or Firm:
CHANG TSI & PARTNERS (CN)
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