Title:
RECEIVING APPARATUS
Document Type and Number:
WIPO Patent Application WO/2004/040836
Kind Code:
A1
Abstract:
A receiving apparatus (5000) has a common circuit (2) and three demodulator circuits (3A,3B,3C). The demodulator circuit (3A) has a second synchronization circuit (DLL) (30), a clock selecting circuit (SEL)(25), a sampling register (Sampler) (28), an alignment calculating circuit (Caliculator)(40), a decoding circuit (Decoder)(50), and a local buffer (BUF). The DLL (30) has a phase detector (PD), a LPF (32) and a voltage controlled delay circuit (VCD) (33). The other demodulator circuits (3B,3C) share the arrangement of the PD (31) and LPF (32) in the DLL (30) of the demodulator circuit (3A). This eliminates a necessity of providing the PD (31) and LPF (32) in the DLLs (30a) of the demodulator circuits (3B,3C) and hence reduces the circuit area.
Inventors:
OKAMURA JUN-ICHI (JP)
Application Number:
PCT/JP2003/013941
Publication Date:
May 13, 2004
Filing Date:
October 30, 2003
Export Citation:
Assignee:
THINE ELECTRONICS INC (JP)
OKAMURA JUN-ICHI (JP)
OKAMURA JUN-ICHI (JP)
International Classes:
H04L7/04; H03L7/07; H03L7/081; H04L7/033; H04L25/14; (IPC1-7): H04L7/033; H03M9/00
Domestic Patent References:
| WO2002065690A1 | 2002-08-22 |
Foreign References:
| JP2000031951A | 2000-01-28 | |||
| JPH1188447A | 1999-03-30 | |||
| JPH1198130A | 1999-04-09 | |||
| JPH0856240A | 1996-02-27 | |||
| JPH05244137A | 1993-09-21 |
Attorney, Agent or Firm:
Katayama, Shuhei (6-1 Kyobahi 1-chom, Chuo-ku Tokyo, JP)
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