CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 62/754,559 filed November 1, 2018, entitled,“RECONFIGURABLE PHASE ARRAY,” and claims priority to U.S. Patent Application No. 62/755,136 filed November 2, 2018, entitled,

“RECONFIGURABLE PHASE ARRAY,” both of which are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

[0002] Some communication systems have high bill of material (BOM) costs and problems with heat sinks. Some communication systems also have a large number of components on a circuit board. Some communication systems also are inefficient with energy and have a large physical size.

SUMMARY

[0003] Some embodiments of a method may include: transmitting a synchronization signal to a plurality of transceiver modules configured in an antenna array; and each transceiver module processing the synchronization signal and responsively aligning a phase of a receive carrier reference signal.

[0004] In some embodiments of a method, each transceiver module may include an injection locked oscillator (ILO) that locks to the synchronization signal.

[0005] With some embodiments of a method, the ILO may generate a local downconversion signal used to downconvert a desired received channel signal.

[0006] In some embodiments of a method, the ILO may generate a local time-to-digital- converter (TDC) reference signal used to synchronize a plurality of polar transceivers.

[0007] In some embodiments of a method, each transceiver module may include a plurality of polar receivers, wherein each polar receiver includes an injection locked oscillator that is tuned to lock onto the synchronization signal, and deviate according to modulation present in the desired received signal.

[0008] Some embodiments of a method may include: receiving a digital baseband signal at an array of transceiver modules, wherein each transceiver module may include a plurality of digital modulators; generating a transmit modulated signal from the digital baseband signal at each of the plurality of digital modulators and power amplifiers; and, combining the transmit modulated signals.

[0009] In some embodiments of a method, the transmit modulated signals may be combined with a Wilkinson combiner.

[0010] With some embodiments of a method, the transmit modulated signals may be combined as electromagnetic energy by connecting each power amplifier to one of a plurality of dipole antennas.

[0011] In some embodiments of a method, the plurality of dipole antennas may be arranged in an array.

[0012] For some embodiments of a method, one or more transceiver modules may be configured with a weighting factor used for beam forming.

[0013] Some embodiments of a method may include receiving a desired signal at an array of transceiver modules arranged on a panel array, each module positioned adjacent to an antenna element on the panel array, wherein each transceiver module may include a plurality of digital demodulators, and may include a baseband signal combiner; generating a demodulated baseband modulated signal from each of the transceiver modules; and combining the digital baseband signals at the panel array using the baseband signal combiners.

[0014] In some embodiments of a method, the signal combiners may be configured by a signal weighting factor.

[0015] In some embodiments of a method, the signal weighting factor may include a beam forming weight.

[0016] In some embodiments of a method, the beam forming weight may be a column weighting factor, a row weighting factor, or both.

[0017] Some embodiments of an apparatus may include: a plurality of transceiver modules configured in an antenna array; a synchronization transmission circuit configured to transmit a synchronization signal to the plurality of transceiver modules; a receive carrier generation circuit configured to generate a receive carrier reference signal; and a synchronization processing circuit configured to process the synchronization signal and to align a phase of the receive carrier reference signal. [0018] Some embodiments of an apparatus may include: a plurality of transceiver modules arranged in an array and configured to receive a digital baseband signal; a plurality of digital modulators and power amplifiers each configured to generate a transmit modulated signal from the digital baseband signal; and a combiner configured to combine the transmit modulated signals.

[0019] Some embodiments of an apparatus may include: a plurality of antenna elements on a panel array; a plurality of transceiver modules arranged on the panel array to be adjacent to one of the plurality of antenna elements and configured to receive a desired signal, wherein each transceiver module may include a plurality of digital demodulators, and includes a baseband signal combiner; a demodulation circuit configured to generate a demodulated baseband signal from each of the transceiver modules; anda combiner configured to combine the digital baseband signals at the panel array using the baseband signal combiners.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed invention, and explain various principles and advantages of those embodiments.

[0021] FIG. 1 is a schematic perspective view illustrating a matrix array of Software-Defined Radio (SDR) modules for an SDR system 100 according to some embodiments.

[0022] FIG. 2A is a graph of an example frequency response 200 illustrating an RF synchronization control signal positioned in the center of an OFDMA channel according to some embodiments.

[0023] FIG. 2B is a graph of an example frequency response 250 illustrating an RF synchronization control signal positioned at the edge of an OFDMA RF channel signal according to some embodiments.

[0024] FIG. 3 is a block diagram illustrating block circuit connections for I/Q receiver chain elements according to some embodiments.

[0025] FIG. 4 is a block diagram illustrating block circuit connections for polar receiver chain elements according to some embodiments. [0026] FIG. 5 is a block diagram illustrating block circuit connections for a transceiver with a power combiner for the Tx path components according to some embodiments.

[0027] FIG. 6 is a block diagram illustrating block circuit connections for a transceiver with the Tx RF signals combining in the air according to some embodiments.

[0028] FIG. 7 is a block diagram illustrating block circuit connections for an array of integrated Software-Defined Radio (SDR) modules according to some embodiments.

[0029] FIG. 8 is a schematic plan view illustrating an example configuration of dipoles superimposed with a 3x3 array of rectangular patches according to some embodiments.

[0030] FIG. 9 is a flowchart illustrating an example process for synchronizing a plurality of antenna array transceiver modules to align the phase of a receive carrier reference signal according to some embodiments.

[0031] FIG. 10 is a flowchart illustrating an example process for generating and combining a plurality of transmit modulated signals according to some embodiments.

[0032] FIG. 11 is a flowchart illustrating an example process for demodulating a plurality of received modulated signals and combining baseband signals according to some embodiments.

[0033] FIGS. 12A-12C are diagrams illustrating example configuration of configurable two- dimensional (“2D”) arrays according to some embodiments.

[0034] FIG. 13 is a diagram illustrating an example of a configurable 2D array showing a modified configuration.

[0035] FIG. 14 is an example chart illustrating an example variation in 3dB beamwidth as a function of angle of orientation for an example non-configurable array versus an example configurable array (e.g., a 2D array) according to some embodiments.

[0036] FIG. 15 is an example diagram showing an antenna array portion of an example configurable array as well as an example detail of an example variable transceiver element of the antenna array according to some embodiments.

[0037] FIG. 16 is an example diagram showing a zoomed in view of the antenna array portion of FIG. 15 according to some embodiments.

[0038] FIG. 17 is an example diagram showing a zoomed in view of the example transceiver element of FIG. 15 according to some embodiments. [0039] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

[0040] The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

[0041] The entities, connections, arrangements, and the like that are depicted in— and described in connection with— the various figures are presented by way of example and not by way of limitation. As such, any and all statements or other indications as to what a particular figure“depicts,” what a particular element or entity in a particular figure“is” or“has,” and any and all similar statements— that may in isolation and out of context be read as absolute and therefore limiting— may only properly be read as being constructively preceded by a clause such as“In at least one embodiment, ...” For brevity and clarity of presentation, this implied leading clause is not repeated ad nauseum in the detailed description of the drawings.

DETAILED DESCRIPTION

[0042] FIG. 1 is a schematic perspective view illustrating a matrix array of Software-Defined Radio (SDR) modules for an SDR system 100 according to some embodiments. FIG. 1 shows an example 4x8 matrix of SDR modules 104 on a circuit board 106. Some embodiments have other matrix configurations of SDR modules 104. Each SDR module may include a 4x4 matrix of sub-array transceiver elements. For some embodiments, an SDR module 104 may include a tunable radio digital-to-analog converter (DAC)/analog-to-digital-to-analog converter (AD AC), an RF switch (time division duplex (TDD) and frequency division duplex (FDD)), a digital power device (DPD), a power amplifier for each sub-array set of transceiver elements.

[0043] A MIMO transceiver circuit board 106 may include an RF antenna 102 according to some embodiments. The RF antenna 102 may be used to transmit a synchronization control signal to each SDR module 104. The synchronization control signal may be a signal that is transmitted with a center carrier frequency near the center of a desired receive channel. For some embodiments, the synchronization control signal may be an information signal that is used to determine the oscillator frequency for injection locked oscillator circuits associated with each SDR module 104.

[0044] Some embodiments may have the oscillator circuit integrated with each SDR module 104, and some embodiments may have part of the oscillator circuit external to an SDR module 104. In some embodiments, one RF antenna 102 is attached to a MIMO circuit board 106 or a housing associated therewith. Some embodiments of the MIMO circuit board 106 may have multiple RF antennas 102, such as, for example, one RF antenna 102 in multiple comers of the MIMO circuit board 106. For example, the MIMO circuit board 106 may have an RF antenna 102 in each comer. A subset of the matrix of SDR modules may be assigned to each RF antenna 102

[0045] For some embodiments, a row or column of the matrix array of SDR modules 104 may be used to perform beam-forming. For example, a row of eight SDR modules 104 may be used to create a phased-array transmit beam. An oscillator circuit associated with each SDR module 104 may use amplitude and phase and/or in-phase (I) and quadrature (Q) weightings to account for propagation delays, timings, and/or other geometries between the location of an RF antenna 102 and the antenna(s) used by each SDR module 104.

[0046] With some embodiments, a calibration routine may be used to determine relative propagation delays for each SDR module 104. Some embodiments may use a run-time calibration routine that may continually adjust weightings. Some embodiments may use a calibration routine that configures weightings at power-up time. With some embodiments, a calibration look-up table may be used for a particular configuration of a circuit board 106.

[0047] FIG. 2A is a graph of an example frequency response 200 illustrating an RF synchronization control signal positioned in the center of an OFDMA channel according to some embodiments. The frequency response of an orthogonal frequency division multiple access (OFDMA) receive (Rx) signal 202 is shown in FIG. 2A for a particular channel. An synchronization control signal 204 may have a center carrier frequency that is nearly equal to a center carrier frequency of the OFDMA Rx signal 202 for a channel.

[0048] FIG. 2B is a graph of an example frequency response 250 illustrating an RF control signal positioned at the edge of an OFDMA RF channel signal according to some embodiments. Similar to FIG. 2A, the frequency response of an OFDMA Rx signal 252 is shown in FIG. 2B for a particular channel. An oscillator control signal 254 may have a center carrier frequency equal to a frequency associated with the channel, such as a frequency near the bottom of the OFDMA channel. Some embodiments may have an oscillator control signal transmitted using a center carrier frequency in-between (for example) the examples shown in FIGs. 2A and 2B. Some embodiments may have an oscillator control signal transmitted using a center carrier frequency higher or lower the than the center carrier frequency of the oscillator control signals 204, 254 shown in FIGs. 2A and 2B.

[0049] FIG. 3 is a block diagram 300 illustrating block circuit connections for I/Q receiver chain elements according to some embodiments. An oscillator control signal may be transmitted by an RF antenna 320, which may be common to one or more SDR modules, and received by an oscillator circuit antenna 318. The RF antenna 320 of FIG. 3 may be the same as the RF antenna 102 of FIG. 1 for some embodiments. The received oscillator control signal may be received by an input to an injection locked oscillator (ILO) or phase-locked loop (PLL) circuit 308. Some embodiments of the SDR module 322 may have a common ILO/PLL circuit 308. For some embodiments, a linear noise amplifier (LNA) may inject the received signal into an oscillator sub-circuit. Oscillator control signals with phases of 0 and 90 degrees may be output by the oscillator sub-circuit. These 0 and 90 degree phase signals may be used by mixers associated with the respective I and Q circuit elements for each receive chain sub-module 302, 304, 306.

[0050] With some embodiments of a receive chain sub-module 302, 304, 306, an RF antenna associated with a receive chain sub-module 302, 304, 306 may receive an OFDMA signal transmitted by an external transmitter / antenna 316. The external transmitter 316 may be a cell phone tower Tx antenna or a Tx antenna attached to a satellite, for example. The OFDMA receive signal may propagate through an LNA and be split into I and Q path phase signals. Each I and Q path phase signal may be mixed with the oscillator control signals with phases of 0 and 90 degrees, respectively to generate I and Q signals for each receive chain sub-module 302, 304, 306.

[0051] For some embodiments, each receive chain sub-module 302, 304, 306 may output I and Q signals that are input to a combiner 310. While FIG. 3 shows three receive chains sub- modules 302, 304, 306, some embodiments of an SDR module 322 may have 8, 16, or another quantity of receive chain set of elements. The combiner 310 may receive combiner row and column weights. For some embodiments, a complex multiply may be performed by the combiner 310 or the multiply accumulator 312. For example, an example combiner output signal may be calculated as shown in Eqn. 1.

where r = 0, ... , N-l for N sets of receive chains; w _Ir = the combiner I weight for a receive chain r; and W _Qt = the combiner Q weight for a receive chain r. For some embodiments, row and column combiner weights may be received by the combiner 310 from a control bus 314, and a matrix of Combined, _Q values may be outputted by the combiner 310 and sent to the multiply accumulator (MAC) 312. The matrix of Combined, _Q values may be calculated using a matrix of respective row and column weights received by the control bus 314.

[0052] The MAC 312 may receive a summation of I signals (å,). a summation of Q signals (Sr), and/or a summation of I and Q signals (å _{/ Q} ) for some embodiments. The MAC 312 also may receive a set of MAC row and column weights. The MAC 312 may perform a complex multiply and accumulation similar to Eq. 1 for a set of MAC weights in some embodiments. The MAC 312 may perform separate I and Q multiplications and accumulations for separate rows and columns according to some embodiments. The MAC 312 may output row and column accumulations that may be sent to the control bus 314. For some embodiments, the MAC accumulator outputs may correspond to distributed phase array signals or distributed beamform signals.

[0053] FIG. 4 is a block diagram 400 illustrating block circuit connections for polar receiver chain elements according to some embodiments. An oscillator control signal may be transmitted by an RF antenna 420, which may be common to one or more SDR modules, and received by a receive chain’s antenna. The RF antenna 420 of FIG. 4 may be the same as the RF antenna 102 of FIG. 1 for some embodiments. For each receive chain sub-module 402, 404, 406, the received oscillator control signal may propagate through a linear noise amplifier (LNA) and be injected into an injection lock oscillator (ILO) circuit. The oscillator control signal may have a central carrier frequency that is substantially similar to a center frequency of a MIMO Rx channel. The ILO circuit may use the oscillator control signal received from a MIMO transceiver circuit board RF antenna 420 as part of a process to lock an oscillator associated with a receive chain sub-module 402, 404, 406. The ILO circuit may output phase and amplitude path signals for each receive chain sub-module 402, 404, 406. The ILO circuit output signals may be received by a time to digital converter (TDC) for the phase and amplitude paths. A TDC synchronization circuit 408 may receive synchronization signals from a control bus 414 for some embodiments. The TDC synchronization circuit 408 may send a synchronization signal to each TDC circuit associated with each receive chain sub-module 402, 404, 406 to synchronize the timing of TDC signals. Each receive chain sub-module 402, 404, 406 may have TDC circuits to generate phase information and amplitude information.

[0054] In some embodiments, the TDC uses the example technology described in U.S. Patent Application Serial No. 15/488,278, entitled“TIME TO DIGITAL CONVERTER WITH INCREASED RANGE AND SENSITIVITY,” filed on April 14, 2017, and incorporated by reference herein. Other implementations may be used for the TDC.

[0055] For some embodiments of a receive chain sub-module 402, 404, 406, an RF antenna associated with a receive chain sub-module 402, 404, 406 may receive an OFDMA signal transmitted by an external transmitter / antenna 416. The external transmitter 416 may be a cell phone tower Tx antenna or a Tx antenna attached to a satellite, for example. The OFDMA receive signal may propagate through an LNA and may be mixed with an ILO output signal to shift the OFDMA receive signal down to baseband, for some embodiments. Phase and amplitude information may be extracted from an ILO circuit output signal. Phase and amplitude path signals may be received by a time-to-digital converter (TDC) for the phase and amplitude paths. A TDC synchronization circuit 408 may receive synchronization signals from a control bus 414 for some embodiments. The TDC synchronization circuit 408 may send a synchronization signal to each TDC circuit associated with each receive chain sub-module 402, 404, 406 to synchronize the timing of TDC signals. Each receive chain sub-module 402, 404, 406 may have TDC circuits to generate phase information and amplitude information for each receive chain sub-module 402, 404, 406.

[0056] For some embodiments, output signals of the TDC synchronization circuit 408 may be time-to-digital conversion (TDC) synchronization signals. Such TDC synchronization output signals may be received by TDC processing circuits for each receive chain sub-module 402, 404, 406 and processed to adjust the phase output signal of each receive chain sub-module 402, 404, 406. The phase of each transceiver module’s phase output signal may be adjusted so as to align the phase of a receive carrier reference signal.

[0057] Some embodiments of the receive chain sub-module 402, 404, 406 (or transceiver module, such as the transceiver module 104 of FIG. 1), may include an injection-locked oscillator (ILO) that locks to the TDC synchronization circuit’s synchronization output signal. The ILO of each receive chain sub-module 402, 404, 406 (or transceiver module) may generate a local downconversion signal that may be used to downconvert a desired received channel signal. For example, an LNA of a transceiver module may receive a modulated RF signal via an antenna, and the LNA may generate an output signal that is mixed with the ILO output signal. The local downconversion signal may be used to control the ILO so that the output of the mixed ILO signal is a downconverted signal for the desired received channel signal.

[0058] For some embodiments, the ILO may generate a local time-to-digital-converter (TDC) reference signal that may be used to synchronize a plurality of polar transceivers. For example, the local TDC signal of each receive chain sub-module 402, 404, 406 (or transceiver module) may be used to generate an output signal of each transceiver module’s TDC processing circuit that may be used to synchronize receive signals received by each receive chain sub-module 402, 404, 406 (or transceiver module).

[0059] With some embodiments of the transceiver module, each transceiver module may include a plurality of polar receivers (such as receive chain sub-modules 402, 404, 406), wherein each polar receiver may include an injection-locked oscillator (ILO) that is tuned to lock onto the synchronization signal and adjust (or deviate) according to modulation present in the desired received signal.

[0060] A combiner 410 may receive phase and amplitude signals for each receive chain sub- module 402, 404, 406. The combiner 410 also may receive row and column weights from the control bus 414. While FIG. 4 shows three receive chains sub-modules 402, 404, 406, some embodiments of an SDR module 422 may have 8, 16, or another quantity of receive chain set of elements. The combiner 410 may receive combiner row and column weights. For some embodiments, amplitude and phase information may be converted into I and Q information. The conversion from amplitude and phase to I and Q may be performed with a CORDIC circuit, which may be internal to the combiner 410 for some embodiments. Some embodiments may use the I and Q information to calculate accumulated I and Q values, which may be similar to Eq. 1. For some embodiments, a complex multiply may be performed by the combiner 410 or the multiply accumulator 412. For some embodiments, row and column combiner weights may be received by the combiner 410 from a control bus 414, and a matrix of Combined, _Q values may be outputted by the combiner 410 and sent to the multiply accumulator (MAC) 412. The matrix of Combined, _Q values may be calculated using a matrix of respective row and column weights received by the control bus 414. For some embodiments, a signal combiner may be configured with a signal weighting factor. The signal weighting factor may be communicated to the combiner 410 with the combiner row weight in and combiner column row weight in signals. The signal weighting factor may be communicated to the MAC 412 with the MAC row weight in and MAC column weight in signals. With some embodiments, the signal weighting factor may include a beam forming weight. The beam forming weight may be a column weighting factor, a row weighting factor, or both a row and a column weight factor for some embodiments.

[0061] The MAC 412 may receive a summation of I signals (å _/ ), a summation of Q signals (SrC and/or a summation of I and Q signals for some embodiments. The MAC 412 also may receive a set of MAC row and column weights. The MAC 412 may perform a complex multiply and accumulation, e.g., similar to Eq. 1 for a set of MAC weights in some embodiments. The MAC 412 may perform separate I and Q multiplications and accumulations for separate rows and columns according to some embodiments. The MAC 412 may output row and column accumulations that may be sent to the control bus 414. For some embodiments, the MAC accumulator outputs may correspond to distributed phase array signals or distributed beamform signals. Some embodiments may sum amplitude and phase information separately without performing a complex multiplication.

[0062] FIG. 5 is a block diagram illustrating block circuit connections for a transceiver 500 with a power combiner for the Tx path components according to some embodiments. FIG. 5 shows an example configuration of an SDR module 504 with up to 8 transmit chain of elements and 1 receive chain of elements. Some embodiments of an SDR module 504 may include a different quantity of transmit and receive chains of elements.

[0063] For some embodiments, a Tx signal with phase information may be received by a phase circuit 510 for each transmit chain. A phase lock loop (PLL) circuit 512 may generate a signal to inject into a digital power amplifier (DP A) 508 for each transmit chain. Each transmit chain’s DPA 508 may generate an amplified and modulated output signal using the phase and PLL input signals. Each transmit chain’s amplified and modulated output signal may be injected into a power combiner. Each SDR module 504 may contain a power combiner 506. The digitally combined power signal may be transmitted by the transceiver via an RF antenna 502 associated connected to the SDR module 504.

[0064] For some embodiments, the power combiner 506 may be a Wilkinson combiner, and transmit modulated signals may be combined with the Wilkinson combiner. With some embodiments, the transmit modulated signals may be combined as electromagnetic energy (which may occur in the air between a transmitter and a receiver, for example) by connecting each power amplifier (such as the output of each digital power amplifier (DP A) 508) to one of a plurality of dipole antennas (such as the dipole antenna 502). For some embodiments, one or more transceiver modules (or transmit chain elements, which may include a DPA 508, a phase circuit 510, and a PLL circuit 512) may be configured with a weighting factor used for beam forming. The power combiner 506 (or a transceiver module 504) may receive weighting factors, such as row and column weight factors, that may be used to adjust power levels for beam forming of transmit signals.

[0065] In some embodiments, an Rx signal may be received by an RF antenna 502 associated with an SDR module 504. Some embodiments of a receive chain of components may have a linear noise amplifier (LNA) 514 that receives a modulated RF signal on an SDR module’s 504 RF antenna 502. The output of the LNA 514 may injected into a mixer 516 and mixed with a PLL signal to generate an Rx path input signal. The output of the ILO 516 may be received by an analog to digital converter (ADC) 518. The ADC 518 may generate a receive output signal (RX).

[0066] FIG. 6 is a block diagram illustrating block circuit connections for a transceiver 600 with the Tx RF signals combining in the air according to some embodiments. FIG. 6 shows an example configuration of an SDR module 604 with up to 8 transmit chain of elements and 8 receive chains of elements. Some embodiments of an SDR module 604 may include a different quantity of transmit and receive chains of elements.

[0067] For some embodiments, a Tx signal with phase information may be received by a phase circuit 610 for each transmit chain. A phase lock loop (PLL) circuit 612 may generate a signal to inject into a digital power amplifier (DPA) 608 for each transmit chain. Each transmit chain’s DPA 608 may generate an amplified and modulated output signal using the phase and PLL input signals. Each transmit chain’s amplified and modulated output signal may be transmitted by an RF antenna 602. Some embodiments may have a separate RF antenna 602 per transmit/receiver chain pair.

[0068] In some embodiments, an OFDMA modulated signal may be received by an RF antenna 602 associated with an SDR module 604. Some embodiments of a receive chain of components may have a linear noise amplifier (LNA) 614 that receives a modulated RF signal on an SDR module’s 604 RF antenna 602. The output of the LNA 614 may injected into a mixer 616 and mixed with a PLL signal to generate an Rx path input signal. The output of the ILO 616 may be received by an analog to digital converter (ADC) 618. The ADC 618 may generate a receive output signal (RX). Each SDR module 604 may contain a power combiner 606 that may be used to combine each receive chain’s Rx signal (RX0, RX1, ... , RX7) to generate a combined RX signal. The digitally combined RX signal may be connected to other components on a transceiver circuit board.

[0069] FIG. 7 is a block diagram illustrating block circuit connections for an array of integrated Software-Defined Radio (SDR) modules 700 according to some embodiments. A phased array system may combine an RF modulated signal through weighting and summation of signals (such as I and Q receive data or amplitude and phase receive data). Each SDR module 702, 704, 706, 708 may include an integrated multiply-accumulator (MAC) to enable distributed combining. Such a configuration may enable scalability of a transceiver. Some embodiments may use different quantities of SDR modules 702, 704, 706, 708.

[0070] FIG. 8 is a schematic plan view illustrating an example dipole configuration 800 with dipoles superimposed with a 3x3 array of rectangular patches according to some embodiments. FIG. 8 shows a configuration of staggered dipoles 802 and a 3x3 array of rectangular patches 804. A single microstrip patch 804 may be replaced with three planar dipole elements 802 that may fit within a similar size area as a single microstrip patch 804. For some embodiments, planar dipole elements may be used instead of microstrip patches. With some embodiments, a triplet of dipoles may be used per SDR module. Some embodiments may different sets of dipoles to adjust spacing between dipoles, such as to increase isolation between dipoles for example.

[0071] For some embodiments, a transmit modulated signal may be transmitted using a plurality of dipoles 802 connected to a transceiver module (such as the transceiver module 104 of FIG. 1) or a transmit chain sub-module, such as a transmit chain of elements shown in FIG. 5 (which may include a DPA 508, a phase circuit 510, and a PLL 512). With some embodiments, the plurality of dipoles 802 may be arranged as an array 804.

[0072] FIG. 9 is a flowchart illustrating an example process 900 for synchronizing a plurality of antenna array transceiver modules to align the phase of a receive carrier reference signal according to some embodiments. For some embodiments, a method may include transmitting 902 a synchronization signal to a plurality of transceiver modules configured in an antenna array. Each transceiver module may process 904 the synchronization signal and responsively align a phase of a receive carrier reference signal. For example, the synchronization signal may be a time-to-digital conversion (TDC) synchronization signal as shown in FIG. 4. Such a TDC synchronization may be received by each module and processed to adjust the phase output signal of each receive chain sub-module (or transceiver module).

[0073] FIG. 10 is a flowchart illustrating an example process for generating and combining a plurality of transmit modulated signals according to some embodiments. A method 1000 may include receiving 1002 a digital baseband signal at an array of transceiver modules, wherein each transceiver module may include a plurality of digital modulators. The method 1000 also may include generating 1004 a transmit modulated signal from the digital baseband signal at each of the plurality of digital modulators and power amplifiers. The method 1000 may further include combining 1006 the transmit modulated signals, such as with a power combiner. The combined signal may be transmitted via an RF antenna.

[0074] FIG. 11 is a flowchart illustrating an example process 1100 for demodulating a plurality of received modulated signals and combining baseband signals according to some embodiments. A method 1100 may include receiving 1102 a desired signal at an array of transceiver modules arranged on a panel array, with each module positioned adjacent to an antenna element on the panel array, wherein each transceiver module may include a plurality of digital demodulators, and may include a baseband signal combiner. The method 1100 also may include generating 1104 a demodulated baseband modulated signal from each of the transceiver modules. The method 1100 may further include combining the digital baseband signals at the panel array using the baseband signal combiners, such as the digital combiner of FIG. 6.

[0075] In some embodiments, 2 dimensional configurable arrays are used to provide variable beam characteristics. In some embodiments, the 2D configurable array may have four sub arrays in a 2x2 sub-array configuration. More generally, other embodiments having N x N configurable arrays or N ² sub-arrays are presented in which one or more sub-arrays of the N x N sub-arrays may be a sub-array of variable transceivers that may shift between being, e.g., a temporarily dedicated sub-array of receivers or a temporarily dedicated sub-array of transmitters. One or more of the sub-arrays of the N x N configurable arrays may be a non variable sub-array of transmitters while one or more other sub-arrays of the N x N configurable arrays or sub-arrays may be anon-variable sub-array of receivers. In some examples according to some embodiments, the N x N configurable array including N ² sub-arrays is a 2 x 2 configurable array (N=2, 2 ² = 4 sub-arrays). In some embodiments, the N x N configurable array including N ² sub-arrays may be, for example, for a 3 x 3 configurable array (3 ² = 9 sub arrays) or a 4 x 4 configurable array (4 ² = 16 sub-arrays). That is, N=3, N=4.

[0076] In some embodiments, a 2D configurable array may include four sub-arrays total, with separate transmit (Tx) and receive (Rx) sub-arrays. In some embodiments, thousands of Tx, Rx, or variable transceiver (Tx/Rx) elements may be split between sub-arrays. The spacing of elements in the transmit array is set to be substantially equal to one half the wavelength of the transmit frequency. The spacing of elements in the receive array is set to be substantially equal to one half the wavelength of the receive frequency. In one non-limiting example in accordance with some embodiments, 4050 elements may be used across four sub-arrays. In a further non limiting example in accordance with some embodiments, a Tx sub-array may be designed to include 1225 elements, which an Rx sub-array may be designed to include 780 elements and remaining variable (e.g., Tx/Rx, Rx, or Tx, depending on how configured) sub-arrays may be designed to include around 1000 elements, e.g., a compromise between potentially more optimal element spacing for the Tx and Rx sub-arrays, respectively. These element values and proportions relative to individual sub-arrays are merely examples, and other element values and relative proportions across arrays may be used.

[0077] In some embodiments, a circular array of transceiver elements may be used. Such a circular array may generally exhibit a constant beam width as a function of phi angle. While a circular array might provide an advantage of more constant beam width in transmission and/or reception as a phi angle changes, the area for the circular array may prove less efficient in some implementations.

[0078] Phi angle may be generally a difference in orientation between an axis of the reconfigurable array and the targeted transceiver, such as a satellite transponder for purposes of transmission and/or reception. As phi angle changes, absent configurability, a corresponding change in beamwidth may typically accompany large changes in the orientation angle. Configurability may be used advantageously in some embodiments to adaptively maintain a constant beamwidth as phi angle changes, as shown in, e.g., FIG. 14, described in more detail below. In some embodiments, a configurable array may be adapted for use in a variety of orbits and satellite altitudes above the earth’s surface, including GEO (Geostationary Equatorial Orbit), LEO (Low Earth Orbit), MEO (Medium Earth Orbit), and GSO (Geosynchronous Orbit). [0079] In some embodiments, a configurable (e.g., reconfigurable) array may be used. In some embodiments, processing may be used to adaptively configure (e.g., or reconfigure) sub-arrays within a configurable array (e.g., a 2D configurable array) or elements within sub-arrays, potentially presenting additional complexity when compared with, e.g., circular array embodiments. In some embodiments, a configurable array such as a 2D configurable array may be configured to provide a generally constant beam width as a function of, e.g., phi angle. In some embodiments, a rectangle panel may be optimized for azimuth and elevation resolution. In some embodiments, a controller receives location information of an intended transceiver (such as a satellite transponder), including azimuth information. In some embodiments, positional information of the array may be obtained from global positioning satellites, and a relative azimuth to a desired satellite may be calculated. The controller also receives array orientation information, which may correspond to heading information from an aircraft on which the array is mounted. The controller may then responsively configure the sub arrays to achieve a desired beamwidth in the direction towards the intended transceiver.

[0080] As a non-limiting example, the following figures will be described with respect to an example two dimensional (2D) configurable array (a 2 x 2 configurable array with 2 ² = 4 sub arrays) according to some embodiments.

[0081] According to the example, a 2D configurable array may be broken up into four sub arrays. In some embodiments, each sub-array may have an element spacing (e.g., a number of Tx, Rx, or Tx/Rx elements within a particular sub-array), e.g., optimized for either Tx, Rx, or a compromise spacing to accommodate Tx and Rx. In some embodiments, the compromise spacing may be used for variable sub-arrays. A variable sub-array may be designed to adaptively change from a receiver sub-array (Rx sub-array as part of an Rx array) to a transmitter sub-array (Tx sub-array as part of a Tx array).

[0082] One potential application for, e.g., configurable arrays is in air travel and specifically in aircraft communication with one or more satellites, e.g., GEO level orbiting satellites. As the orientation of an aircraft changes with respect to one or more satellites that the aircraft’s on board wireless communications may be in communication with, the power requirements to maintain that communication may change due to the variation in the beamwidth. In accordance with some embodiments, N dimensional configurable arrays such as 2D configurable arrays having, e.g., adaptive processing, may be advantageously utilized to adaptively maintain a constant beamwidth (or relatively more constant beamwidth) as an aircraft’s orientation changes (e.g., a phi angle change) relative to one or more satellites.

[0083] In some embodiments, a particular configurable array configuration used in, e.g., aircraft, may vary with the orientation and heading of the aircraft. In some embodiments, a system level approach may be used in which a configurable array may obtain location and heading information to allow for beamwidth optimization in relation to the satellite constellation. The radio-frequency integrated circuits (RFICs) used in the configurable array may be generally required to quickly re-configure between Rx operation and Tx operation.

[0084] FIGS. 12A-12C are diagrams illustrating example configuration of configurable two- dimensional (“2D”) arrays according to some embodiments.

[0085] A configurable 2D array 1200 is shown in FIG. 12A. An example 2 x 2 array includes four sub-arrays in which, for some embodiments, one sub-array is dedicated for reception (Rx) with antenna element spacings optimized for reception, one sub-array is dedicated for transmission (Tx) with antenna element spacings optimized for transmission, and two sub arrays have antenna element spacings suitable for both transmit and receive operation. The intermediate element spacing sub-arrays are configurable for Tx and Rx, and are referred to herein as“variable sub-arrays”. The configuration (e.g., a Tx or an Rx configuration) of the variable sub-arrays may be changed based on orientations and headings relative to, e.g., satellite(s). For some embodiments, the variable sub-arrays may have about 1000 elements per sub-array. The sub-array with spacings optimized for Rx may have about 780 elements for some embodiments, while the sub-array with spacings optimized for Tx may have about 1225 elements for some embodiments, although these values are merely examples, and other spacings may be used.

[0086] FIG. 12B shows an example configuration of sub-arrays such that the two sub-arrays on the left are configured as a Tx array, and the two sub-arrays on the right are configured as an Rx array. FIG. 12C shows an example configuration of sub-arrays such that the top two sub arrays are configured as an Rx array, and the bottom two sub-arrays are configured as a Tx array. In other words, the variable sub-arrays may be configured such that the Tx and Rx arrays are vertical (FIG. 12B) or horizontal (FIG. 12C) for some embodiments.

[0087] FIG. 13 is a diagram illustrating an example of a configurable 2D array showing a modified configuration. [0088] FIG. 13 shows two example configurations of an example 2 x 2 configurable 2D array. As stated above, a 2D array may be N x N, but a 2x2 array is used here by way of example. The left side of FIG. 13 shows the sub-arrays configured for vertical Tx and Rx arrays, while the right side of FIG. 13 shows the sub-arrays configured for horizontal Tx and Rx arrays. The vertical Tx and Rx array configuration of sub-arrays may be used if satellites are oriented in a vertical orientation. Likewise, the horizontal Tx and Rx array configuration of sub-arrays may be used if satellites are oriented in a horizontal orientation for some embodiments. A vertical Tx and Rx array configuration may be used with an oval beamwidth that is longer in the horizontal direction for some embodiments. A horizontal Tx and Rx array configuration may be used with an oval beamwidth that is longer in the vertical direction for some embodiments.

[0089] In some embodiments, an aspect ratio of the switching array may be designed to better align a narrow beamwidth with satellite alignment. In some embodiments, a beam width used in, e g., Rx and Tx communication may vary based on, e.g., an orientation of the configurable array.

[0090] FIG. 14 is an example chart illustrating an example variation in 3dB beamwidth as a function of angle of orientation for an example non-configurable array versus an example configurable array (e.g., a 2D array) according to some embodiments. Example chart 1400 plots“scan angle” (e.g., phi angle) versus the beamwidth at 3 dB for two example arrays: an example non-configurable array and an example configurable 2D array according to some embodiments. For the non-configurable array and the configurable array, as scan angle (e.g., phi angle) increases from 0 degrees to 90 degrees, the 3 dB beamwidth stays generally steady (beginning at 1.9 degrees beamwidth) until around 43 degrees (at or around 2.3 or 2.4 degrees 3 dB beamwidth). From that, the behavior at increasing scan angle (e.g., phi angle) begins to deviate between the example non-configurable and configurable arrays. The beamwidth of non-configurable array expands to a beamwidth of roughly 3.7 degrees. At the same time, the behavior and performance of the example configurable array essentially maintains a relatively constant bandwidth despite increasing scan angle (e.g., phi angle), creating a mirror image of its performance from scan angle 0 degrees to 45 degrees in the range of increasing scan angle from 45 degrees to 90 degrees. In some embodiments, this behavior and performance is achieved by way of adaptive configurability of the configurable array at or around (or toward) a scan angle (e.g. Phi angle) of 45 degrees. The adaptive configurability (by way, e.g., of the variable subarrays shifting from a temporarily dedicated function (e.g., Rx or Tx) to another temporarily dedicated function (e.g., correspondingly Tx or Rx) and vice versa results in consistent beamwidth behavior and performance.

[0091] As an example with reference to FIGS. 12A-12C, assume that 2D configurable array 1200, 1230, 1260 includes two variable sub-arrays (top left and bottom right, respectively) and a Tx sub-array (bottom-left) and an Rx sub-array (top-right). In FIG. 12B, corresponding (say) to scan angle 0 to 45 degrees in the example chart 1400 of FIG. 14, the Tx sub-array at bottom- left forms a (vertical) Tx array with the top-left variable sub-array (here acting as a Tx sub array), while the Rx sub-array at top-right forms a (also vertical) Tx array with the bottom- right variable sub-array (here acting as an Rx sub-array).

[0092] As, e.g., the scan angle approaches and begins to increase past 45 degrees, the 2D configurable array 1230 of 12B begins to shift in operation to resemble the 2D configurable array 1260 of FIG. 12C, such that the Tx and Rx arrays shift in direction from vertical to horizontal. The Tx and Rx arrays are also composed of different variable sub-arrays, respectively, such that (1) the variable sub-array at top-left here now acts as an Rx sub-array and now forms a horizontal Rx array with the Rx sub-array at top-right, and (2) the variable sub-array at bottom-right here now acts as a Tx sub-array and now forms a horizontal Tx array with the Tx sub-array at bottom-left.

[0093] In some embodiments, a transition of a variable sub-array from, e.g., Tx to Rx or Rx to Tx may be abrupt, such as on a symbol by symbol basis at a particular transition point or scan angle (e.g., phi angle). In some embodiments, a transition of one or more variable sub-arrays in operation from, e.g., Tx to Rx or Rx to Tx may occur gradually, or may occur prior to an abrupt transition point. In some embodiments, some or all of individual elements of the variable sub-array may be configured as transceiver elements that can switch from Tx to Rx based on adaptive processing. In some embodiments, one or more transceiver elements of a particular variable sub-array may be configured to transmit and receive simultaneously. In some embodiments, a first set of transceiver elements of a particular variable sub-array may transmit (or receive) while another second set of transceiver elements of the same particular variable sub-array may receive (or transmit) at the same time. For example, in some embodiments, if the first set of transceiver elements is located in proximity to a non-variable Tx sub-array, that first set of transceiver elements might switch to transmit sooner or switch from transmitting later than a second set of transceiver elements located in proximity to a non variable Rx sub-array, such that the second set of transceiver elements might switch to receive sooner or switch from receiving later than the first set of transceiver elements. Any number of combinations and designs for the variable sub-arrays is possible and contemplated by the present disclosure.

[0094] FIG. 15 is an example diagram 1500 showing an antenna array portion of an example configurable array as well as an example detail of an example variable transceiver element of the antenna array according to some embodiments. In some embodiments, the example antenna array portion is part of a variable sub-array that includes transceiver elements. The left side of FIG. 15 shows the antenna array portion with multiple transceiver elements, while the right side of FIG. 15 shows one example circuit implementation of a transceiver element. The antenna array portion (e.g., a portion of a variable sub-array) with multiple transceiver elements will be discussed in more detail with FIG. 16, while an example transceiver element will be discussed in more detail in FIG. 17.

[0095] FIG. 16 is an example diagram showing a zoomed in view of the antenna array portion of FIG. 15 according to some embodiments. In some embodiments, the example antenna array portion is part of a variable sub-array that includes transceiver elements. The antenna array portion 1600 may include multiple transceiver elements. Rx signals may be received via a plurality of antenna patch elements. Rx signals may be daisy-chained together and communicated between each transceiver element via an Rx serial bus. A DSP may be connected to the Rx serial bus and may receive a summed Rx signal that has been weighted and summed by each transceiver element. Modulated Tx signals may be received by each transceiver element from a DSP via the Tx serial bus. Control data may be received by each transceiver element from a DSP to control the Rx and Tx circuit elements within each transceiver element. Weighted and summed Rx signals may be in I and Q format for some embodiments. Weighted and summed Rx signals also may be in polar format for some embodiments. Similarly, modulated Tx signals may be in I and Q format for some embodiments and in polar format for some embodiments.

[0096] FIG. 17 is an example diagram showing a zoomed in view of the example transceiver element of FIG. 15 according to some embodiments. FIG. 17 shows one example circuit implementation of a transceiver element 1700. The example transceiver element 1700 may have separate serial data buses for Rx, Tx, and control data. Rx and Tx signals may be received by the transceiver element 1700 as shown on the left side of FIG. 17. Rx and Tx weightings also may be received by the control data input shown on the left side of FIG. 17, Serialized/deserialized (SERDES) circuit elements may be used to convert between serial and parallel input data. Rx and Tx weightings may be in complex I and Q (in-phase and quadrature) format for some embodiments. Rx and Tx weightings also may be in polar (amplitude and phase) format for some embodiments. Control data also may include time delay settings. Time delay settings and Tx weightings may be configured to enable a plurality of transmitter circuit elements to be arranged for beamforming for communication with one or more satellites. Similarly, time delay settings and Rx weightings may be configured to enable a plurality of receiver elements to be arranged to receive an array of modulated signals from a satellite. RF signals may be received from a satellite via a patch element. The received signal may go through a duplexer and be received at the input to the Rx circuit element shown in FIG. 17. The Rx circuit element may be controlled by data received on the control serial bus input line. The output of the Rx element may be weighted and summed with Rx data received on the Rx serial bus input line. An adjustable delay may be configured to delay Rx signal data received by the Rx serial bus. Summed Rx signals may be processed by a SERDES circuit element to convert the de-serialized Rx signal data into serial data format. The Rx serial bus data may be outputted via the Rx serial bus output. Similarly, modulated Tx signal data may be received by the Tx serial bus input. The modulated Tx signal data may be inputted into the Tx circuit element. The Tx circuit element may be controlled by data received by the control data bus. The output of the Tx circuit element may be weighted in I and Q format for some embodiments. Some embodiments may weight the output of the Tx circuit element in polar format. Weighted Tx signals may be sent to the duplexer and transmitted to a satellite via the patch element.

[0097] Some embodiments may therefore comprise an apparatus having a plurality of antenna elements arranged in at least four adjacent groups of array elements on a panel array, the first group of elements having an inter-element spacing based on a transmit signal wavelength, a second group of elements having an inter-element spacing based on a receive signal wavelength, and a third and fourth group of elements having an inter-element spacing based on a wavelength between the transmit signal wavelength and the receive signal wavelength. The embodiment includes a plurality of transmitter modules arranged on the panel array and each configured to transmit desired signals from the antenna elements in the first group of elements and a selected one of the third and fourth groups of elements; and a plurality of receiver modules arranged on the panel array and each configured to receive desired signals from antenna elements in the second group of elements and a selected other one of the third and fourth groups of elements. [0098] In some embodiments, each transmitter module and receiver module are combined as a transceiver module thereby forming a plurality of transceiver modules. Furthermore, the at least four adjacent groups of array elements on the panel array are arranged in four quadrants of a rectangle, or perhaps a a circular or oval array of elements. The first group of elements is laterally adjacent to the third and fourth groups, and the second group of elements is laterally adjacent to the third and fourth groups such that the first group of elements and second group of elements are not laterally adjacent. That is, the spacing of elements in the transmit array is set to be substantially equal to one half the wavelength of the transmit frequency, and the spacing of elements in the receive array is set to be substantially equal to one half the wavelength of the receive frequency, with those two sub arrays being positioned in opposite quadrants, and not adjacent quadrants. In this way, the first group of elements may be selectively paired with either the third or fourth group of elements, and the second group of elements may be selectively paired with a remaining fourth or third group of elements, respectively.

[0099] Some embodiments comprise a method of: selecting a transmit array of antenna elements having a first group of elements having an inter-element spacing based on a transmit signal wavelength, and a laterally adjacent third group of elements having an inter-element spacing based on a wavelength between the transmit signal wavelength and a receive signal wavelength; selecting a receive array of antenna elements having a second group of elements having an inter-element spacing based on the receive signal wavelength, and a laterally adjacent fourth group of elements having an inter-element spacing based on a wavelength between the transmit signal wavelength and the receive signal wavelength; transmitting desired signals from the transmit array; receiving desired signals from the receive array; and, dynamically reconfiguring the transmit array to include the first group of elements and the fourth group of elements and dynamically reconfiguring the receive array to include the second group of elements and the third group of elements, and transmitting and receiving desired signals from the reconfigured transmit and receive arrays.

[0100] Some embodiments of a method may include: transmitting a synchronization signal to a plurality of transceiver modules configured in an antenna array; and each transceiver module processing the synchronization signal and responsively aligning a phase of a receive carrier reference signal. [0101] In some embodiments of a method, each transceiver module may include an injection locked oscillator (ILO) that locks to the synchronization signal.

[0102] With some embodiments of a method, the ILO may generate a local downconversion signal used to downconvert a desired received channel signal.

[0103] In some embodiments of a method, the ILO may generate a local time-to-digital- converter (TDC) reference signal used to synchronize a plurality of polar transceivers.

[0104] In some embodiments of a method, each transceiver module may include a plurality of polar receivers, wherein each polar receiver includes an injection locked oscillator that is tuned to lock onto the synchronization signal, and deviate according to modulation present in the desired received signal.

[0105] Some embodiments of a method may include: receiving a digital baseband signal at an array of transceiver modules, wherein each transceiver module may include a plurality of digital modulators; generating a transmit modulated signal from the digital baseband signal at each of the plurality of digital modulators and power amplifiers; and, combining the transmit modulated signals.

[0106] In some embodiments of a method, the transmit modulated signals may be combined with a Wilkinson combiner.

[0107] With some embodiments of a method, the transmit modulated signals may be combined as electromagnetic energy by connecting each power amplifier to one of a plurality of dipole antennas.

[0108] In some embodiments of a method, the plurality of dipole antennas may be arranged in an array.

[0109] For some embodiments of a method, one or more transceiver modules may be configured with a weighting factor used for beam forming.

[0110] Some embodiments of a method may include receiving a desired signal at an array of transceiver modules arranged on a panel array, each module positioned adjacent to an antenna element on the panel array, wherein each transceiver module may include a plurality of digital demodulators, and may include a baseband signal combiner; generating a demodulated baseband modulated signal from each of the transceiver modules; and combining the digital baseband signals at the panel array using the baseband signal combiners. [0111] In some embodiments of a method, the signal combiners may be configured by a signal weighting factor.

[0112] In some embodiments of a method, the signal weighting factor may include a beam forming weight.

[0113] In some embodiments of a method, the beam forming weight may be a column weighting factor, a row weighting factor, or both.

[0114] Some embodiments of an apparatus may include: a plurality of transceiver modules configured in an antenna array; a synchronization transmission circuit configured to transmit a synchronization signal to the plurality of transceiver modules; a receive carrier generation circuit configured to generate a receive carrier reference signal; and a synchronization processing circuit configured to process the synchronization signal and to align a phase of the receive carrier reference signal.

[0115] Some embodiments of an apparatus may include: a plurality of transceiver modules arranged in an array and configured to receive a digital baseband signal; a plurality of digital modulators and power amplifiers each configured to generate a transmit modulated signal from the digital baseband signal; and a combiner configured to combine the transmit modulated signals.

[0116] Some embodiments of an apparatus may include: a plurality of antenna elements on a panel array; a plurality of transceiver modules arranged on the panel array to be adjacent to one of the plurality of antenna elements and configured to receive a desired signal, wherein each transceiver module may include a plurality of digital demodulators, and includes a baseband signal combiner; a demodulation circuit configured to generate a demodulated baseband signal from each of the transceiver modules; anda combiner configured to combine the digital baseband signals at the panel array using the baseband signal combiners.

[0117] In the foregoing specification, specific embodiments have been described. However, one of ordinary skill in the art would appreciate that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings. [0118] The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

[0119] Moreover, in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “has,” “having,” “includes,” “including,”“contains,”“containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by“comprises ... a”,“has ... a”,“includes ... a”,“contains ... a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms“a” and“an” are defined as one or more unless explicitly stated otherwise herein. The terms “substantially”,“essentially”,“approximately”,� �about”, or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non- limiting embodiment the term is defined to be within 10%, in another embodiment within 5%, in another embodiment within 1% and in another embodiment within 0.5%. The term “coupled” as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is“configured” in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

[0120] It will be appreciated that some embodiments may comprise one or more generic or specialized processors (or “processing devices”) such as microprocessors, digital signal processors, customized processors and field programmable gate arrays (FPGAs) and unique stored program instructions (including both software and firmware) that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of the method and/or apparatus described herein. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used.

[0121] Accordingly, some embodiments of the present disclosure, or portions thereof, may combine one or more processing devices with one or more software components (e.g., program code, firmware, resident software, micro-code, etc.) stored in a tangible computer-readable memory device, which in combination form a specifically configured apparatus that performs the functions as described herein. These combinations that form specially programmed devices may be generally referred to herein as“modules.” The software component portions of the modules may be written in any computer language and may be a portion of a monolithic code base, or may be developed in more discrete code portions such as is typical in object-oriented computer languages. In addition, the modules may be distributed across a plurality of computer platforms, servers, terminals, and the like. A given module may even be implemented such that separate processor devices and/or computing hardware platforms perform the described functions.

[0122] Moreover, an embodiment can be implemented as a computer-readable storage medium having computer readable code stored thereon for programming a computer (e.g., comprising a processor) to perform a method as described and claimed herein. Examples of such computer- readable storage media include, but are not limited to, a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory) and a Flash memory. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.

[0123] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.