RECONFIGURABLE PROCESSING ELEMENT ARRAY FOR ZERO-BUFFER PIPELINING, AND ZERO-BUFFER PIPELINING METHOD

WIPO Patent Application WO/2022/126621

A1

A reconfigurable processing element array for zero-buffer pipelining, and a zero-buffer pipelining method. In a reconfigurable processing element array (PEA) for zero-buffer pipelining, data transmission between processing elements (PE), read and write of a local register (LR) in the PE by the PE, and access of the PEA to a global register (GR) and a shared memory (SM) in the PEA do not pass through a first-in first-out (FIFO) memory, static scheduling of calculation operators is performed on a reconfigurable processor by using configuration information that includes the number of pause cycles, and a starting time of a PE corresponding to each calculation operator is determined on the basis of the number of pause cycles, such that zero-buffer pipelining is realized. By means of software definition of configuration information, the number of pause cycles is used, such that overheads of FIFO are omitted, thereby reducing delay of data transmission and processing, and thus also greatly improving the efficiency of data transmission and data processing.

YIN SHOUYI (CN)
XIE SIMIN (CN)
GU JIANGYUAN (CN)
ZHONG MING (CN)
LUO LIE (CN)
ZHANG SONG (CN)
WANG ZHI (CN)
HAN HUIMING (CN)
LIU LEIBO (CN)
WEI SHAOJUN (CN)

PCT/CN2020/137677

June 23, 2022

December 18, 2020

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UNIV TSINGHUA (CN)

G06F5/06; G06F15/78

CN109597646A	2019-04-09
CN104615474A	2015-05-13
CN102298568A	2011-12-28
CN107168708A	2017-09-15
CN101630275A	2010-01-20
CN102214157A	2011-10-12
US6507947B1	2003-01-14

BEIJING SANYOU INTELLECTUAL PROPERTY AGENCY LTD. (CN)

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