Title:
REFERENCE CLOCK DUTY RATIO CALIBRATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/237366
Kind Code:
A1
Abstract:
Disclosed in the present invention is a reference clock duty ratio calibration circuit, comprising a low-noise low-dropout regulator, an oscillation circuit, a duty ratio adjustment circuit and a duty ratio calibration circuit. The duty ratio detection circuit of the reference clock duty ratio calibration circuit detects the duty ratio of a reference clock signal outputted by the duty ratio adjustment circuit, and when it is determined that the duty ratio of the reference clock signal deviates from a preset duty ratio, the duty ratio detection circuit adjusts the amplitude of the output signal thereof, and the duty ratio of the reference clock signal outputted by the duty ratio adjustment circuit is adjusted by means of the output voltage of the digital-to-analog conversion circuit and the output voltage of the low-noise low-voltage differential regulator. The reference clock duty ratio calibration circuit of the present invention can be used to effectively reduce the noise of the reference clock, improving the communication performance.
Inventors:
YANG YI (CN)
MIN QING (CN)
CHEN DONGHAI (CN)
MIN QING (CN)
CHEN DONGHAI (CN)
Application Number:
PCT/CN2018/091691
Publication Date:
December 19, 2019
Filing Date:
June 15, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03K5/156
Foreign References:
| US20140125390A1 | 2014-05-08 | |||
| CN106961261A | 2017-07-18 | |||
| CN106656122A | 2017-05-10 | |||
| US8471644B2 | 2013-06-25 |
Other References:
See also references of EP 3809594A4
Attorney, Agent or Firm:
SCIHEAD IP LAW FIRM (CN)
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