The present in.ven.tion geiieialiy relates to the Lie^i < n' twitched mode power supplies {sometimes iei erred to as switch mode power supplies or switching mode power suppl i -r<) and more specifically to the generation, of -< ι> f 01 ence voltage by a fly-buck, converter for use in control of a switched mode power supply,

[Background]

The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency, for example in personal computers and portable electronic devices such as cell phones. A SMPS achieves these advantages by switching one or more switching elemen s such as power MOSFETs at. a high, frequency (usually tens to hundreds of kHz) , with the frequency or duty cycle of the switching being adjusted by a feedback loop (also widely referred to as a "compensation 1oop" or "feedback circuit" ) to convert an input voltage to a desired output voltage . An SMPS may take the for of a rectifier (AC/DC converter) , a DC/DC converter, a frequency changer (AC/AC) or an inverter (DC/AC) ,

Increasing dynamic requirements, such as monotonic start-up, recovery af er short-circuit, load transient performance, have led to the relocation of the control circuits of many modern isolated switched mode power supplies from the primary side to the secondary side of the SMPS. When the control circuit is on the secondary side of the isolation barrier, some means of powering i from the primary side needs to be provided, and the input voltage needs to be monitored, accurately, since it is used in the control of the mai converter of the SMPS .. The control circuit of an isolated SMPS is of e powered via an auxiliary (or 'housekeeping' ) converter. There are numerous of ways of designing such an auxiliary converter. For example. Fig. 1 provides a schematic illustration, of an SMPS 11 comprising a main converter 12 for converting an input voltage V _in to an output ge V _out , a drive circuit 15 for driving the converter 12, a controller 16 for controlling the drive circuit 15 (for example, by controlling the switching duty cycle or the switching of one o more switching elements , such as field-effect sistors {FETs) , in the drive circuit 15} and thus the operation of the main converter 12, and an auxiliary converter 17 for down-converting the input voltage V _in to a voltage suitable for powering the controller 16. Such an auxiliary converter 17 may supply power to the primary side circuits of the SMPS 11 and provide an isolated power supply to secondary side circuits of the

SMPS 11. The auxiliary converter 17 may also send information about the input voltage V _in to secondary side circuits, such as controller 16, which i formation may be used fo voltage feed- forward in an SMPS controlled from the secondary side, or for setting a reference voltage in a switched mode power supply being controlled in the regulated ratio (RR) mode or the hybrid regulated ratio (HRR) mode, as described in WO 2012/116750· Al and WO 2013/113354 Al, for example,

The main converter 12 is an isolated DC-DC converter, typically down-converting the input voltage V _in to a suitable output voltage

V _ouc for powering the load of the SMPS 11. The main converter 12 may typically operate with an input or output voltage range of 10- 100 V.

The auxiliary converte 17 may be provided, in the form of a fly- buck converter . Figure 2 illustrates an isolated fly-buck converter, which can be used as the auxi 1 iary converter 17 in the SMPS of Fig. 1. The fly-buck convc ;Lei is conf J gin d to convert the input voltage V _ln to a secondary side output voltage v _s , and comprises a primary winding ¾, a non- isolated buck C _p» and a pair of switches Q _: , Q ₂ on a primary side of the converter. A secondary winding X _2» a first capacitive element C _s , and a first rent i i ying " 1 i.-ment Ό _ι are provided on the secondary side of the converter . hile isolated t 1 y 1 ii-'k converters typically have a transformer ratio between the ' ■' r:- < tr.J secondary windings of 1:1, t told- 1 ί f cct transistors, which may be used in controller 16, usually require lower voltages. Therefore, a suitable converter ratio for the isolated f ly - back converter may be 1 : 0 , 75.

The non- isolated buck C _p (which may be provided in the form of a capacitor, for exampe) is connected in series with the primary winding X _l and the pai of switching lents Q _lf Q ₂ (e.g. FETs such as MOSFETs) arranged in the primary side circuit. The switching elements Q _lt Q ₂ are configured to switch such that , d ring a forward phase of operation of the isolated fly-buck converter, the primary winding Χ _χ and the non- isolated buck C _p are connected to the input voltage V _in and, during a fly-buck phase of operation of the isolated fly-buck converter, the primary winding X _x and the non-isolated buck C _P are disconnected from the input voltage and are connected to one another in a closed circuit. The switching of the switching elements Q _x , Q ₂ may be controlled by a switching controller (not illustrated} .

The secondary winding X ₂ is elect omagnetically coupled to the primary winding X _x . The first capacitive element C _s , which may be provided in the form of a capacitor, is connected over the secondary winding X ₂ . The first rectifying element D ₁ , which may be provided in the form of a diode , is connected to the secondary winding X ₂ and the first capacitive element C _s so as to prevent current f om flowing through the secondary winding X ₂ to charge/discharge the first capacitive element C _s during the forward phase of operation of the fly-buck converter. The output voltage V _s of the fly-buck conv>>i * corresponds to the voltage over the first capacitive element C _s .

A modi f ir.d ^ rm of the above- described fly-buck converter, which allows a if lin lt measurement of the input vol age to be made on the secondary side, is described in WO 2n ί 5/13785Γ! Λ1 , The circuit diagram of this modified fly-buck converter is illustrated in Fig. 3.

As shown in Fig. 3 _» the modi f ied fly-buck converter is additionally provided with an input voltage sensing circuit for generating a vol age V _sen9e that is indicative of the input vol age V _in . The input voltage sensing circuit comprises a second capacitive element C _F (e.g. implemented as a capacitor) and a second rectifying element D ₂ (e.g. implemented as a diode) that are connected in series . The input voltage sensing circuit is connected over the secondary wiring X ₂ such that the second, rectifying element D ₂ prevents current from flowing through the input voltage sensing circuit during the fly-buck phase... The sum of the voltage V _F over the second capacitive element C _F and the output vol age V _g is the sensed measure V _sense on the secondary side , which is indicative of the input voltage V _in on the primary side. The input voltage sensing circuit may, as in the example of Fig . 3 , comprise a resistive element R ₃ connected in series with the second capacitive element C _F and the second rectifying element D ₂ , the resistive element R ₃ serving to reduce current spikes during charging of the second capacitive element C _F , thereby producing a less noisy voltage over second capacitive element C _p .

To further explain the operation of the modified fly-buck converter shown in Fig. 3 , the relation between the sensed voltage ^v sense ^{and the} inpu voltage V _in will be derived in the case where the primary winding X _v has one winding and the secondary winding X ₂ is taken to have n windings. Steady- state switching with a duty cycle D, a small ripple current in the windings, and a small vol age ripple in the capacitances are also assumed .

Du ing the forward phase, wherein the switching element Q ₁ is conducting and the swi ching element Q ₂ is off, he fly-buck. converter- of Fig . 3 can be simplified to the circuit diagram shown in Fig . 4a, since the rectifying element D, becomes nonconducting . For simplicity, the resistive element R _} is removed during this analysis.

The voltage over the inductor can be stated directly on the primary side as

V L - V _m - V _P , Equation 1 o , using the reflected voltage over the second capacitive element V _p on the primary side , as

Vp + V _D

y — _i ¹ ± Equation 2

¹ n where V _D is the vol age drop ove the diode D ₂ in the forward direction.

During the fly-buck phase , the fly-buck converter of Fig. 3 can be simplified to the circuit diagram shown in Fig . 4b.

The voltage over the primary winding X _: can be stated directly on the primary side as

V _L = -V _Pt Equation 3 or, using the reflected output voltage V _s on. the primary side, as

¾ + v ₀

V , i Equation 4

n where V ₀ is the voltage drop over the diode Ό ₁ in the forward direction.

For the non- isolated buck voltage V _p , the vol -second balance using Equa ions 1 and 3 becomes Equation 5 where he forward phase duration is equ l to the duty cycle D, and the fly-buck duration is (1 - D) = D ' , Solving Equation 5 for V _p yields

V _P = DV _in . Equation 6

For the isolated fly-buck, the volt -second balance using Equations 1 and 4 becomes

D(V _ln - V _p ) + D' {- ^Vs = 0. Equation 7

Collecting terms on eac side yields

DV _in = DV _P + D and using Equation 6 yields

V _p = DVp+D ^l — -.

n 11 a ting V _p on the b-tt hand side and using (1 - D) = D ' yields

Dividing this by D ' on both sides and solving for V _s yields

V _s = nV - V _[} , 8

For he isolated forward-buck, the volt-second balance using Equations 2 and 3 becomes j)!LL _{+ £>'} _ _! ¾ ₌ Q. Equation s n

Solving Equa ion 1 for D' { -V _p > and replacing in Equation 9 yields

Solving for V _F yields

V _F n(V _in - V _P ) - V _D . Equation 10

The sensed voltage V _sense indicative of the input voltage V _in is the sum of the voltages V _s and V _F , and using Equations 8 and 10 yields

V _smse = V _s + Vp = nV _P - V _D + n(V _ln - V _P ) - V _D , and collecting terms yields V _sense = nV _in - 2V _D . Equation 11

Hence, the. sensed voltage V _8er , _8e is linear in the input voltage "V _j _ _n and offset by two diode forward voltages V _D . Since the input voltage V _in times the ratio n is much greater than 2V _D , Equation 11 can be simplified to

%ense ^¾ · Equal ion 12

The diode voltage drops can be reduced using Schottky diodes or can even be eliminated by using synchronous rectification,

The sensed voltage V _sense indicative of the input voltage V _in and sensed on the isolated secondary side can be used in the cont ol of the mai converter 12 of the switched mode power supply 11.

The controller 16 of the switched mode power supply 11 may thus be cfd ; >JJ * ·? 3 to rec -' v- the sensed voltage V _8en8e , or a voltage indicative thereof, from the isolated secondary side of the auxiliary converter 11, i.e. the above-described fly-buck converter, and to control the drive circuit 15 and thus he voltage conversion, performed by the main converter 12 on the basis of the sensed vol age V _senae .

The sensed vol age V _ser , _se , as measured on the secondary side, may then be used for voltage feedforward control in a secondary-side controlled switched mode power supply . Alternatively or additionally, the sensed voltage V _sense may be used for setting the reference voltage in a regulated ratio or hybrid regulated ratio controlled swi ched mode power supply .

Fig . 5 illustrates another isolated fly-buck converter disclosed in WO 2015/137852, which is an extension of the converter of Fig . 3 and may be used for hybrid regulated ratio (HRR) control in the switched mode power supply of Fig . 1.

The isolated fly-buck converter of Fig . 5 comprises, on the secondary side , a voltage divider including two serially-connected. resis ive elemen s , R., and R ₂ , that are connected in parallel over the first and second capacltive elements C _s and, C _F to divide the sensed voltage V _sensje . A fourth capacltive element, {which, may be provided in the form of a capacitor! _» and a voltage reference (voltage- limiting element) V _{re f} are connected in parallel over one of he resistive elements of the voltage divider (namely, R _x ) , wherein a voltage V _R over the voltage reference V _ref changes with a time constant that is dependent upon the fourth capacltive lament C _] . The voltage V _R is usable as a hybrid regulated ratio reference in hybrid regulated ratio (HRR5 control of the main converter 12,

In the fly-buck converter of Fig, 5, the voltage V _{sen8e ¾} nV _in is divided using the potential divider comprising R _l and. R ₂ , and a time constant is set by the capacitor C ₁ . The reference voltage is saturated using a high, recision voltage reference V _ref , yielding the vol age for hybrid regulated ratio as

' ^V "f Equat ⁱ on where s is a complex f equency, the regulated ratio input voltage par has the gain G _RR of

«1

Equation l + «2 and the time constant. ¾„ becomes

_{¾fi = Cl} J?^. Equation 15 [Summary]

The present inventors have recognised that accurate sensing of, and the ><b 1 - t t. con f i qui e increasing and decreasing slew rates of, the voltage V _R is important for proper control of an SMPS ,

More par icularly, the inventors have recognised tha , with known converter of Fig . 5, for a given capacitor C _lt it is not possible to configure a slew rate of reference signal V _R without also having to modify the gain G _RR for generating reference signal V _R .

Therefore, where the required voltage range of the reference signal V _R is defined by the recipient circuit of the reference signal, it is not possible to conI inure the slew rate of the reference signal at all . Furthermore, in the fly-buck converter of Fig, 5, the increasing and decreasing slew rates of voltage v _R are both defined by the potential divider comprising R _:1 and R2 , and capacitor C ₁ , and so the increasing and decreasing slew rates cannot be independen ly configured . In view of the above problems , the inventors have devised an isolated fly-buck converter for converting an input voltage to an output voltage , and generating a voltage indicat ive of the input vol age . The isolated fly-buck converter comprises a primary side circuit comprising a primary winding and a non- isolated buck connected in series , and switching elements arranged in the primary side circuit and configured to switch such that , during a forward phase o operation of the isolated fly-buck converter, the primary winding and the non- isolated buck, are connected to the input voltage and, during a fly-buck phase of operation of the isolated fly-buck converter, the primary winding and the nonisolated buck are disconnected from the input voltage and are connected to one another in a closed circuit . The isolated fly- buck converter further comprises a secondary side circuit comprising a secondary winding coupled to the primary winding, a first capacitive element connected across the secondary winding, and a first rectifying element that is connected to the secondary winding so as to prevent current flowing hrough the secondary winding during the forward phase, wherein the output voltage is the voltage across the first capaci ive elemen . The secondary side circuit further comprises an input voltage sensing circuit for generating the voltage indicative of the input voltage, the input voltage sensing circuit comprising a second capacitive element and a second rectifying element connected in series, the input voltage sensing circuit being connected across the secondary winding such tha the second rectifying dement prevents current f r :i",\ flowing through the input voltage sensing circuit during the fly-buck phase. The input voltage sensing circuit further comprises a voltage buffer arranged to buffer a voltage, which is indicative of a sum of the voltage over the second capacitive clement and the output voltage, and to output the butt red voltage or a voltage based on the buffered voltage as the voltage that is indicative of the input voltage, wherein the output of the voltage buffer is connected to ground via a first resistive element in series with a parallel combination of a second resistive element and a third capacitive element.

The inventors have further devised a switched mode power supply comprising an isolated fly-buck controller as set out above, The inventors have yet further devised a base station comprising an isolated fly- buck controller or a switched mode power supply as set out above .

[Brief Description of the Drawings]

Embodiments of the invention will now be explained in detail, by way of example only, with reference to the accompanying figures, in which: Fig. 1 illustrates functional components of a conventional switched mode power supply; Fig ^, 2 11 lustratf M «, conventional isolated fly-buck converter.

Fig. 3 trates a second conventional isolated fly-buck converte ..

Pigs. 4a and 4b show circuit diagrams which the isolated fly-buck converter of Pig. 3 can be considered to simplify to during the forward and fly- buck phases of opera ion, respectively.

Fig . 5 illustrates a fly-buck converter based on the converter shown in Fig . 3 , which may be used for hybrid regulated ratio control i the switched mode power supply of Fig, 1, Fig. 6 shows a circuit diagram of an isolated fly-buck converter according to an embodiment of the present invention; and

Fig . 7 is a schematic illustration of a base station comprising a switched mode power supply according to an embodiment of the present invention.

[Detailed Description of Embodiments]

Figure 6 shows the circuit diagram of an isolated fly-buck converter 100 according to an embodiment of the present invention, which is configured to convert an input voltage ¥ _in to an output voltage Vg on the secondary side , and generate a voltage V _R that is indicative of the input voltage V _in . The isolated fly-buck converter 100 may form part of a switched mode power supply as shown in Fig. 1 _» which also includes a main converter 12 (e.g. a DC-DC converter) configured to convert the input voltage V _in to an output voltage V _out of the switched mode power supply 11 by switching one or more switching elements (e.g. FETs such as MOSFETs) , and a controller 16 arranged to control the operation of the main converter 12, including the conversion performed by the main converter 12» by controlling the switching of the switching element (s) on the basis of a control signal . in this embodiment, the isolated fly-buck conver er 100 functions as he auxiliary converter 17 for powering the controller 16 using output voltage V _s . The isolated fly-buck converter 100 is preferably configured to also provide the contulUr 16 with the control signal, this being the reference voltage V _R that the isolated fly-buck converter 100 generates . Alternatively, in other embodiments, the voltage V _R generated by the isolated fly-buck converter may be provided to a sample and hold circuit that extracts data representative of the inpu voltage signal V _in , which may then be used for control of the operation of the main converter 12 by the controller 16, or for other purposes. The reference voltage V _R is indicative of the input voltage V _in , as will be explained in the following.

Referring agai to Fig . 6 , the isolated fly-buck converter 100 may, for illustrative: purposes only, be considered to be formed of three parts, i.e. 100A, 1003 and lOOC.

Part 100A of the fly-buck converter 100 is the same as the fly- buck converter described above with reference to Fig . 3, and the layo and functionality of its circuit will therefore not be described again here.

Part lOOC of the isolated fly-buck converter 100 comprises a voltage buffer 110, which is arranged to buffer a voltage v ^" _in _ _div that is indicative of the sensed voltage V _sense {this being a sum of the voltage V _F over the second capacitive element Cp and the output vol age V _s ) , and to output the buffered voltage as the voltage V _R that is indicative of the input voltage V _in . The voltage buffer 110 may, as in the pi >sent embodiment, comprise an operational amplifier 112 provided with a feedback circuit that is arranged to feed back an output voltage of the voltage buiit-t 110 to an inverting input of the operational amplifier 112. The non- inver ing input of the operational amplifier is arranged to receive a fraction of the voltage V _3ense that is set by the values of resistors R _x and R ₂ forming a potential divider in part 10GB of the converter 100. A third resistive element r may, as in the present embodiment, be provided in the feedback circuit of the operational amplifier 112, between the output of the voltage L i i no and the inverting input of the operational amplifier 112.. The · r serves to prevent, or at least mitigate, any voltage offset problems which may arise . The output of the voltage buffer 110 is connected to ground via a first resistive element R _slew in series with a parallel combination of a second resistive element R _t and. a third capacitive element C _t . The rate of charging and discharging of capacitive element C _t through the first and second resistive elements R _glew and R _t defines slew rates for the voltage V _R . When, the fly-buck converter is inactive, the second resistive element R _t provides a discharge path for the third capacitive element C _t .

The voltage buffer 110 may, as in the present embodiment, further comprise a third rectifying element D ₃ arranged to connect the output of the opera ional amplifier 112 to the first resistive element H. _s i _ew so as to prevent current from flowing from the voltage buffer liO to the first resistive element R _slew . In this embodiment, third rectifying element D ₃ is arranged between the output of the operational amplifier 112 and a terminal for reading the voltage V _R , as shown in Fig . 6. Accordingly, when the third rect i fying element D ₃ is biased to prevent current from flowing through R _8lew , the voltage V _R does not depend on V _8enge , and only depends on the voltage across the third capacitive element C _t . As the third rectifying element D ₃ is arranged as par of the feedback circui of the voltage buffer 110 in this embodiment, then when the third rectifying element D ₃ is reverse biased to prevent current flow, there is no feedback in the buffer, and the non-conducting state is maintained until voltage V _R becomes equal to or greater han the voltage V _in . _dlv through the charging of t capacitive element C, .

With the combined effects of the voltage buffer 110 and the fi st and second resistive elements R _s i _ew and R _t , the voltage V _R follows the buffered voltage ν _1η .^ _1ν with a regulated ratio response according to he following equation {neglecting the small offset over R _elew ) ;

Equation 16 where the time constant R _R = C _t . Equation 17

^K t ^{+ K} slew

In embodiments like the present that include the third rectifying element D ₃ , the rectifier prevents the third capacitive element C _t from being charged by the voltage buffer 110. Therefore, in embodiments where the third rectifying element D ₃ is included in the input voltage sensing circuit, it may be necessary to introduce an alternative means for charging the third capacitive element C _t . This may be achieved by arranging the second resistive element R _t and the third capacitive element C _t such that they are connected to ground in parallel with the first capacitive element C _s . This connection may, as in the present embodiment, be achieved, by the input voltage sensing circuit further comprising a fourth resist Lve element, R _ramp , connecting the I n n capacitive element

C _s to the first resistive element R _slew the second resistive element R _t and. the third capacitive element C _t , as shown in Fig. 6.

When the charge in third capacitive element C _t , and therefore the voltage V _R , decrease following a decrease of the input voltage V _in , current t ! ws through both the first resistive element R _g i _ew and the fourth resistive element R _ratnp , and so the third capacitive element C _t discharges with a time constant that is dependent on both the first and fourth sistive elements R _alew and R _ram p. On the other hand, due to third rectifying element D ₃ , when the third capacitive element C _t charges following an increase in the i put voltage v, _n , current flows through the fourth resistive element R _ramp but not through the first lement R _8jew , and so the third capaciti e element C _t charges with a time constant that is dependent upon the fourth resistive element R _raiB p but not dependent upon the first resistive element R _s i _ew - Therefore, by choosing appropriate resistance values for the first and fourth resistive elements R _s i _ew and R _rarp , the fly-buck converter 100 may be configured such that the voltage V _R responds to changes in the input voltage V _i with different rising and falling slew rates that may be set independen ly of one another. Additionally, the fourth resistive element R _raTT , _p may be adjusted to control an initial charging time of the third capacitive element C _t , which is dependent upon, the ratio between the resistances of fourth resistive element R _ramp and first resistive element R _slew . The value of R _raMp may therefore be set to achieve a required initial ramp-up time of voltage V _R .

The isolated, fly-buck converter 100 may, as in the present embodiment further comprise a voltage reference D _re£ connected in parallel with the second resistive element R _t and the third capacitive element C _t , The voltage reference D _ref functions as a voltage -limiting element and is hereafter referred to as such. The voltage- limiting element D _ref may, for example, comprise a Zener diode. A converter with a voltage- limiting element D _ref may, for example, be used in order to operate an SMPS comprising the isolated fly-buck converter 100 in a Hybrid Regulated Ratio (HRR) mode. The output voltage V _out of the SMPS is provided with a regulated ratio be ween the input voltage V _ln and output voltage

V _out when the input voltage V _in is in a first voltage range, and is provided independently from the input voltage V _in when the input voltage V _in is in a second, higher voltage range. When V _in is in the second voltage range, the third rectifying element D ₃ limits the current through the voltage limiting ' 1 orient D _ref .

Operating in HRR mode (and neglecting the fourth resistive component R _rarnp , and the offset across the first resistive component R _s]ew for simplicity) , the voltage V _R will follow V _in in a regulated ratio mode until it reaches a voltage V _ref , which is defined by the voltage-limi ing element D _ref . If V _in increases beyond this level _. , V _R will not vary in regulated ratio mode but will instead remain, at V _ref until ¥ _in falls below this level again.

This variation of V _R may be expressed as follows

Equation 18

As noted above , a potential divider (part 10OB) may be provided between parts 10OA and. iOOC, and may, as in the present comprise a combination of wo serially-connected resistive elements R and

R ₂ , the combination being connected in parallel across the first and second capacitive elements C _s and C _F of part 10OA so as to conver the voltage V _sense to a lowered voLtaqt, V _in . _div , In this embodiment, this lowered voltage is then provided to part lOOC as the voltage which is indicative of a sensed voltage V _sense , and the voltage buffer 110 is arranged to buffer the lowered voltage V _in . div ·

With this potential divider, the voltage V _R is defined by the following formula :

nV _ln , V _ref ], Equatic

H _t + K _siew where s is a complex frequency, the regulated ratio input voltage part has t e gain G _RR of

Q — _n ———— , Equation 20

«1 + «2 ' and. the time constant t _m becomes

¾« = ^C _t o . o · Equation 21

^K t ^* Kslew

This embodiment therefore differs from the known converter of Fig. 5 {which follows Equations 13 to 15) at least by the gain G _RR and time constant t _RR being independently configurable for a given capacitor C _t , and so the gain and time constant may be set to values required by a recipient circuit of voltage V _R , such as the controller 16 of an SNIPS 11, and the SMPS may be properly controlled.

The isolated fly-buck converter according to an embodiment of the present Invention, or an SMPS having the same (as described above ) , may find numerous applications, and may, in particular, 13 serve as a power supply 11* for a base sta ion 21 in a telecommunications network, as illustrated in Fig . 7.

{ odifications and Variations]

Many modifications and variations can be made to he embodiments described above .

For example, in the above embodiment, the third rectifying element D ₃ is arranged between the voltage buffer 110 and a terminal where the voltage is measured . However, in other embodiments, the third rectifying d ode D ₃ may be arranged between the terminal where the voltage V _R is measured and the first reni stive element R _siew . In these alternative embodiments, when the third rectifying element D ₃ is preventing current from flowing, the voltage V _R does not depend upon the voltage across the third capacitive element C _t , and only depends on V _sense . Therefore , depending on where the third rectifying element D ₃ is placed in the circui , it may have the effect either of delaying a response of the voltage V _R to an increase in the input voltage V _in , by isolating the voltage V _R from

Vsense , or of eliminating any delay in such circumstances , by isolating the voltage V _R from, the third capacitive element C _t .

Additionally,, in the embodiment described above , the isolated f ly- buck converter 100 comprises a voltage limiting- element D _ref . However, in other embodiments, vol age limiting element D _ref may be omitted. Such embodiments may, for example , be used in order to operate an SMPS comprising the isolated fly-buck converter in a Regulated Ratio (RR) mode , in which the output voltage V _out of the SMPS is provided with a regulated ratio between the input voltage V _in and the output voltage V _out for all values of input voltage

V _in . Furthermore, in the embodiment described above, the output of the voltage buffer 110 is taken to provide the voltage V _R tha is indicative of the input voltage V _in , However, in other embodiments, a vol age other than the buffered voltage, which is nevertheless based on the bu fered vol age , may be outpu by the input voltage sensing circuit as the voltage V _R that is indicative of the input voltage ¥ _in »