REGISTER ARCHITECTURE AND REGISTER BLOCK OF RISC ARCHITECTURE PROCESSOR, AND RISC ARCHITECTURE PROCESSOR

WIPO Patent Application WO/2023/226802

A1

The present invention relates to the technical field of processors. Disclosed are a register architecture and a register block of an RISC architecture processor, and the RISC architecture processor. The register architecture is provided with 32 register spaces, comprising eight special-purpose registers and 24 general-purpose registers, wherein the 24 general-purpose registers are used for being provided for a processor to execute general-purpose read-write operations on the general-purpose registers according to instructions of the general-purpose registers, and the eight special-purpose registers are used for being provided for the processor to execute conditional judgment, jump operations, or arithmetic operations on the special-purpose registers according to specified instructions. Therefore, the types of processor instruction set conditional judgment/jump instructions can be reduced, the types and the number of instructions specially used for processing flag bits and calculation results exceeding bit width are reduced, the implementation difficulty and costs of processor hardware design are reduced, the performance of the processor for executing the conditional judgment, jump operations, or arithmetic operations is improved, the instruction overhead is reduced, and the performance of the processor is not significantly reduced.

YANG ZHIHUA (CN)
ZHOU HUANG (CN)
ZHAO WENPAN (CN)

PCT/CN2023/094091

November 30, 2023

May 13, 2023

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SHENZHEN FABTHINK TECH LTD (CN)

G06F9/30

CN114661355A	2022-06-24
CN113656071A	2021-11-16
CN101876892A	2010-11-03
US20020179719A1	2002-12-05

SHENZHEN XIECHENG INTELLECTUAL PROPERTY AGENCY (GENERAL PARTNERSHIP) et al. (CN)

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