RESISTANCE-CHANGE NON-VOLATILE MEMORY DEVICE

WIPO Patent Application WO2010109803

A1

Memory cells (MC) are each provided with one transistor and one resistance-change element. Each transistor is provided with a first main terminal, a second main terminal, and a control terminal. Each resistance-change element is provided with a first electrode, a second electrode, and a variable resistance layer provided between the first electrode and second electrode. Serial paths (SP) connecting the main terminals of the plurality of memory cells in series are each formed by connecting the first main terminal of one memory cell, among two adjacent memory cells, to the second main terminal of the other memory cell. In each memory cell, the control terminal is either a portion of a first interconnect (WL) corresponding to that memory cell or is connected to that first interconnect, the second electrode is either a portion of a second interconnect (SL) corresponding to that memory cell or is connected to that second interconnect, and the first electrode is either a portion of the serial path (SP) corresponding to that memory cell or is connected to that serial path.

WEI ZHIQIANG
AZUMA RYOTARO
TAKAGI TAKESHI
IIJIMA MITSUTERU
KANZAWA YOSHIHIKO

PCT/JP2010/001833

September 30, 2010

March 15, 2010

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PANASONIC CORP (JP)
WEI ZHIQIANG
AZUMA RYOTARO
TAKAGI TAKESHI
IIJIMA MITSUTERU
KANZAWA YOSHIHIKO

G11C13/00; G11C11/56; G11C17/06; G11C17/14; H01L27/10; H01L45/00; H01L49/00

JP2008146740A	2008-06-26
JP2004200641A	2004-07-15
JP2008269741A	2008-11-06
JP2007026627A	2007-02-01
JPS6130063A	1986-02-12

PATENT CORPORATE BODY ARCO PATENT OFFICE (JP)
Patent business corporation Owner old patent firm (JP)

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