RF CHIP PACKAGE

WIPO Patent Application WO/2023/080279

A1

The present invention provides an RF chip package which includes an (I)-shaped step formed in a partial area of a substrate, and an RF die mounted on top of the step of the substrate, and a first peripheral circuit and a second peripheral circuit chip mounted on the substrate in an area where the step is not formed, and which may include first mutual inductance adjusting portions arranged apart from each other on each of the first peripheral circuit chip and the RF die on the substrate between the first peripheral circuit chip and the RF die, so as to adjust the size of mutual inductance between the first peripheral circuit chip and the RF die, and second mutual inductance adjusting portions arranged apart from each other on each of the second peripheral circuit chip and the RF die on the substrate between the second peripheral circuit chip and the RF die, so as to adjust the size of mutual inductance between the second peripheral circuit chip and the RF die.

WO/2015/005977	THICK CONDUCTIVE STACK PLATING PROCESS WITH FINE CRITICAL DIMENSION FEATURE SIZE FOR COMPACT PASSIVE ON GLASS TECHNOLOGY
WO/2003/107445	SEMICONDUCTOR DEVICE, SEMICONDUCTOR CIRCUIT AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

LEE SANG-HUN (KR)
LEE SANG-YEOL (KR)
KIM SANG-SOO (KR)

PCT/KR2021/015987

May 11, 2023

November 05, 2021

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WAVEPIA CO LTD (KR)

H01L23/64; H01L23/00; H01L23/66; H01L25/16

KR20190111549A	2019-10-02
KR0156334B1	1998-10-15
KR20060132448A	2006-12-21
KR20090021605A	2009-03-04
JP2004126108A	2004-04-22

JEON, Jong Il (KR)

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