Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent

Application Serial Number 61 /565,670, filed on December 1 , 201 1 and entitled OFFSET LOOP CAPACITOR FOR ENVELOPE TRACKING," the disclosure of which is incorporated herein by reference in its entirety.

[0002] This application is also related to U.S. Patent Application Serial Number 13/661 ,164, filed on October 26, 2012 and entitled "AVERAGE

FREQUENCY CONTROL OF SWITCHER FOR ENVELOPE TRACKING," and to U.S. Patent Application Serial Number 13/661 ,227, filed on October 26, 2012 and entitled "RF SWITCHING CONVERTER WITH RIPPLE CORRECTION," the disclosures of which are incorporated herein by reference in their entireties. Field of the Disclosure

[0003] The disclosure relates generally to radio frequency (RF) power converters.

Background

[0004] User communication devices use radio frequency (RF) power converters to generate one or more supply voltages to power RF circuitry. If an RF switching converter provides Envelope Tracking (ET) and/or Average Power Tracking (APT), a supply voltage level of the supply voltage may need to be controlled with adequate precision in order to provide adequate power

performance and to prevent unwanted distortion. Specialized RF components may be provided in RF power converters to meet spectrum and power performance requirements in certain operational modes. Unfortunately, these specialized RF components require additional die area, and therefore increase manufacturing costs.

[0005] Accordingly, RF power converters with more versatile RF components are needed. Summary

[0006] This disclosure relates to radio frequency (RF) power converters and methods of operating the same. In one embodiment, an RF power converter includes a switching circuit, a switching controller, a low-drop out (LDO) regulation circuit, and an RF filter. The switching circuit is operable to receive a power source voltage, the switching circuit being switchable so as to generate a pulsed output voltage from the power source voltage. The switching controller is configured to switch the switching circuit so that the switching circuit generates the pulsed output voltage. The RF filter is coupled to receive the pulsed output voltage from the switching circuit and is operable to alternate between a first RF filter topology and a second RF filter topology. In the first RF filter topology, the RF filter is configured to convert the pulsed output voltage from the switching circuit into a supply voltage. However, the switching controller is configured to be activated and deactivated. Thus, the switching circuit generates the pulsed output voltage when the switching controller is activated.

[0007] When the switching controller is deactivated, the LDO regulation circuit may be activated. When the LDO regulation circuit is activated, the LDO regulation circuit is configured to generate the supply voltage. The RF filter is coupled to receive the supply voltage from the LDO regulation circuit and may be alternated into the second RF filter topology. The RF filter in the second RF filter topology is configured to filter the supply voltage from the LDO regulation circuit to reduce a ripple variation in a supply voltage level of the supply voltage. As such, since the RF filter can be alternated between the first RF filter topology and the second RF filter topology, the RF filter is more versatile because separate RF filters are not required to operate in conjunction with the switching circuit and the LDO regulation circuit to generate the supply voltage.

[0008] Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. Brief Description of the Drawings

[0009] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0010] Figure 1 illustrates one embodiment of a radio frequency (RF) switching converter with a switching controller and a switching circuit.

[0011] Figure 2 illustrates one embodiment of an RF amplification device with another embodiment of an RF switching converter and an RF amplification circuit where the RF switching converter has the switching controller and the switching circuit shown in Figure 1 , along with an RF filter that converts a pulsed output voltage from the switching circuit into a supply voltage that is provided to the RF amplification circuit.

[0012] Figure 3 is a semiconductor layout of one embodiment of the RF switching converter shown in Figure 2, where the RF switching converter includes a bang-bang controller (BBC), a voltage offset loop (VOL), a current sense detector, and an average frequency controller (AFC).

[0013] Figure 4 illustrates one embodiment of the BBC shown in Figure 3, which compares a sense signal level of a current sense signal to threshold voltage levels to operate the switching circuit shown in Figure 3.

[0014] Figure 5A illustrates one embodiment of the current sense signal as a function of time along with threshold voltage levels when the BBC shown in Figure 4 is operating in a first bang-bang mode.

[0015] Figure 5B illustrates one embodiment of the pulsed output voltage generated by the switching circuit shown in Figure 3 when the BBC shown in Figure 4 is operating in the first bang-bang mode.

[0016] Figure 6A illustrates one embodiment of the current sense signal as a function of time along with threshold voltage levels when the BBC is operating in a second bang-bang mode.

[0017] Figure 6B illustrates one embodiment of the pulsed output voltage generated by the switching circuit shown in Figure 3 when the BBC shown in Figure 4 is operating in the second bang-bang mode. [0018] Figure 7 illustrates one embodiment of the AFC shown in Figure 3, wherein the AFC sets a pulse count integer to an initial value and decrements the pulse count integer to a final value to determine whether an average pulse frequency of the pulsed output voltage is greater than or less than a target average frequency.

[0019] Figure 8A illustrates a pair of noise curves for the RF switching converter shown in Figure 3, wherein the noise curves are each shown as a function of a threshold parameter when the target average frequency is 30 MHz.

[0020] Figure 8B illustrates a pair of wideband noise power curves for the RF switching converter shown in Figure 3, wherein the wideband noise power curves are functions of frequency.

[0021] Figure 9 illustrates another embodiment of the AFC shown in Figure 3, wherein the AFC sets a pulse count integer to an initial value and increments the pulse count integer to a final value, and upper limits and lower limits for the final value are calculated to determine whether the average pulse frequency of the pulsed output voltage should be adjusted.

[0022] Figure 10 illustrates still another embodiment of the AFC shown in Figure 3, wherein the AFC sets a pulse count integer to an initial value and increments the pulse count integer to a final value, and a gain error is used to adjust the average pulse frequency.

[0023] Figure 1 1 illustrates one embodiment of the current sense detector shown in Figure 3, along with a ripple current correction circuit configured to generate a ripple correction current that reduces ripple variation in a supply current level of a supply current provided by the RF switching converter shown in Figure 3.

[0024] Figure 12 illustrates one embodiment of the VOL illustrated in Figure 3 wherein the VOL maintains a displacement voltage magnitude across a decoupling capacitor relatively constant.

[0025] Figure 13 illustrates a graph of one embodiment of the supply voltage, a supply control output voltage, and the displacement voltage magnitude as a function of time. [0026] Figure 14 illustrates one embodiment of an RF power converter, which includes an RF switching converter, a low-drop out (LDO) regulation circuit, and an RF filter that is configured to be alternated between different RF filter topologies.

[0027] Figure 15 is a circuit diagram illustrating an equivalent circuit topology when the LDO regulation circuit is activated.

[0028] Figure 16 is a graph illustrating system efficiency versus a target average power value. Detailed Description

[0029] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0030] This disclosure relates to radio frequency (RF) switching converters and RF amplification devices. RF switching converters convert a power source voltage, such as a battery voltage, into a supply voltage. Often, RF switching converters are employed in RF power amplification devices to provide the supply voltage to an RF amplification circuit within the RF amplification device. Using this supply voltage, the RF amplification circuit amplifies an RF signal by transferring power from the supply voltage to the RF signal in accordance with an amplifier gain.

[0031] The RF amplification devices may be used to amplify RF signals formatted in accordance with various RF communication standards. Different supply voltage biasing techniques may be more power efficient and/or introduce less distortion into the RF signal depending on the RF communication standard, power range, and/or RF frequency band. These supply voltage biasing techniques may include Envelope Tracking (ET), Average Power Tracking (APT), Polar Modulation, Low-Drop Out Regulation, and/or the like. Embodiments of the RF switching converters described herein may be designed to operate in different modes, where each mode is designed to implement a different supply voltage technique or a different set of supply voltage techniques. For example, in each mode, the RF switching converters may be designed to implement a different set of supply voltage techniques where each supply voltage technique in the set of supply voltage techniques provides a different supply voltage to different parts of the RF amplification circuit (such as driver amplifier stages and final amplifier stages).

[0032] Figure 1 is a block diagram of one embodiment of an RF switching converter 1 0. The RF switching converter 1 0 has a switching controller 1 2 and a switching circuit 1 4. The RF switching converter 1 0 is configured to generate a pulsed output voltage 1 6 from a power source voltage V _PO WER- The power source voltage V _PO WER may come from a power source, such as a battery, an AC- to-DC converter, and/or the like. Except for power source abnormalities and possibly AC-to-DC ripple variations, the power source voltage level of the power source voltage V _PO WER may generally be described as DC and relatively constant, at least with respect to some acceptable ripple variation and/or some acceptable rate of transient voltage abnormalities. In particular, the switching circuit 1 4 is operable to receive the power source voltage V _PO WER- The switching circuit 1 4 is switchable so as to generate the pulsed output voltage 1 6 from the power source voltage V _PO WER- Thus, the switching circuit 1 4 may include one or more switches, such as switchable transistors, that can be turned on and turned off to present the pulsed output voltage 1 6 in at least two different voltage states. In this manner, pulses are produced in the pulsed output voltage 1 6.

[0033] The switching controller 1 2 is configured to switch the switching circuit 1 4 and determine switch timing for proper regulation of the pulsed output voltage 1 6. For example, the switching controller 1 2 may generate one or more control signals that turn on or turn off the switches and the switching circuit 1 4. The switching controller 1 2 may be analog, digital, and/or digital and analog, and may itself include various different controllers, as explained in further detail below. The pulsed output voltage 16 may be transmitted to an RF filter to convert the pulsed output voltage 16 into a supply voltage. The RF filter may or may not be included in the RF switching converter 10. For example, the RF filter may instead be included within a power amplification circuit and be external to the RF switching converter 10.

[0034] In this embodiment, the RF switching converter 10 may be used to employ APT and ET supply voltage biasing techniques. When RF signals are encoded using orthogonal frequency division multiple access multiplexing (OFDMA), the RF switching converter 10 may be used to implement ET. On the other hand, when RF signals are encoded using code division multiple access multiplexing (CDMA), the RF switching converter 10 may used to implement APT.

[0035] Referring again to Figure 1 , the switching controller 12 is configured to switch the switching circuit 14 such that the pulsed output voltage 16 has an average pulse frequency. In other words, although a duty ratio of the pulsed output voltage 16 may vary, the duty ratio has an average value with respect to time, and thus the pulsed output voltage 16 has an average pulse frequency with respect to time. A DC supply voltage level of the supply voltage is determined by a pulse frequency of the pulsed output voltage 16. Thus, a DC voltage state of the supply voltage varies as the pulse frequency varies.

[0036] By varying the pulse frequency and duty ratio of the pulsed output voltage 16, the DC voltage state of the supply voltage can change quickly.

However, the pulsed output voltage has an average pulse frequency, which is essentially the mean frequency at which pulses are provided in the pulsed output voltage 16 with respect to time. Nevertheless, due to manufacturing variations and operational variations (such as temperature variation and power source variation), the average pulse frequency of the pulsed output voltage 16 may not always be set consistently or in accordance with a contemplated design. In fact, in some embodiments, the average pulse frequency has been shown to change by up to ±40% due to operational variations. [0037] To mitigate the effects of manufacturing and operational variations, the switching controller 12 is configured to adjust the average pulse frequency. As shown in Figure 1 , the switching controller 12 is operable to receive a target average frequency value 18. In this embodiment, the target average frequency value 18 is a data parameter that identifies a target average frequency for the average pulse frequency of the pulsed output voltage 16. The switching controller 12 is configured to detect that the average pulse frequency of the pulsed output voltage 16 during a time period differs from the target average frequency identified by the target average frequency value 18. To help correct for the effects of manufacturing and/or operational variations on the average pulse frequency, the switching controller 12 reduces a difference between the average pulse frequency and the target average frequency identified by the target average frequency value 18. In this manner, the switching controller 12 can eliminate, minimize, or at least decrease errors in the average pulse frequency of the pulsed output voltage 16.

[0038] In the embodiment shown in Figure 1 , the switching controller 12 receives a pulsed feedback signal 20 that changes from one voltage state to another in accordance with the pulsed output voltage 16 generated by the switching circuit 14. Thus, the pulses of the pulsed feedback signal 20 are indicative of the pulses of the pulsed output voltage 16. From the pulsed feedback signal 20, the switching controller 12 can detect whether the average pulse frequency of the pulsed output voltage 16 differs from the target average frequency identified by the target average frequency value 18 during the time period. The switching controller 12 may then alter the switching frequency of the switching circuit 14 to reduce the difference between the average pulse frequency and the target average frequency identified by the target average frequency value 18.

[0039] It should be noted that the difference between the average pulse frequency and the target average frequency may or may not be eliminated after a single time period. For example, if the difference between the average pulse frequency and the target average frequency is large enough, the switching controller 12 may require multiple time periods in order to minimize the

difference. Furthermore, the difference between the average pulse frequency and the target average frequency identified by the target average frequency value 18 may or may not ever be fully eliminated. This may depend on the frequency resolution and the control accuracy of a particular embodiment of the RF switching converter 10.

[0040] Figure 2 illustrates one embodiment of an RF amplification device 22. The RF amplification device 22 includes another embodiment of an RF switching converter 24 and an RF amplification circuit 26. The RF switching converter 24 is the same as the RF switching converter 10 shown in Figure 1 , except the RF switching converter 24 shown in Figure 2 has an RF filter 28 coupled to receive the pulsed output voltage 16. Thus, the RF switching converter 24 has the same switching controller 12 and the same switching circuit 14 described above with respect to Figure 1 . The RF filter 28 is configured to convert the pulsed output voltage 16 from the switching circuit 14 into a supply voltage VSUPPLY for the RF amplification circuit 26.

[0041 ] With regard to the RF amplification circuit 26 shown in Figure 2, the RF amplification circuit 26 is operable to receive both the supply voltage VSUPPLY from the RF switching converter 24 and an RF signal 30 from external upstream RF circuitry. In this particular embodiment, the RF amplification circuit 26 receives the RF signal 30 at an input terminal 32. The RF amplification circuit 26 is configured to amplify the RF signal 30 using the supply voltage VSUPPLY from the RF switching converter 24. In other words, the RF amplification circuit 26 provides amplification to the RF signal 30 by transferring power from the supply voltage VSUPPLY to the RF signal 30. The RF amplification circuit 26 then outputs the RF signal 30 after amplification from an output terminal 34 to external downstream circuitry. For example, the RF amplification circuit 26 may be provided in a transmission chain of a transceiver in a user communication device, such as a laptop, a cellular phone, a tablet, a personal computer, or the like. The output terminal 34 may be coupled to an antenna (not shown) that radiates the RF signal 30 to a base station or directly to another user communication device after amplification by the RF amplification circuit 26.

[0042] The RF amplification circuit 26 may be configured to amplify the RF signal 30 when the RF signal 30 is formatted in accordance with any one of a multitude of RF communication standards. Often, the RF amplification circuit 26 is divided into RF amplification stages, including one or more driver RF amplification stages and a final RF amplification stage. The supply voltage

VSUPPLY may provide the supply voltage VSUPPLY to all of the RF amplification stages, or alternatively, to a set of the RF amplification stages. For example, the supply voltage VSUPPLY may provide the supply voltage VSUPPLY to only the final RF amplification stage. Other circuitry may be provided in the RF switching converter 24 or externally to provide a second supply voltage to the driver RF amplification stages if desired.

[0043] The RF signal 30 may be encoded in any one of a plurality of multiplexing formats, such as Time Division Multiplexing (TDM), Frequency

Division Multiplexing (FDM), CDMA, OFDMA, or the like. When CDMA is being employed, the RF switching converter 24 may be used to implement APT, and thus the RF amplification circuit 26 may need to be operated at back-off power levels well within a linear region of the RF amplification circuit 26. On the other hand, the RF switching converter 24 may be used to implement ET where the supply voltage level of the supply voltage VSUPPLY is modulated. Other types of power regulation circuits (either internal or external), such as low-drop out (LDO) regulation circuits, may be provided for TDM and FDM. However, LDO

regulation circuits are generally unable to efficiently transfer power to the RF amplification circuit 26 for CDMA and OFDMA due to large resistances, which consume a significant amount of power. The RF switching converter 24 is generally much more power efficient due to its ability to provide power

conversion using primarily reactive components.

[0044] Referring again to Figure 2, the switching controller 12 may be configured to switch the switching circuit 14 such that the RF amplification circuit 26 is configured to amplify the RF signal 30 when the RF signal 30 is formatted in accordance with a Long Term Evolution (LTE) standard, which utilizes OFDMA to encode data in the RF signal 30. The RF amplification circuit 26 needs to amplify the RF signal 30 without introducing an excessive amount of distortion into the RF signal 30. However, to do this at the maximum efficiency, the RF

amplification circuit 26 should operate near saturation. If the saturation voltage simply remains constant, the RF amplification circuit 26 introduces an excessive amount of distortion to the RF signal 30, since the RF amplification circuit 26 is not operating linearly. Often, other approaches have dealt with this problem by backing off from the saturation point. However, in this embodiment, the supply voltage VSUPPLY has a supply voltage level that varies so as to adjust the saturation voltage of the RF amplification circuit 26. Thus, although the RF amplification circuit 26 does not operate linearly when saturated, the saturation voltage of the RF amplification circuit 26 is selected so that the amplification gain associated with that saturation voltage is maintained essentially constant given the input power of the RF signal 30. In this manner, amplification is provided linearly simply by selecting the saturation voltage so that the amplification gain remains essentially the same, regardless of the input power of the RF signal 30.

[0045] As shown in Figure 2, the RF filter 28 is operable to receive the pulsed output voltage 1 6 from the switching circuit 1 4, and is configured to convert the pulsed output voltage 1 6 into the supply voltage VSUPPLY- TO convert the pulsed output voltage 1 6 into the supply voltage VSUPPLY, the RF filter 28 includes a power inductor 36 coupled in series and a power capacitor 38 coupled in shunt with respect to the switching circuit 1 4. Accordingly, the power inductor 36 is configured to generate an inductor current 40 in response to the pulsed output voltage 1 6. While the voltage across the power inductor 36 can change instantly, the power inductor 36 resists changes in the inductor current 40. In contrast, while a current to the power capacitor 38 can change instantly, the power capacitor 38 resists changes in voltage. The supply voltage VSUPPLY in this embodiment is essentially the voltage across the power capacitor 38.

[0046] The power capacitor 38 generates the supply voltage VSUPPLY having a supply voltage level that varies in accordance with a ripple variation. However, this ripple variation is generally small, and the RF filter 28 generates the supply voltage VSUPPLY with an average DC supply voltage level set in accordance with a pulse frequency of the pulsed output voltage 1 6. Similarly, the power inductor 36 provides the inductor current 40 having an inductor current level that varies in accordance with a ripple variation. However, the ripple variation is generally small enough so that the inductor current 40 provides an average DC current level. As the pulse frequency varies, so does the average DC supply voltage level. In this manner, the supply voltage level is, for the most part, DC and can be set to a particular value by adjusting the pulse frequency of the pulsed output voltage 1 6.

[0047] The switching circuit 1 4 is operable to receive the power source voltage V _PO WER, and is switchable so as to generate the pulsed output voltage 1 6 from the power source voltage V _PO WER- The switching controller 1 2 is configured to switch the switching circuit 1 4 such that the pulsed output voltage 1 6 has an average pulse frequency. The average pulse frequency is generally a center value for the pulse frequency. In this embodiment, the average pulse frequency may be set to different values, such as, for example, 5 MHz, 1 8 MHz, or 30 MHz. The pulse frequency may vary from the average pulse frequency by ± 4.5 MHz.

[0048] However, as discussed above, due to manufacturing variations and/or operational variations, the average pulse frequency (or, in other words, the center pulse frequency) may be set inappropriately or drift. To determine that the average pulse frequency is set incorrectly, the switching controller 1 2 receives the pulsed feedback signal 20 and detects whether the average pulse frequency of the pulsed output voltage 1 6 differs from the target average frequency identified by the target average frequency value 1 8 during the time period. If so, the switching controller 1 2 adjusts the average pulse frequency to reduce the difference between the average pulse frequency and the target average frequency identified by the target average frequency value 1 8.

[0049] Figure 3 illustrates a semiconductor layout of one embodiment of the RF switching converter 24, with the switching controller 1 2, switching circuit 1 4, and RF filter 28 shown in Figure 2. The RF switching converter 24 shown in Figure 3 includes a semiconductor substrate 42. The switching controller 1 2 and the switching circuit 14 are formed with the semiconductor substrate 42. In particular, the switching controller 1 2 and the switching circuit 14 may be formed in a device region formed from metallic layers and doped semiconductor layers in the semiconductor substrate 42. Typical dopants that may be utilized to dope the semiconductor layers in the device region of the semiconductor substrate 42 are Gallium (Ga), Arsenic (As), Silicon (Si), Tellurium (Te), Zinc (Zn), Sulfur (S), Boron (B), Phosphorus (P), Beryllium (Be), Aluminum Gallium Arsenide

(AIGaAs), Indium Gallium Arsenide (InGaAs), and/or the like. The device region is generally formed over a semiconductor die within the semiconductor substrate 42. The semiconductor die is generally not doped and can be formed from any suitable semiconductor material, such as Si, Silicon Germanium (SiGe), Gallium Arsenide (GaAs), Indium Phosphorus (InP), and/or the like.

[0050] The switching controller 1 2 shown in Figure 3 includes a bang-bang controller (BBC) 44, an average frequency controller (AFC) 46, a current sense detector 48, and a voltage offset loop (VOL) 50. The switching circuit 14 includes a P-type field effect transistor (P-FET) 52, an N-type field effect transistor (N- FET) 54, and a charge pump 56. With regard to the switching circuit 14, the P- FET 52 is operable to receive the power source voltage V _PO WER from a power source 58, such as a battery. The N-FET 54 is operable to receive a reference voltage, such as ground. In this particular embodiment, the P-FET 52 includes a source SP, a drain Dp, and a gate Gp. The source Sp is configured to receive the power source voltage V _PO WER- The N-FET 54 includes a drain D _N , a source S _N , and a gate G _N . The source S _N is coupled to ground, while the drain D _N is coupled directly to the drain D _P of the P-FET 52. The pulsed output voltage 1 6 is generated from a node N between the drain D _P and the drain D _N .

[0051 ] In order for the switching circuit 14 to generate the pulsed output voltage 1 6, the BBC 44 of the switching controller 1 2 is configured to switch the P-FET 52 between an on state and an off state. In the on state, the P-FET 52 is configured to pull the pulsed output voltage 16 toward the power source voltage VpowER- The BBC 44 is also configured to switch the N-FET 54 between the on state and the off state. The N-FET 54 is configured to pull the pulsed output voltage 16 toward the reference voltage (i.e., ground) in the on state. To switch the P-FET 52 between the on state and the off state, the BBC 44 is operable to generate a first control signal 60 that may be provided in an activation state or in a deactivation state. The first control signal 60 is received at the gate GP of the P-FET 52. In the activation state, the first control signal 60 switches the P-FET 52 into the on state to pull the pulsed output voltage 16 toward the power source voltage V _PO WER- When the first control signal 60 is in the deactivation state, the P-FET 52 is turned off and a power source voltage level of the power source voltage V _PO WER is dropped across the P-FET 52.

[0052] The BBC 44 also generates a second control signal 62. The gate G _N of the N-FET 54 is operable to receive the second control signal 62 from the BBC 44. When the second control signal 62 is in an activation state, the N-FET 54 is switched on and the pulsed output voltage 16 is pulled toward the reference voltage, in this case ground. On the other hand, when the second control signal 62is in the deactivation state, the N-FET 54 is switched off and the voltage from the node N to the reference voltage is dropped across the N-FET 54.

[0053] The BBC 44 is operable in a first bang-bang mode and in a second bang-bang mode. In the first bang-bang mode, the BBC 44 only switches the P- FET 52 and the N-FET 54 on and off. With regard to the first bang-bang mode, when the P-FET 52 is switched on, the N-FET 54 is switched off. Thus, the pulsed output voltage 16 is provided in a first voltage state near the power source voltage level of the power source voltage V _PO WER- On the other hand, when the P-FET 52 is switched off, the N-FET 54 is switched on. Thus, the pulsed output voltage 16 is provided in a second voltage state near the reference voltage level of the reference voltage (in this case, ground).

[0054] With regard to the second bang-bang mode, the BBC 44 is also operable to control switches within the charge pump 56. The charge pump 56 has a switching topology that may include two flying capacitors and seven switches to allow the charge pump 56 to generate two different boost voltages that can be dynamically selected. Thus, while in the first bang-bang mode, the BBC 44 only switches the N-FET 54 and the P-FET 52 on and off to present step-down buck voltages at the node N. However, in the second bang-bang mode, the BBC 44 is further configured to operate the switches in the charge pump 56 so as to present two different boost voltages, equal to about 1 .5 times the power source voltage V _PO WER and 2 times the power source voltage V _PO WER at node N. The BBC 44 may generate a charge pump output 64, which may include several control signals to control the switches of the charge pump 56. The operation of the BBC 44 is explained in further detail below.

[0055] To determine when to switch on and switch off the P-FET 52 and the N-FET 54 in either the first bang-bang mode or the second bang-bang mode, the BBC 44 receives a threshold parameter 66 from the AFC 46. The AFC 46 of the switching controller 12 is operable to receive the threshold parameter 66 at an initialized value from external circuitry. The BBC 44 is also operable to receive an offset voltage 68 from the VOL 50. Finally, the BBC 44 is operable to receive a current sense signal 70 from the current sense detector 48. The current sense signal 70 has a signal level indicative of a current level of the inductor current 40 of the power inductor 36. To do this, the current sense detector 48 receives a feedback voltage 72 and generates the current sense signal 70 as a current having a current level indicative of the current level of the inductor current 40.

[0056] The BBC 44 is configured to set the average pulse frequency of the pulsed output voltage 16 based on the threshold parameter 66 from the AFC 46. To correct the average pulse frequency, the AFC 46 adjusts the threshold parameter 66 to reduce the difference between the average pulse frequency and the target average frequency identified by the target average frequency value 18. After the time period for detection of the average pulse frequency, the AFC 46 adjusts the threshold parameter 66 and provides the updated threshold parameter 66 to the BBC 44.

[0057] Figure 4 illustrates one embodiment of the BBC 44 shown in Figure 3. The BBC 44 includes a digital control unit 74, a decoder 76, a comparator 80, a comparator 82, a comparator 84, a comparator 86, a voltage adder 88, a voltage adder 90, a voltage adder 92, a voltage adder 94, a voltage adder 96, a voltage adder 98, a variable resistor 100, a variable resistor 102, and a mirrored ratio circuit 104. The digital control unit 74 is configured to receive the threshold parameter 66 from the AFC 46 (shown in Figure 3). The BBC 44 is configured to set a first threshold voltage level based on the threshold parameter 66. To do this, the digital control unit 74 searches a stored list of threshold magnitudes based on the threshold parameter 66. The threshold magnitude |TM| is then used to generate a first intermediary current signal 106 and a second

intermediary current signal 108. The first intermediary current signal 106 has a current level with a negative of the threshold magnitude, -|TM|. The first intermediary current signal 106 is transmitted through the variable resistor 102 to provide a first intermediary voltage 1 10. In this embodiment, the first

intermediary voltage 1 10 is a voltage across the variable resistor 102. The variable resistor 102 has a variable resistance of Rdad , which is set by the digital control unit 74.

[0058] With regard to the second intermediary current signal 108, the second intermediary current signal 108 has a current level that is a positive of the threshold magnitude, +|TM|. The second intermediary current signal 108 is transmitted through the variable resistor 100 to generate a second intermediary voltage 1 12. In this embodiment, the second intermediary voltage 1 12 is a voltage across the variable resistor 100. The variable resistor 100 has a variable resistance of Rdac2- The digital control unit 74 is configured to set the variable resistance Rdac2- Generally, the variable resistances Rdad , Rdac2 are set by the digital control unit 74 to the same, or substantially the same, resistance value.

[0059] With regard to the decoder 76, the decoder 76 is configured to receive an operational mode control signal 1 14. The operational mode control signal 1 14 may indicate either the first bang-bang mode or the second bang-bang mode. As shown in Figure 4, the voltage adders 92 and 94 are provided in order to add a range voltage 1 16 to the first intermediary voltage 1 10 and the second

intermediary voltage 1 12. In the first bang-bang mode, however, the range voltage 1 16 has a voltage level of zero (0) Volts. From the voltage adder 92, a first threshold signal 1 18 is generated having a first threshold voltage level based on the threshold parameter 66. From the voltage adder 94, a second threshold signal 120 is generated having a second threshold voltage level based on the threshold parameter 66.

[0060] The first threshold voltage level and the second threshold voltage level are used to determine when to turn on and turn off the P-FET 52 (shown in Figure 3) and the N-FET 54 (shown in Figure 3). In the first bang-bang mode, only the first threshold voltage level of the first threshold signal 1 18 and the second threshold voltage level of the second threshold signal 120 are relevant. The charge pump 56 (shown in Figure 3) is not utilized. However, with regard to the second bang-bang mode, additional threshold levels to set boost levels can be provided through the operation of the charge pump 56.

[0061] In the embodiment shown in Figure 4, both the first threshold signal 1 18 and the second threshold signal 120 are voltages, and in particular, DC voltages. Thus, the first threshold voltage level of the first threshold signal 1 18 and the second threshold voltage level of the second threshold signal 120 are relatively constant voltage levels. The second threshold voltage level is lower than the first threshold voltage level because the first intermediary current signal 106 had the negative of the threshold magnitude, -|TM|, while the second intermediary current signal 108 had the positive of the threshold magnitude, +|TM|. The first threshold signal 1 18 is received at a non-inverting terminal of the comparator 84, while the second threshold signal 120 is received at a non- inverting terminal of the comparator 86.

[0062] As shown in Figure 4, the current sense signal 70 is received from the current sense detector 48. The current sense signal 70 is then provided to the mirrored ratio circuit 104. The mirrored ratio circuit 104 has a variable resistor 104A and a mirror circuit 104B. The mirror circuit 104B receives the current sense signal 70 and is configured to generate a mirror current 104C from the current sense signal 70. A ratio of a current level of the mirror current 104C and the current level of the current sense signal 70 is 1 /M. The ratio 1/M is variable where the value of M is controlled by the digital control unit 74 based on a dedicated MIPI bit 104D. [0063] The first threshold voltage level and the second threshold voltage level are set to equal the Rdac (i.e., the resistance value of either R _da ci or Rdac2) R * M ^* |TM|. With regard to the first bang-bang mode, the value of M is set equal to 20. For instance, since the threshold parameter 66 is 4 bits, the threshold parameter 66 may represent current levels from 20 mA to 40 mA in steps of 2 mA. The second bang-bang mode requires an increased range. To increase the range for the second bang-bang mode, the value M is set equal to 40. For instance, since the threshold parameter 66 is 4 bits, the threshold parameter may represent current levels from 40mA to 80mA in steps of 4mA. The threshold parameter 66 may thus represent current levels where the ratio of 1/M may be changed from 1 /20 to 1 /40 via the dedicated MIPI bit 104D.

[0064] A preliminary voltage 104E, which is the voltage across the variable resistor 104A, is then generated and provided to the voltage adder 96. The variable resistor 104A has a variable resistance R, which is set by the digital control unit 74. During operation of the VOL 50 (shown in Figure 3) in fast mode, there is a need for a large dynamic range to control large current through an offset capacitor (discussed below), thus the variable resistances R, Rdad , Rdac2 are reduced so that R and Rdad , and R and Rdac2, have the same ratio to allow an increased feedback dynamic range, and the decoder 76 operates in the second bang-bang mode. Then, at the end of the fast mode, both the ratios for R and R _d a _d , and R and Rdac2 are set back to their nominal values and the decoder 76 operates in the first bang-bang mode.

[0065] The offset voltage 68 is received at the voltage adder 98 from the VOL 50, which adds the range voltage 1 16 so as to generate a preliminary voltage 122. The preliminary voltage 122 is subtracted from the preliminary voltage 104E so as to generate a current sense signal 124 having a sense signal level indicative of a current level of the current across the power inductor 36 (shown in Figure 3). In this case, the current sense signal 124 is a voltage and the sense signal level is a voltage level. As mentioned above, in the first bang-bang mode, only the first threshold voltage level of the first threshold signal 1 18 and the second threshold voltage level of the second threshold signal 120 are relevant. In this embodiment, the current sense signal 124 is a voltage, while the current sense signal 70 is a current. A clip 126 provides voltage limitations to the current sense signal 124 to ensure that the appropriate headroom is provided to the P- FET 52 (shown in Figure 3) and the N-FET 54 (shown in Figure 3).

[0066] The comparator 84 generates a comparator signal 127 from the comparison of the current sense signal 124 and the first threshold signal 1 18. The decoder 76 turns on the P-FET 52 and turns off the N-FET 54 in response to the sense signal level being above the first threshold voltage level. As such, the decoder 76 is configured to generate the first control signal 60 in the activation state and the second control signal 62 in the deactivation state. The comparator 86 generates a comparator signal 128, which is received by the decoder 76. The comparator 86 is configured to compare the second threshold voltage level and the sense signal level of the current sense signal 124. The decoder 76 is configured to turn off the P-FET 52 and turn on the N-FET 54 in response to the sense current signal level of the current sense signal 124 being below the second threshold voltage level of the second threshold signal 120. Thus, in this case, the decoder 76 is configured to generate the first control signal 60 in the deactivation state and the second control signal 62 in the activation state. Note that the BBC 44 does not turn off the P-FET 52 and turn on the N-FET 54 when the sense signal level is below the first threshold voltage level of the first threshold signal 1 18. Rather, the P-FET 52 is turned off and the N-FET 54 is turned on in response to the sense signal level being below the second threshold voltage level. This provides the so-called "bang-bang" control operation of the BBC 44.

[0067] In the second bang-bang mode, the range voltage 1 16 is also provided to provide a greater range for comparisons. For example, the range voltage 1 16 may have a range voltage level of approximately 1 .7 volts in the second bang- bang mode. A third intermediary voltage 129 is generated by the digital control unit 74 based on the threshold parameter 66. A third threshold signal 130 is generated from the voltage adder 90 having a third threshold voltage level. In this manner, the BBC 44 is configured to set a third threshold voltage level that is higher than the first threshold voltage level in the high voltage mode.

Additionally, the digital control unit 74 is configured to generate a fourth intermediary voltage 132 based on the threshold parameter 66 in the high voltage mode. A fourth threshold signal 134 is generated from the voltage adder 88 having a fourth threshold voltage level. In this manner, the BBC 44 is configured to set a fourth threshold voltage level that is higher than the third threshold voltage level.

[0068] The comparator 82 receives the third threshold signal 130 at a non- inverting input and the current sense signal 124 at an inverting input. A

comparator signal 136 is generated from the comparator 82. The decoder 76 is configured to switch the charge pump 56 (shown in Figure 3) such that the pulsed output voltage 16 is provided in the first high voltage state (which, in this example, is approximately 1 .5 times the power source voltage level of the power source voltage V _PO WER) in response to the sense signal level being above the third threshold voltage level of the third threshold signal 130. The comparator 80 is configured to receive the fourth threshold signal 134 at a non-inverting terminal and the current sense signal 124 at an inverting terminal. The comparator 80 is configured to generate a comparator signal 138. The decoder 76 is configured to switch the charge pump 56 such that the pulsed output voltage 16 is provided in the second high voltage state (which, in this example, is approximately double the power source voltage level of the power source voltage V _PO WER) in response to the sense signal level being above the fourth threshold voltage level. The decoder 76 is configured to control the charge pump 56 by controlling the activation and deactivation states of the control signals in the charge pump output 64.

[0069] Referring now to Figures 5A and 5B, Figure 5A illustrates one embodiment of the current sense signal 124 with respect to time. The voltage magnitude VOFFS is the magnitude of the offset voltage 68 received from the VOL 50 shown in Figure 3. Thus, in the first bang-bang mode, the voltage magnitude VOFFS determines a center voltage level V _C EN since the first intermediary current signal 106 was the negative of the threshold magnitude |TM|. Thus, the second threshold voltage level is provided at a voltage difference Vi lower than the center voltage level V _C EN- The second threshold voltage level is thus at M ₂ . Since the second intermediary current signal 108 had a current level that was the positive of the threshold magnitude |TM|, the first threshold voltage level of the first threshold signal 1 18 is provided at M-i . The first threshold voltage level M is the voltage difference Vi above the center voltage level V _C EN- [0070] Figure 5B illustrates one embodiment of the pulsed output voltage 16 in the first bang-bang mode. The voltage magnitude BUCK in Figure 5B represents the voltage level resulting in the pulsed output voltage 16 when the P- FET 52 (shown in Figure 3) is pulled up near the power source voltage level of the power source voltage V _PO WER (shown in Figure 3). The voltage magnitude AG (i.e., approximately ground) in Figure 5B represents the voltage level resulting in the pulsed output voltage 16 when the N-FET 54 (shown in Figure 3) is pulled down near ground. As shown in Figure 5A, the sense signal level of the current sense signal 124 is above the first threshold voltage level M at time ti .

Accordingly, the P-FET 52 pulls the pulsed output voltage 16 to the voltage level BUCK in response to the sense signal level of the current sense signal 124 being above the first threshold voltage level M-i , as shown in Figure 5B. The pulsed output voltage 16 is maintained at the voltage level BUCK until time t ₂ . As shown in Figure 5A, the sense signal level of the current sense signal 124 is below the second threshold voltage level M ₂ at time t ₂ . Accordingly, the N-FET 54 pulls the pulsed output voltage 16 to the voltage level AG in response to the sense signal level of the current sense signal 124 being below the second threshold voltage level M ₂ , as shown in Figure 5B. The process repeats itself to generate pulses 140 in the pulsed output voltage 16. The BBC 44 shown in Figure 3 is thus configured to switch the switching circuit 14 at a switching frequency that is based on the threshold parameter 66. This is because the threshold parameter 66 determines the voltage and the voltage difference V|, and thus determines how often and for how long a pulse 140 is provided in the pulsed output voltage 16. [0071 ] Figures 6A and Figure 6B illustrate the operation of the BBC 44 shown in Figure 3 in the second bang-bang mode. Note that in the second bang-bang mode, the first threshold voltage level M and the second threshold voltage level M ₂ have been adjusted downward by the range voltage level V _C M of the range voltage 1 16 (shown in Figure 4). The current sense signal 124 is shown in Figure 6A, along with the third threshold voltage level M ₃ of the third threshold signal 130 and the fourth threshold voltage level m ₄ of the fourth threshold signal 134.

[0072] At time t ₃ , the sense signal level of the current sense signal 124 is above the first threshold voltage level M-i , as shown in Figure 6A. Accordingly, in response, the pulsed output voltage 16 is pulled to the voltage level BUCK, as shown in Figure 6B. The voltage level of the pulsed output voltage 16 is maintained at the voltage level BUCK until time t ₄ . At time t ₄ , the sense signal level of the current sense signal 124 is above the third threshold voltage level M ₃ , as shown in Figure 6A. Accordingly, the BBC 44 switches the charge for the charge pump 56 so that the voltage level of the pulsed output voltage 16 is provided at the high voltage state of 1 .5X, as shown in Figure 6B. The voltage level is maintained in the high voltage state 1 .5X until time t ₅ . At time t ₅ , the sense signal level of the current sense signal 124 is above the fourth threshold voltage level M ₄ , as shown in Figure 6A. Accordingly, in response, the BBC 44 operates the charge pump 56 so that the voltage level of the pulsed output voltage 16 is provided at the high voltage state 2. OX, as shown in Figure 6B. The voltage level of the pulsed output voltage 16 is maintained at the high voltage state 2. OX until time t ₆ . At time t ₆ , the sense signal level of the current sense signal 124 is below the second threshold voltage level M ₂ , as shown in Figure 6A. Accordingly, in response, the voltage level of the pulsed output voltage 16 is pulled down to the voltage level AG, as shown in Figure 6B. Given that an example of the operation of the BBC 44 (shown in Figure 3) in Figures 5A, 5B, 6A, and 6B has been given, the operation of embodiments of the AFC 46 (shown in Figure 3) can now be described. [0073] Figure 7 illustrates one embodiment of an AFC 46(1 ). The AFC 46(1 ) includes a clock generation circuit 142, a counter 144, a digital control unit 146, and an accumulator 148. In this embodiment, the clock generation circuit 142 receives a pulse ratio parameter 150 that identifies a pulse ratio. For example, the pulse ratio parameter 150 may be an integer equal to one (1 ), two (2), or four (4). The clock generation circuit 142 generates a clock signal from the pulsed feedback signal 20. More specifically, the clock generation circuit 142 shown in Figure 7 is configured to generate a clock signal 152 such that clock pulses of the clock signal 152 are provided at the pulse ratio with respect to the pulses 140 (shown in Figure 5B) of the pulsed output voltage 1 6 (shown in Figures 3 and 5B). Thus, if the pulse ratio identified by the pulse ratio parameter 150 is one (1 ), for every pulse in the pulsed feedback signal 20 there is a clock pulse in the clock signal 152. In contrast, if the pulse ratio parameter 150 is two (2), the clock generation circuit 142 provides one clock pulse for every two pulses in the pulsed feedback signal 20. If the pulse ratio identified by the pulse ratio parameter 150 is four (4), there will be four pulses in the pulsed feedback signal 20 for every clock pulse in the clock signal 152.

[0074] The clock generation circuit 142 provides the clock signal 152 to the counter 144. The counter 144 is configured to perform a count operation on a pulse count integer during a time period in accordance with the clock signal 152 so that the pulse count integer has a final value upon expiration of the time period. To initiate the pulse count integer of the counter 144 to an initial value, the digital control unit 146 is configured to generate an enable signal 149 and a reset signal 151 . In other words, upon receiving both the enable signal 149 and the reset signal 151 , the counter 144 is configured to set the pulse count integer to the initial value. In this embodiment, the value of the pulse count integer is initialized to equal the number of clock pulses of the clock signal 152 that should be provided if the pulsed output voltage 16 is operating at the target average frequency identified by the target average frequency value 18. The initial value of the pulse count integer is thus equal to the target average frequency identified by the target average frequency value 18, multiplied by a time duration of the time period, and divided by a pulse ratio of the pulse ratio parameter 150.

[0075] In this embodiment, the count operation performed by the counter 144 is a decrement operation that decrements the pulse count integer as long as the pulse count integer is above a minimum value. For example, the count operation decrements the pulse count integer until the pulse count integer reaches a minimum value, which in this example is zero (0). The final value of the pulse count integer is thus indicative of when the average pulse frequency during the time frequency differs from the target average frequency identified by the target average frequency value 18. If the final value of the pulse count integer is zero (0), it may be presumed that the average pulse frequency is greater than the target average frequency. If the final value is greater than zero (0), it may be presumed that the average pulse frequency is less than the target average frequency.

[0076] The counter 144 then sets a flag bit 154 based on the final value of the pulse count integer. In this embodiment, the counter 144 sets the flag bit 154 to a first bit state in response to the final value of the pulse count integer being above the minimum value, which in this example is zero (0). The counter 144 sets the flag bit 154 to a second bit state antipodal to the first bit state in response to the final value of the pulse count trigger being equal to the minimum value. For example, the flag bit 154 may be set to a logical 1 if the final value of the pulse count integer is greater than the minimum value (i.e., zero (0) in this example). The counter 144 would set the flag bit 154 to a logical 0 if the final value of the pulse count integer is at the minimum value (i.e., zero (0) in this example).

[0077] The accumulator 148 is operable to receive the threshold parameter 66 and the flag bit 154. The accumulator 148 is configured to adjust the threshold parameter 66 such that the threshold parameter 66 is increased by a step size in response to the flag bit 154 being in the first bit state (i.e., in this example, logical 1 ). As a result, this reduces the average pulse frequency. In contrast, the accumulator 148 is configured to adjust the threshold parameter 66 such that the threshold parameter 66 is decreased by the step size in response to the flag bit 154 being in the second bit state (i.e., in this example, logical 0). As a result, the threshold parameter 66 is provided to the BBC 44 such that the BBC 44 increases the average pulse frequency of the pulsed output voltage 16.

[0078] Note that the accumulator 148 is further operable to receive a noise adjustment selection bit 156. The accumulator 148 is configured to set the step size to a first integer in response to the noise adjustment selection bit 156 being in the first bit state (i.e., logical 1 ) and is configured to set the step size to a second integer in response to the noise adjustment selection bit 156 being in the second bit state (i.e., logical 0). In this embodiment, the first integer is a step size of two (2), while the second integer is a step size of one (1 ). The noise adjustment selection bit 156 is provided to the BBC 44 shown in Figure 3. The digital control unit 74 shown in Figure 4 is configured to set the ratio between the variable resistors 100, 102, 104A and the value of M in accordance with the noise adjustment selection bit 156. For example, if the noise adjustment selection bit 156 is equal to zero (0), the first bang-bang mode is selected. M is equal to the value 20 and the ratios between the variable resistor 104A and the variable resistor 102, and between the variable resistor 104A and the variable resistor 100, are set accordingly. On the other hand, if the noise adjustment selection bit 156 is equal to one (1 ), the second bang-bang mode is selected. M is equal to 40 and the ratios between the variable resistor 104A and the variable resistor 102, and between the variable resistor 104A and the variable resistor 100, are set accordingly by the digital control unit 74.

[0079] Also, note that the digital control unit 146 shown in Figure 7 is configured to receive a mode value 158. If the mode value 158 is equal to zero (0), the accumulator 148 only loads the threshold parameter 66 and the noise adjustment selection bit 156. When the mode value 158 is equal to one (1 ), the accumulator 148 updates the threshold parameter 66 after the time duration. If the mode value 158 is equal to two (2), the accumulator 148 holds the threshold parameter 66 without providing any changes. [0080] To start the time period, the digital control unit 146 is configured to receive a trigger signal 160. The trigger signal 160 may be in an activation state or in a deactivation state. In this particular embodiment, the trigger signal 160 is a time slot initiation signal. The digital control unit 146 is configured to begin the time period in response to the trigger signal 160 being in the activation state. This signifies the beginning of the time slot.

[0081] When the mode value 158 is equal to one (1 ), the digital control unit 146 sets the pulse count integer to the initial value and performs a count operation in response to each one of the clock pulses of the clock signal 152. If the pulse ratio parameter 150 is equal to one (1 ), this means that the digital control unit 146 sets the time duration of the time period to approximately a first time slot size in response to the pulse ratio parameter being 1 . For example, the first time slot size may be equal to .5 milliseconds. The digital control unit 146 may also set the time duration to equal a second time slot size greater than the first time slot size in response to the pulse ratio parameter 150 being equal to two (2). For example, the second time slot size may be .667 milliseconds. The digital control unit 146 sets the time duration of the time period to approximately double the second time slot size in response to the pulse ratio parameter 150 being equal to four (4). Thus, in this example, the time duration will cover two time slots of .667 milliseconds. Between the time slots, the mode value 158 may be provided as two (2) in order for the accumulator 148 to hold its contents. After the time duration, whether .5 milliseconds, .667 milliseconds, or 2 X .667 milliseconds, the accumulator 148 adjusts the threshold parameter 66, and the updated threshold parameter 66 is provided for the next subsequent time slot.

[0082] Referring now to Figures 8A and 8B, Figure 8A has a noise curve 162 and a noise curve 164 as functions of the threshold parameter 66 when the target average frequency is 30 MHz. In particular, the noise curve 162 is provided when the noise adjustment selection bit 156 is equal to zero (0), while the noise curve 164 is provided when the noise adjustment selection bit 156 is equal to one (1 ). [0083] Figure 8B illustrates a first wideband noise power curve 166 and a second wideband noise power curve 168 as functions of frequency. Also shown is a transmission band 170 having a center frequency of 30 MHz and cut-off frequencies of around 30MHz ±4.5 MHz. The first wideband noise power curve 166 is provided when the noise adjustment selection bit 156 is equal to zero (0), and the second wideband noise power curve 168 is provided when the noise adjustment selection bit 156 is equal to one (1 ).

[0084] Figure 9 illustrates another embodiment of an AFC 46(2). The AFC 46(2) is similar to the AFC 46(1 ) shown in Figure 7. However, the count operation performed by a counter 144' is an increment operation that increments the pulse count integer. Thus, in this embodiment, the pulse count integer may be set to an initial value of zero (0). A digital control unit 146' is operable to receive the target average frequency value 18. In this embodiment, the digital control unit 146' is configured to calculate an upper limit for the final value of the pulse count integer based on the target average frequency value 18 and the pulse ratio parameter 150. Accordingly, given a tolerance, the digital control unit 146' calculates the upper limit for the final value. The digital control unit 146' is also configured to calculate a lower limit for the final value based on the target average frequency value 18 and the pulse ratio parameter 150. Given the tolerance, the final value for the pulse count integer should not be lower than a particular value. The clock generation circuit 142 generates the clock signal 152 such that the clock pulses of the clock signal 152 have the pulse ratio identified by the pulse ratio parameter 150 with respect to the pulses of the pulsed output voltage 16. The counter 144' performs the count operation on the pulse count integer, in this example, an increment operation, in response to each one of the clock pulses. Thus, in response to each clock pulse, the counter 144' is configured to increment the pulse count integer.

[0085] After the time period is over, the counter 144' is configured to generate a pulse count integer voltage 172 having a voltage level indicative of the final value. The digital control unit 146' is configured to generate an upper limit voltage 174 having a voltage level indicative of the upper limit for the final value. Additionally, the digital control unit 146' is configured to generate a lower limit voltage 176 having a voltage level indicative of the lower limit for the final value. The AFC 46(2) has a first comparator 178 configured to compare the upper limit voltage 174 and the pulse count integer voltage 172 so as to generate a first comparator signal 180. The first comparator signal 180 is in an activation state in response to the voltage level of the pulse count integer voltage 172 being greater than the voltage level of the upper limit voltage 174. The AFC 46(2) also includes a second comparator 182 configured to compare the lower limit voltage 176 and the pulse count integer voltage 172 so as to generate a second comparator signal 184. The second comparator signal 184 is in an activation state in response to the voltage level of the pulse count integer voltage 172 being lower than the voltage level of the lower limit voltage 176.

[0086] The accumulator 148' is configured to receive the threshold parameter 66, the first comparator signal 180, and the second comparator signal 184. If the first comparator signal 180 is in the activation state and the second comparator signal 184 is in the deactivation state, the accumulator 148' is configured to adjust the threshold parameter 66 by increasing the threshold parameter 66 by a step size in response to the first comparator signal 180 being in the activation state. If the second comparator signal 184 is in the activation state and the first comparator signal 180 is in the deactivation state, the accumulator 148' is configured to adjust the threshold parameter 66 by decreasing the threshold parameter 66 by a step size in response to the second comparator signal 184 being in the activation state. As in the previous embodiment described above with regard to Figure 7, the noise adjustment selection bit 156 may be used to select an integer size of the step size.

[0087] Figure 10 illustrates another embodiment of an AFC 46(3). The AFC 46(3) includes the same counter 144' described above with regard to Figure 9. As such, the counter 144' increments the pulse count trigger from an initial value in response to each of the clock pulses of the clock signal 152. However, in this embodiment of the AFC 46(3), the counter 144' outputs a pulse count integer 186 at the final value. The AFC 46(3) includes a subtractor 188 operable to receive the pulse count integer 186 at the final value. The subtractor 188 is configured to subtract the target average frequency value 18 from the final value of the pulse count integer 186 so as to generate a count error value 190.

[0088] In this embodiment, a digital control unit 146" is operable to receive a gain error parameter 192 that identifies a gain error. The digital control unit 146" provides the gain error parameter 192 to a multiplier 194. The multiplier 194 also receives the count error value 190 from the subtractor 188. The gain error parameter 192 identifies the gain error, which indicates a ratio of adjustment for the threshold parameter 66 with respect to the count error value 190. The multiplier 194 is configured to multiply the gain error parameter 192 with the count error value 190 so as to generate an error value 196.

[0089] An accumulator 148" is operable to receive the error value 196 from the multiplier 194. The accumulator 148" is configured to adjust the threshold parameter 66 by adding the error value 196 or a rounded value of the error value 196 to the threshold parameter 66. After updating the threshold parameter 66, the accumulator 148" provides the threshold parameter 66 to the BBC 44 (shown in Figure 3), as described above.

[0090] The switching controller 12 shown in Figure 3 is further configured to reduce the ripple variation in the supply voltage level of the supply voltage

VSUPPLY- One way of reducing the ripple variation is to increase the inductance of the power inductor 36. However, this would be detrimental to the operation of the RF switching converter 24 due to the large slew rate since the maximum current rate that the switching circuit 14 can deliver efficiently is limited by

(VpoWER - BUCK)/LpoWER INDUCTOR = dlpoWER INDUCTOR/dt.

[0091 ] Figure 1 1 illustrates one embodiment of the current sense detector 48 shown in Figure 3, along with a ripple current correction circuit 198 used to decrease the ripple variation in the VSUPPLY without requiring an increase of the inductance of the power inductor 36. In this embodiment, the switching controller 12 includes the current sense detector 48 and the ripple current correction circuit 198. However, it should be noted that in alternative embodiments, the current sense detector 48 and the ripple current correction circuit 198 may be provided in circuitry outside or external to the switching controller 12.

[0092] Referring again to Figure 1 1 , the RF filter 28 has a decoupling capacitor 200 coupled to receive the supply voltage VSUPPLY- The current sense detector 48 is configured to generate the current sense signal 70 having the sense signal level set so as to indicate a supply current level of a supply current 202 resulting from the supply voltage VSUPPLY- In this embodiment, the supply current 202 is the inductor current 40. The ripple current correction circuit 198 is configured to receive the current sense signal 70 from the current sense detector 48 and generate a ripple correction current 204. In this manner, ripple variation in the supply current level of the supply current 202 can be corrected without having to significantly increase the inductance of the power inductor 36.

[0093] For instance, the RF amplification circuit 26 (shown in Figure 2) has a non-zero and varying output impedance. Due to this non-linear output impedance, the ripple variation of both the supply current 202 and the supply voltage VSUPPLY can be significantly high without correction. In order to reduce the ripple variation of the supply current 202 (and therefore also reduce the ripple variation of the supply voltage VSUPPLY), the current sense detector 48 is configured to adjust the sense signal level of the current sense signal 70 in response to a change in the supply voltage level of the supply voltage VSUPPLY at the decoupling capacitor 200. Accordingly, the sense signal level of the current sense signal 70 is adjusted such that the sense signal level varies in accordance with the ripple variation of the supply voltage VSUPPLY, and thus as a result of the ripple variation of the supply current level of the supply current 202. In other words, the rippling supply voltage results in the ripple variation in the supply current level of the supply current 202, thereby resulting in rippling across the decoupling capacitor 200. Accordingly, the sense signal level of the current sense signal 70 ripples in accordance with the ripple variation and the supply current level of the supply current 202.

[0094] As shown in Figure 1 1 , the current sense detector 48 includes a comparator 206, a P-FET 208, an N-FET 210, and a feedback circuit 212. During the normal mode of operation, the P-FET 208 is switched on, while the N- FET 210 is switched off. The comparator 206 includes a non-inverting input terminal 214 configured to receive a supply control input voltage 218, an inverting input terminal 216 configured to receive the feedback voltage 72 from the feedback circuit 212, and an output terminal 222. The comparator 206 operates to maintain the voltage at a node N _C AP at the supply control voltage level of the supply control input voltage 218. More specifically, the comparator 206 is configured to generate a supply control output voltage 224 from the output terminal 222 based on the supply control input voltage 218 and the feedback voltage 72. If the supply control input voltage 21 8 and the feedback voltage 72 have unequal voltage levels, the comparator 206 drives the supply control output voltage 224 until the feedback voltage 72 at the inverting input terminal 216 is equal to the voltage level of the supply control input voltage 218 at the non- inverting input terminal 214. In turn, this results in a current being drawn across the P-FET 208. Since the decoupling capacitor 200 is coupled to the node N _C AP, the decoupling capacitor 200 is coupled to receive the supply control output voltage 224. The change in the supply control output voltage 224 results in a change in the current across the P-FET 208. The current across the P-FET 208 is tapped in order to provide the current sense signal 70 from the current sense detector 48.

[0095] The ripple current correction circuit 198 shown in Figure 1 1 is operable to receive the current sense signal 70, a pulsed feedback signal 226 based on the pulsed output voltage 16, and the supply control input voltage 218. From the pulsed feedback signal 226, the supply control input voltage 218, and the current sense signal 70, the ripple current correction circuit 198 estimates the supply current level of the supply current 202. More specifically, the ripple current correction circuit 198 has a current estimation circuit 228 coupled to receive the pulsed feedback signal 226, the supply control input voltage 218, and the current sense signal 70. Based on the pulsed feedback signal 226, the supply control input voltage 218, and the current sense signal 70, the current estimation circuit 228 is configured to generate an estimated current signal 230 that is estimated to be directly proportional to the sense current level of the current sense signal 70. The estimated current signal 230 is received at an inverting terminal 232 of a comparator 234. A non-inverting terminal 235 of the comparator 234 is coupled to ground, while an output terminal 236 of the comparator 234 is coupled between an N-FET 238 and a P-FET 240.

[0096] During ET high power mode operation, the N-FET 238 is switched off, and the P-FET 240 is switched on. Since the sense signal level of the current sense signal 70 varies in accordance with the ripple variation in the supply current level of the supply current 202, a signal level of the estimated current signal 230 also has ripple variation. Since the estimated current signal 230 is received at the inverting terminal 232 of the comparator 234, this results in the generation of a current across the P-FET 240, which is the ripple correction current 204.

[0097] The ripple current correction circuit 198 is coupled so as to inject the ripple correction current 204 into the decoupling capacitor 200 in order to filter the ripple correction current 204. In this embodiment, the decoupling capacitor 200 provides a high-pass filter with a stopband that extracts the high-frequency ripple current from the ripple correction current 204. The decoupling capacitor 200 outputs the ripple correction current 204 such that the ripple correction current 204 reduces the ripple variation in the supply current level of the supply current 202, and therefore also the ripple variation of the supply voltage VSUPPLY- In this particular embodiment, a node N _R | _P coupled between the N-FET 238 and the P-FET 240 is connected to the node N _C AP- The stopband, which in this case is a notch, provided by the decoupling capacitor 200 is centered at or near the signal frequency of the RF signal 30 (shown in Figure 2). By applying the ripple correction current 204, after filtering, the ripple correction current 204 reduces the ripple variation in the supply current level of the supply current 202. The ripple correction current 204 is generated as an estimated mirror of the supply current 202. However, filtering by the decoupling capacitor 200 only injects high frequency portions of the ripple correction current 204 to avoid degrading power efficiency. [0098] The RF switching converter 10 (shown in Figure 3) needs to meet stringent noise standards within a transmission band for the RF signal 30. For example, when fewer than twelve (12) Resource Blocks (RBs) are being utilized in the RF signal 30 (shown in Figure 2), the noise needs to be better than -138 dbm/Hz for LTE at a 30 MHz offset. In contrast, where the number of RBs is large, i.e., > twelve (12), noise only needs to be better than -120 dbm/Hz for LTE at a 30 MHz offset. Thus, some noise filtering can be sacrificed when the number of RBs is large. However, the greater the capacitance of the decoupling capacitor 200, the larger the currents drawn by the current sense detector 48. Accordingly, power efficiency is degraded by greater or larger capacitances at the decoupling capacitor 200. Consequently, it may be desirable to sacrifice some noise filtering when the number of RBs is large, in order to get better power efficiency. While this may not be done when the number of RBs is low, since the noise level requirements are stricter, noise filtering can be relaxed for a larger number of RBs.

[0099] As shown in Figure 1 1 , the switching controller 12 has a digital control unit 242 configured to receive an RB parameter 244 that indicates an integer number of RBs. The digital control unit 242 generates a control signal 246 in an activation state when the RB parameter 244 indicates that the integer number is less than an RB threshold value (i.e., twelve (12), in this example). However, the digital control unit 242 is configured to generate the control signal 246 in a deactivation state when the RB parameter 244 indicates that the integer number is greater than or equal to the RB threshold value (i.e., twelve (12), in this example). A switch 248 within a shunt-coupled circuit 250 is closed in response to the control signal 246 being provided in the activation state. In contrast, the switch 248 is opened in response to the control signal 246 being provided in the deactivation state.

[00100] The shunt-coupled circuit 250 shown in Figure 1 1 is included in the switching controller 12, and in this particular embodiment, the feedback circuit 212 includes the shunt-coupled circuit 250. [00101 ] The shunt-coupled circuit 250 has a second decoupling capacitor 252 and the switch 248. The switch 248 is coupled in series with the second decoupling capacitor 252, and is configured to be opened and closed, as explained above. The digital control unit 242 transmits the control signal 246 to the switch 248 so that the digital control unit 242 can open and close the switch 248 based on the RB parameter 244. When the RB parameter 244 indicates that the integer number of RBs is greater than or equal to the RB threshold value (i.e., twelve (12), in this example), noise level requirements are relaxed. Thus, a smaller capacitance may be used to increase power efficiency.

[00102] For example, the decoupling capacitor 200 has a first capacitance. The switch 248 is open in response to the RB parameter 244 indicating an integer number of RBs greater than the RB threshold value, and thus a second capacitance of the second decoupling capacitor 252 is not seen by the supply voltage VSUPPLY- The ripple correction current 204 is not further filtered by the second decoupling capacitor 252 when the switch 248 is open. In this case, noise filtering is sacrificed for greater power efficiency.

[00103] However, in the feedback circuit 212, the shunt-coupled circuit 250 is coupled in shunt with respect to the decoupling capacitor 200. Thus, when the switch 248 is closed, the second capacitance of the second decoupling capacitor 252 is added to the first capacitance of the decoupling capacitor 200. As such, the second decoupling capacitor 252 further filters the ripple correction current 204 when the switch 248 is closed. The switch 248 is closed when the RB parameter indicates that the integer number of RBs is less than the RB threshold value (i.e., twelve (12), in this example), and thus, power efficiency is sacrificed for greater noise filtering.

[00104] Referring now to Figures 5A, 6A, and 12, Figure 12 illustrates one embodiment of the VOL 50 that generates the offset voltage 68, as shown in Figure 3. The voltage magnitude VOFFS of the offset voltage 68 determines the center voltage level V _C EN- The ripple variation of the sense signal level of the current sense signal 124 oscillates from peak to peak about the center voltage level VCEN- To generate the current sense signal 124, the BBC 44 (shown in Figure 4) is configured to receive the current sense signal 70 from the current sense detector 48. The BBC 44 converts the current sense signal 70 into the preliminary voltage 1 04E (shown in Figure 4), and then the BBC 44 subtracts the voltage magnitude VOFFS of the offset voltage 68 from the preliminary voltage 1 04E to generate the current sense signal 1 24. Accordingly, adjusting the voltage magnitude VOFFS also adjusts the center voltage level V _C EN- This therefore results in the sense signal level of the current sense signal 1 24 reaching the first threshold voltage level M and the second threshold voltage level M ₂ at different points in the oscillation of the current sense signal 1 24.

[00105] Referring now specifically to Figures 5A and 6A, decreasing the voltage magnitude VOFFS lowers the center voltage level V _C EN SO that the current sense signal level of the current sense signal 1 24 reaches the first threshold voltage level Mi closer to a voltage peak maximum V _PE AKMAX _. The current sense signal level of the current sense signal 1 24 would reach the second threshold voltage level M ₂ further away from a voltage peak minimum V _PEA KMIN- (In Figure 6A, the current sense signal level of the current sense signal 1 24 also reaches the third threshold voltage level M ₃ and the fourth threshold voltage level M ₄ closer to the voltage peak maximum V _PEA KMAX-)

[00106] Note that while the first threshold voltage level M and the second threshold voltage level M ₂ (along with the third threshold voltage level M ₃ and the fourth threshold voltage level M ₄ ) are not adjusted by the offset voltage 68 in this embodiment, the relationship between the sense signal level of the current sense signal 1 24 and the sense signal level of the current sense signal 70 (shown in Figure 3) is modified by adjustments of the voltage magnitude VOFFS- For example, if the voltage magnitude VOFFS is increased, the center voltage level VCEN is raised. Thus, the current sense signal 1 24 reaches the first threshold voltage level M further away from the voltage peak maximum V _PE AKMAX, and reaches the second threshold voltage level M ₂ closer to the voltage peak minimum V _PEA KMIN.

[00107] Prior to the increase of the voltage magnitude VOFFS, the sense signal level of the current sense signal 1 24 is equal to the first threshold voltage level Mi and the sense signal level of the current sense signal 124 is equal to the second threshold voltage level M ₂ at particular values of the sense signal level of the current sense signal 70. However, when the voltage magnitude VOFFS is increased, the sense signal level of the current sense signal 124 equal to the first threshold voltage level Mi and the sense signal level of the current sense signal 124 equal to the second threshold voltage level M ₂ each correspond to different values of the sense signal level of the current sense signal 70. More specifically, the sense signal level of the current sense signal 124 equal to the current threshold voltage level Mi and the sense signal level of the current sense signal 124 equal to the second threshold voltage level M ₂ each correspond to lower values of the sense signal level of the current sense signal 70. As such, with regard to the sense signal level of the current sense signal 70, the threshold voltage levels M-i , M ₂ have been effectively lowered. Additionally, the pulse length of the pulse 140 would be decreased by increasing the voltage magnitude VOFFS- This thereby results in a decrease in the supply voltage level of the supply voltage V _SU PPLY-

[00108] Conversely, decreasing the voltage magnitude VOFFS results in the sense signal level of the current sense signal 124 equal to the first threshold voltage level M and the sense signal level of the current sense signal 124 equal to the second threshold voltage level M ₂ each corresponding to higher values of the sense signal level of the current sense signal 70. Additionally, this results in an increase of the pulse length of the pulse 140, and thereby an increase in the supply voltage level of the supply voltage VSUPPLY- Note that the same effect could be achieved by directly inputting the preliminary voltage 104E as the current sense signal into the comparators 80, 82, 84, and 86 (shown in Figure 4), while adding the offset voltage 68 to the first threshold signal 1 18, the second threshold signal 120, the third threshold signal 130, and the fourth threshold signal 134 (shown in Figure 4). However, the specific embodiment of the BBC 44 shown in Figure 4 reduces the number of adders required, since rather than adding the offset voltage directly to the threshold signals 1 18, 120, 130, 134, the offset voltage 68 is subtracted from the preliminary voltage 104E to generate the current sense signal 124.

[00109] Referring again to Figure 12, the current sense detector 48 generates the supply control output voltage 224, as explained above. The RF filter 28 is operable to apply the supply control output voltage 224 to the supply voltage

VSUPPLY such that the supply voltage level of the supply voltage VSUPPLY is biased by the supply control output voltage level of the supply control output voltage 224. Accordingly, the supply control output voltage level of the supply control output voltage 224 and the supply voltage level of the supply voltage VSUPPLY are displaced by a displacement voltage magnitude | V _D is| - In this embodiment, the supply control output voltage 224 is received by the decoupling capacitor 200 to bias the supply voltage VSUPPLY- Accordingly, this results in the displacement voltage magnitude |V _D is| across the decoupling capacitor 200.

[001 10] As described above, the BBC 44 (shown in Figure 4) is configured to receive the offset voltage 68, wherein adjustments to the voltage magnitude

VOFFS (shown in Figures 5A and 6A) adjust the pulse length of the pulses 140 (shown in Figure 5B). This thereby adjusts the supply voltage level of the supply voltage VSUPPLY- AS a result, the voltage magnitude VOFFS determines the displacement voltage magnitude |V _D is| between the supply control output voltage level of the supply control output voltage 224 and the supply voltage level of the supply voltage VSUPPLY- The BBC 44 is thus configured to switch the switching circuit 14 such that the displacement voltage magnitude |V _D is| is set in

accordance with the voltage magnitude VOFFS (shown in Figures 5A and 5B) of the offset voltage 68. The VOL 50 is configured to adjust the voltage magnitude VOFFS of the offset voltage 68 so that the displacement voltage magnitude |V _D is| is driven to a target displacement voltage magnitude. In this manner, voltage spurs in the supply voltage VSUPPLY and current spikes in the supply current 202 can be minimized or eliminated.

[001 1 1 ] In this embodiment, the VOL 50 adjusts the voltage magnitude VOFFS of the offset voltage 68 so that the displacement voltage magnitude |V _D is| appears almost as a constant DC voltage set at the target displacement voltage magnitude. The BBC 44 and, in particular, the digital control unit 74, are operable to receive a target displacement voltage parameter 254 that identifies the target displacement voltage magnitude. The digital control unit 74 of the BBC 44 is configured to generate a target displacement voltage signal 256 having a target displacement voltage level that is indicative of the target displacement voltage magnitude.

[00112] The VOL 50 shown in Figure 1 2 includes an adder 258 that receives the feedback voltage 72 having the feedback voltage level indicative of the supply voltage level. The adder 258 is also operable to receive a feedback voltage 260 indicative of the supply control output voltage level of the supply control output voltage 224. The adder 258 is configured to subtract the feedback voltage level of the feedback voltage 72 from the feedback voltage level of the feedback voltage 260 so as to generate a displacement indication voltage 262 having a voltage magnitude indicative of the displacement voltage magnitude |V _D is|.

[00113] The VOL 50 also includes an adder 264. The adder 264 is operable to receive the target displacement voltage signal 256 from the BBC 44 and the displacement indication voltage 262 from the adder 258. The adder 264 subtracts the voltage level of the displacement indication voltage 262 from the target displacement voltage level of the target displacement voltage signal 256 so as to generate an error voltage 266 with an error voltage magnitude indicative of a difference between the displacement voltage magnitude |V _D is| and the target displacement voltage magnitude.

[00114] As shown in Figure 1 2, the VOL 50 includes an integrator circuit 268 configured to receive the error voltage 266. The integrator circuit 268 provides and integration function over time, such that the voltage magnitude VOFFS of the offset voltage 68 is adjusted so long as the error magnitude of the error voltage 266 indicates that the displacement voltage magnitude |V _D is| is different from the target displacement voltage magnitude. For example, if the error voltage magnitude is not zero, integration will continue. On the other hand, the voltage magnitude VQFFS of the offset voltage 68 changes the supply voltage level of the supply voltage VSUPPLY until the displacement voltage magnitude |V _D is| is approximately equal to the target displacement voltage magnitude. By driving the displacement voltage magnitude | V _D is| to the target displacement voltage magnitude, spurs in the supply voltage level of the supply voltage VSUPPLY and spikes in the supply current level of the supply current 202 can be minimized.

[00115] In one embodiment, the integrator circuit 268 has a transfer function of:

-(I+TI *S) _^ transfer function thus not only has a pole, but also has a zero to

(X2*S)

help stabilize the VOL 50. The pole and the zero can be adjusted by modifying the values of τ and τ ₂ . These values may be modified by adjusting reactive impedance levels of reactive components provided by the integrator circuit 268. Also, modulation for ET can be provided by modulating the supply control input voltage level of the supply control input voltage 218.

[001 16] Figure 13 illustrates one embodiment of the supply voltage VSUPPLY, the supply control output voltage 224, and the displacement voltage magnitude |V _D is| as a function of time, while providing ET. Accordingly, the supply voltage level of the supply voltage VSUPPLY and the supply control output voltage level of the supply control output voltage 224 are modulated. As shown in Figure 13, the VOL 50 (shown in Figure 12) maintains the displacement voltage magnitude I V _D is| relatively steady and virtually DC at a target displacement voltage magnitude |V _TA RGET|-

[001 17] Figure 14 illustrates one embodiment of an RF power converter 270 configured to generate the supply voltage VSUPPLY- The RF power converter 270 includes an RF switching converter 24', an LDO regulation circuit 272, interface circuitry 274, and an operational mode controller 276. The RF switching converter 24' shown in Figure 14 includes a switching controller 12' and the switching circuit 14 described above. In this embodiment, the switching controller 12' includes the BBC 44, the AFC 46(1 ), the VOL 50, the current sense detector 48, and the ripple current correction circuit 198 described above with respect to Figures 3, 4, 7, 1 1 , and 12. Additionally, the switching controller 12' includes an APT controller 278 configured to generate an APT signal 280 for APT, as described below. As mentioned above, the RF switching converter 24' also includes the switching circuit 14 described above with respect to Figure 3. An RF filter 282 is configured to convert the pulsed output voltage 16 from the switching circuit 14 into the supply voltage VSUPPLY, and to bias the supply voltage VSUPPLY with the supply control output voltage 224 from the current sense detector 48. Additionally, the RF filter 282 includes an additional inductor 284 coupled in series with the power inductor 36, a switch 286, a notch filter 288, and a switch 290. The inductor 284 typically has a small inductance with respect to the power inductor 36. For example, the power inductor 36 may have an inductance of around 0.5-1 .5 microhenries (μΗ), while the inductor 284 may have an inductance of around 3.0-7.0 nanohenries (nH). In this manner, the supply control output voltage 224 and the feedback voltage 72 may be slightly time- advanced, thereby reducing the effects of loop delay in the switching controller 12'.

[001 18] As described above, the current sense detector 48 is configured to receive the supply control input voltage 218 having the supply control input voltage level modulated to provide ET. The notch filter 288 provides a notch and may be an LC-type RF filter configured to filter the ripple variation of the supply voltage VSUPPLY- Furthermore, the notch filter 288 may reduce an impedance relative to the supply current 202, which is also modulated during ET. However, the notch filter 288 may need to be disabled via the switch 290 when the supply voltage VSUPPLY is operating with over 30 RBs in order to avoid degrading the modulation of the supply voltage VSUPPLY and the supply current 202.

[001 19] During APT, the supply voltage VSUPPLY and the supply current 202 are not modulated. In this case, as explained below, either the APT controller 278 may be used to control the BBC 44 or the LDO regulation circuit 272 may be configured to generate the supply voltage VSUPPLY- The APT controller 278 is configured to generate the APT signal 280. The APT signal 280, which in this example is a voltage, takes the place of the current sense signal 70 so that the APT signal 280 is compared with the thresholds instead of the current sense signal 70 as described above with respect to Figure 4. The BBC 44 is operable to receive the APT signal 280 having the APT signal level, and is configured to switch the switching circuit 14 based on the APT signal level of the APT signal 280 so as to generate the pulsed output voltage 16 when the APT controller 278 is activated. In contrast, if the LDO regulation circuit 272 is used, the LDO regulation circuit 272 sets an average DC supply voltage level of the supply voltage VSUPPLY in accordance with the supply control input voltage level of the supply control input voltage 218.

[00120] The BBC 44 shown in Figure 14 is operable to be activated and deactivated, and the LDO regulation circuit 272 is also operable to be activated and deactivated. When the LDO regulation circuit 272 is activated, the LDO regulation circuit 272, not the RF power converter 24', is configured to generate the supply voltage VSUPPLY- More specifically, the RF filter 282 is coupled to receive the pulsed output voltage 16 from the switching circuit 14 and the supply voltage VSUPPLY from the LDO regulation circuit 272. The RF filter 282 is operable to alternate between a first RF filter topology and a second RF filter topology depending on whether the BBC 44 is activated or the LDO regulation circuit 272 is activated. The RF filter 282 in the first filter topology is configured to convert the pulsed output voltage 16 from the switching circuit 14 into the supply voltage VSUPPLY- Furthermore, in this embodiment, the switch 286 is open in the first RF filter topology, so that the supply control output voltage 224 and the ripple correction current 204 can be applied through the decoupling capacitor 200. However, when the BBC 44 is deactivated, the LDO regulation circuit 272 may be activated to generate the supply voltage VSUPPLY- In this case, the RF filter 282 in the second RF filter topology is configured to filter the supply voltage VSUPPLY from the LDO regulation circuit 272 to reduce a ripple variation in the supply voltage level of the supply voltage VSUPPLY- In particular, the switch 286 may be closed, so that the decoupling capacitor 200 is operable to passively filter the supply voltage VSUPPLY from the LDO regulation circuit 272. When the switch 286 is closed, the passive filtering from the decoupling capacitor 200 reduces the ripple variation in the supply voltage level of the supply voltage VSUPPLY _.

[00121 ] In this embodiment, the BBC 44, the APT controller 278, the VOL 50, the current sense detector 48, the AFC 46(1 ), the ripple current correction circuit 198, and the LDO regulation circuit 272 are each operable to be activated and deactivated. The operational mode controller 276 is configured to activate and deactivate the BBC 44, the APT controller 278, the VOL 50, the current sense detector 48, the AFC 46(1 ), the ripple current correction circuit 198, and the LDO regulation circuit 272 so that the RF power converter 270 operates in different operational modes. For example, the operational mode controller 276 may be operable to set the RF power converter 270 in a first operational mode, a second operational mode, a third operational mode, and a fourth operational mode. The first operational mode and the second operational mode may be for ET, while the third operational mode and the fourth operational mode may be for APT.

[00122] The first operational mode may be a high-power ET mode. In the high- power ET mode, the APT controller 278 and the LDO regulation circuit 272 are deactivated by the operational mode controller 276. The operational mode controller 276 is configured to provide the BBC 44, the VOL 50, the ripple current correction circuit 198, and the current sense detector 48, such that each is activated. The operational mode controller 276 is further operable to provide the RF filter 282 in the first RF filter topology by closing the switch 286 and the switch 290.

[00123] As shown in Figure 14, the switch 286 is provided in a switchable ground path 292. Activating the switch 286 closes the switchable ground path

292, while deactivating the switch 286 opens the switchable ground path 292.

The operational mode controller 276 is also configured to deactivate the switch

286 and open the switchable ground path 292 to provide the RF filter 282 in the first RF filter topology. To provide the RF filter 282 in the first RF filter topology, the switch 290 also forms a switchable ground path 294. The operational mode controller 276 is configured to activate the switch 290, which closes the switchable ground path 294.

[00124] The switchable ground path 292 is coupled in shunt between the ripple current correction circuit 198 and the decoupling capacitor 200. Thus, the ripple current correction circuit 198 is coupled so as to inject the ripple correction current 204 into the decoupling capacitor 200 when the switchable ground path 292 is open. The decoupling capacitor 200 is further operable to filter the ripple correction current 204. The decoupling capacitor 200 outputs the ripple correction current 204 such that the ripple correction current 204 reduces the ripple variation in the supply current level of the supply current 202 that results from the supply voltage VSUPPLY- Similarly, when the switchable ground path 292 is open, the current sense detector 48 biases the supply voltage VSUPPLY with the supply control output voltage 224. Furthermore, the operational mode controller 276 holds the P-FET 240 in the on state and holds the N-FET 238 in the off state.

[00125] In the high-power ET mode, the current sense signal 70 is provided to the BBC 44, and the BBC 44 is configured to switch the switching circuit 14 based on the sense signal level of the current sense signal 70 so as to generate the pulsed output voltage 16 when the current sense detector 48 is activated by the operational mode controller 276. The APT controller 278 is deactivated, and thus does not provide the APT signal 280 to the BBC 44. The BBC 44 is further configured to receive the offset voltage 68 having the offset voltage magnitude and to switch the switching circuit 14 such that the displacement voltage magnitude |V _D is| (shown in Figure 12) is set in accordance with the offset voltage magnitude of the offset voltage 68 when the VOL 50 is activated.

[00126] The second operational mode is a medium-power ET mode. The operational mode controller 276 is configured to set the RF power converter 270 in the same manner as described above with respect to the high-power ET mode, except that in the medium-power ET mode, the ripple current correction circuit 198 is deactivated. Accordingly, in the second operational mode, the ripple variation of the supply voltage VSUPPLY is reduced entirely by the notch filter 288, since the switchable ground path 294 remains closed. Also, the supply control output voltage 224 continues to bias the supply voltage VSUPPLY- [00127] As shown in Figure 14, the interface circuitry 274 receives a

preliminary differential control signal 296. In both the high-power ET mode and the medium-power ET mode, the operational mode controller 276 sets the interface circuitry 274 so that the interface circuitry 274 converts the preliminary differential control signal 296 into the single-ended supply control input voltage 218. Also, during ET, the preliminary differential control signal 296 is modulated and the interface circuitry 274 is set by the operational mode controller 276 to provide pre-distortion and anti-alias filtering. The interface circuitry 274 provides the supply control input voltage 218 to the current sense detector 48 so as to drive the supply control output voltage 224.

[00128] The third operational mode is a medium-power APT mode. In the medium-power APT mode, the switching controller 12' continues to switch the switching circuit 14 to generate the pulsed output voltage 16 so that the RF filter 282 converts the pulsed output voltage 16 into the supply voltage VSUPPLY- In this embodiment, the RF filter 282 is further operable to be alternated to a third RF filter topology. During the medium-power APT mode, the operational mode controller 276 provides the RF filter 282 in the third RF filter topology while the switching controller 12' is activated. More specifically, the operational mode controller 276 provides the RF power converter 270 such that the BBC 44, the AFC 46(1 ), the APT controller 278, the switch 286, and the switch 290 are all activated during the medium-power APT mode. Additionally, the operational mode controller 276 deactivates the VOL 50, the ripple current correction circuit 198, the current sense detector 48, and the LDO regulation circuit 272. Thus, the RF filter 282 is provided in the third RF filter topology when the switchable ground path 292 and the switchable ground path 294 are each closed while the switching controller 12' is activated. In contrast, during the high-power ET mode and the medium-power ET mode, the RF filter 282 is provided in the first RF filter topology when the switchable ground path 292 is open and the switchable ground path 294 is closed while the switching controller 12' is activated. The operational mode controller 276 may further hold the P-FET 240 in the off state and hold the N-FET 238 in the on state while the current sense detector 48 is deactivated.

[00129] The decoupling capacitor 200 and the notch filter 288 are thus each operable to passively filter the supply voltage VSUPPLY converted from the pulsed output voltage 16, which was generated by the switching circuit 14, when the RF filter 282 is in the third RF filter topology. The decoupling capacitor 200 is thus coupled in shunt with respect to external downstream circuitry (such as, for example, the RF amplification circuit 26 shown in Figure 2). In this case, the preliminary differential control signal 296 is not modulated and the operational mode controller 276 simply configures the interface circuitry 274 so that the interface circuitry 274 converts the preliminary differential control signal 296 into the single-ended supply control input voltage 218. Since the current sense detector 48 is deactivated and the switch 286 is activated, the current sense detector 48 is no longer biasing the supply voltage VSUPPLY- Instead, the supply control input voltage level of the supply control input voltage 218 is unmodulated for APT and is indicative of a target average DC voltage level.

[00130] In the medium-power APT mode, the APT controller 278 is also configured to receive the feedback voltage 72 having the feedback voltage level indicative of the supply voltage level of the supply voltage VSUPPLY from the feedback circuit 212 and the supply control input voltage 218 from the interface circuitry 274. As mentioned above, the BBC 44 is operable to receive the APT signal 280, which takes the place of the current sense signal 70. Thus, the BBC 44 may include a multiplexer (not shown) to select whether the current sense signal 70 or the APT signal 280 are to be used. Since the BBC 44 uses the APT signal 280 in the medium-power APT mode, the BBC 44 is configured to switch the switching circuit 14 based on the APT signal level of the APT signal 280 so as to generate the pulsed output voltage 16 when the APT controller 278 is activated. Again, the feedback voltage level of the feedback voltage 72 is indicative of the supply voltage level of the supply voltage VSUPPLY- The APT controller 278 is configured to adjust the APT signal level to drive the feedback voltage level of the feedback voltage 72 to the supply control input voltage level of the supply control input voltage 218. In this manner, the pulsed output voltage 16 is generated by the switching circuit 14 so as to provide an average DC supply voltage level of the supply voltage VSUPPLY approximately at the target average DC voltage level indicated by the supply control input voltage level of the supply control input voltage 218. [00131 ] The switching controller 12' and the switching circuit 14 should be used to generate the supply voltage VSUPPLY SO long as the power source voltage level of the power source voltage V _PO WER is high enough to provide adequate headroom to the P-FET 52 and the N-FET 54. Once the power source voltage level cannot provide adequate headroom, the operational mode controller 276 may be configured to provide the RF power converter 270 in the fourth operational mode. Thus, the fourth operational mode is a low-power APT mode. In the low-power APT mode, the operational mode controller 276 is configured to provide the RF power converter 270 such that the BBC 44, the APT controller 278, the VOL 50, the ripple current correction circuit 198, and the current sense detector 48 are each deactivated. The operational mode controller 276 provides the LDO regulation circuit 272 such that the LDO regulation circuit 272 is activated. The P-FET 240 and the N-FET 238 are maintained in the off state and the on state, respectively. In addition, the BBC 44 is configured to hold the P- FET 52 in the off state and hold the N-FET 54 in the on state when the BBC 44 is deactivated, such that the switching circuit 14 and the power inductor 36 form a ground path. The RF filter 282 is provided in the second RF filter topology during the low-power APT mode. More specifically, the power mode controller 276 provides the RF filter 282 so that the switch 286 is activated, the switch 290 is deactivated, and such that the power inductor 36 and the switching circuit 14 form a ground path. Accordingly, the switchable ground path 292 is closed, the switchable ground path 294 is open, and the switching circuit 14 and the power inductor 36 form the ground path in the second RF filter topology of the RF filter 282.

[00132] The LDO regulation circuit 272 is configured to generate the supply voltage VSUPPLY when the LDO regulation circuit 272 is activated. The RF filter 282 in the second RF filter topology is configured to filter the supply voltage

VSUPPLY from the LDO regulation circuit 272 to reduce a ripple variation in the supply voltage level of the supply voltage VSUPPLY- More specifically, the switchable ground path 292 is closed in the second RF filter topology, and thus the decoupling capacitor 200 is configured to passively filter the supply voltage VSUPPLY to reduce the ripple variation in the supply voltage level of the supply voltage VSUPPLY. The switchable ground path 294 is open, and thus the notch filter 288 does not filter the supply voltage VSUPPLY, since at backed-off power levels, the notch filter 288 may cause excessive distortion.

[00133] In this embodiment, the LDO regulation circuit 272 is configured to generate the supply voltage VSUPPLY from a charge pump voltage VCHARGE when the LDO regulation circuit 272 is activated. A charge pump 298 is operable to provide an adjustable voltage ratio. More specifically, the charge pump 298 is configured to generate the charge pump voltage VCHARGE from the power source voltage V _PO WER such that an average DC voltage level of the charge pump voltage VCHARGE has the adjustable voltage ratio with respect to a power source voltage level of the power source voltage V _PO WER- For example, the charge pump 298 may be able to provide the adjustable voltage ratio at 1 /3 or 1 /4.

When the adjustable voltage ratio is 1 /3, the charge pump 298 provides the average DC voltage level of the charge pump voltage VCHARGE at 1 /3 the power source voltage level of the power source voltage V _PO WER- In contrast, when the adjustable voltage ratio is set to 1 /4, the average DC voltage level of the charge pump voltage VCHARGE may be at 1 /4 the power source voltage level of the power source voltage V _PO WER- [00134] Since the charge pump voltage VCHARGE is generated by the charge pump 298, a charge pump voltage level of the charge pump voltage VCHARGE has a ripple variation, thereby resulting in a ripple variation of the supply voltage

VSUPPLY provided by the LDO regulation circuit 272. The charge pump 298 may include an oscillator 300 used to time the switching of the switches in the charge pump 298. The adjustable voltage ratio may be set to 1 /3 or 1 /4 by adjusting the pulse frequency of the clock signal generated by the oscillator 300.

[00135] As shown in Figure 14, the LDO regulation circuit 272 includes a comparator 302 and a voltage regulator, which in this example is a P-FET 304. The comparator 302 receives the supply control input voltage 218 from the interface circuitry 274 and the feedback voltage 72 from the feedback circuit 212. The comparator 302 may be configured to drive the P-FET 304 so that the feedback voltage level of the feedback voltage 72 is approximately equal to the supply control input voltage level of the supply control input voltage 218. This causes the supply voltage level of the supply voltage VSUPPLY to be adjusted. The amount of adjustment of the supply voltage level of the supply voltage VSUPPLY depends on the amount of adjustment required to drive the feedback signal voltage of the feedback voltage 72 so that the feedback voltage level is approximately equal to the supply control input voltage level of the supply control input voltage 218.

[00136] So long as the P-FET 304 is not saturated, the comparator 302 drives the P-FET 304 to resist the change and therefore resist the ripple variation from the charge pump voltage VCHARGE- By being coupled to ground, the decoupling capacitor 200 further reduces the ripple variation in the supply voltage level of the supply voltage VSUPPLY by filtering the supply voltage VSUPPLY- [00137] Figure 15 illustrates a circuit diagram of the LDO regulation circuit 272, the charge pump 298, and the RF filter 282 during the low-power APT mode. A capacitance C _PA R represents the parasitic capacitance of the N-FET 54. Both the capacitance CPAR and the inductance of the power inductor 36 are relatively high, and thus have little effect on the output impedance of the RF filter 282. A resistance R _S w represents an equivalent resistance of the N-FET 238 and the switchable ground path 292 when the switchable ground path 292 is closed and the N-FET 238 is held in the on state. As such, the N-FET 238 and the switchable ground path 292 are parallel and the resistance Rsw is decreased. Furthermore, the inductance of the inductor 284 is very small. As such, the output impedance is mainly set by the decoupling capacitor 200 and the parasitic resistance Rsw, which has been lowered by holding the N-FET 238 in the off state.

[00138] Referring now to Figures 14 and 16, Figure 16 is a graph illustrating system efficiency versus a target average power value. The operational mode controller 276 is configured to obtain a target average power output parameter 306 shown in Figure 14 that identifies the target average power output value for the RF power converter 270. The operational mode controller 276 is configured to select between the first operational mode, the second operational mode, the third operational mode, and the fourth operational mode based on the target average power output value identified by the target average power output parameter 306.

[00139] As shown in Figure 16, the operational mode controller 276 is configured to select the first operational mode (i.e., the high-power ET mode) when the target average power output value identified by the target average power output parameter 306 is above a threshold value 308. At a maximum target average power output value 310, the RF power converter 270 is at 100% system efficiency and cannot provide additional power. Once the target average power output value is below the threshold value 308, the operational mode controller 276 selects the second operational mode (i.e., the medium-power ET mode). As such, the supply voltage VSUPPLY continues to be modulated, but the ripple current correction circuit 198 is deactivated.

[00140] At a certain point, ET becomes inefficient in comparison to APT because although ET can reach higher system efficiency faster, it also decreases at a faster rate than APT. This point can be approximated to be at a threshold value 312, which is below the threshold value 308. When the operational mode controller 276 obtains the target average power output parameter 306 identifying a target average power output value below the threshold value 312, the operational mode controller 276 selects the third operational mode (i.e., the medium-power APT mode). As such, the BBC 44 and the switching circuit 14 continue to generate the pulsed output voltage 16 for conversion into the supply voltage VSUPPLY- The third operational mode is selected so long as the RF switching converter 24' can provide the pulsed output voltage 16 at a level that is greater than the power source voltage level of the power source voltage V POWER- This no longer becomes the case at a threshold value 314, which is below the threshold value 312, the threshold value 308, and the maximum target average power output value 310.

[00141 ] The operational mode controller 276 is configured to select the fourth operational mode (i.e., the low-power APT mode) when the target average power output value identified by the target average power output parameter 306 is below the threshold value 314. In this case, the LDO regulation circuit 272 is activated to generate the supply voltage VSUPPLY- From the threshold value 314 to a threshold value 316, the adjustable voltage ratio of the charge pump 298 is set to 1 /3. The operational mode controller 276 is configured to set the adjustable voltage ratio of the charge pump 298 to 1 /4 when the target average power output value identified by the target average power output parameter 306 is below the threshold value 316.

[00142] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.