Title:
RFIC MODULE AND RFID TAG EQUIPPED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2016/084658
Kind Code:
A1
Abstract:
In the present invention, an RFIC chip 16 has a first input/output terminal 16a and a second input/output terminal 16b, and is built into a multilayered substrate. A feeder circuit 18 includes coil conductors 20a to 20c, and is built into the multilayered substrate. The coil conductor 20a has one end (a first coil end) that is connected to the first input/output terminal 16a, and the coil conductor 20b has one end (a second coil end) that is connected to the second input/output terminal 16b. A first terminal electrode 14a and a second terminal electrode 14b are respectively connected to the other end (a first position) of the coil conductor 20a and to the other end (a second position) of the coil conductor 20b. A first coil part CIL1 exists in a section from the first coil end to the first position, and a second coil part exists in a section from the second coil end to the second position. The RFIC chip 16 is interposed between the first coil part CIL1 and the second coil part CIL2, in a plan view of the multilayered substrate.
Inventors:
KATO NOBORU (JP)
KOMAKI KUNIHIRO (JP)
KOMAKI KUNIHIRO (JP)
Application Number:
PCT/JP2015/082287
Publication Date:
June 02, 2016
Filing Date:
November 17, 2015
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
G06K19/077; G06K19/07; H01F17/00; H01Q1/40; H01Q7/00; H01Q9/16
Domestic Patent References:
| WO2012096365A1 | 2012-07-19 | |||
| WO2011055702A1 | 2011-05-12 |
Foreign References:
| JP2009080843A | 2009-04-16 | |||
| JP2012085306A | 2012-04-26 |
Other References:
See also references of EP 3176734A4
Attorney, Agent or Firm:
SAKAI, MASATOSHI (JP)
Boundary Masatoshi (JP)
Boundary Masatoshi (JP)
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