ROUTER AND CHIP CIRCUIT

WIPO Patent Application WO/2011/142087

A1

Disclosed is a router which achieves power saving transmission even if traffic of various delay requests is present together in a Network on Chip (NoC). The router is used in a data transmission system provided with a first node for sending data, a second node for receiving data sent from the first node, and a plurality of routers for routing data that are transmitted between the first and second nodes. The router is provided with a load value processing unit for acquiring information of a load value in another router which is connected to a communication bus; and an aggregate assessment unit for aggregating into a transmission path over which a plurality of signals of traffic are transmitted and/or into a destination of data of the plurality of signals of the traffic, according to transmission quality requested for each signal of the traffic, on the basis of information of a load value acquired from each router while the plurality of signals of the traffic are being generated.

YAMAGUCHI TAKAO
YOSHIDA ATSUSHI
ISHII TOMOKI

PCT/JP2011/002356

November 17, 2011

April 22, 2011

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PANASONIC CORP (JP)
YAMAGUCHI TAKAO
YOSHIDA ATSUSHI
ISHII TOMOKI

G06F13/36; G06F13/14; H01L21/822; H01L27/04; H04L12/56

WO2009150849A1

2009-12-17

JP2010161501A	2010-07-22
JP2007528177A	2007-10-04

DAISUKE ARAI ET AL.: "Proposal on ECO-friendly Distributed Routing Protocol for Reducing Network Energy Consumption", IEICE TECHNICAL REPORT, vol. 109, no. 411, 28 January 2010 (2010-01-28), pages 17 - 22
JOHN KIM: "Low-Cost Router Microarchitecture for On-Chip Network", MICRO'09, 12 December 2009 (2009-12-12)

OKUDA, SEIJI (JP)
Seiji Okuda (JP)

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